coreboot-gerrit November 2021

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 29: (7 comments) File src/ec/starlabs/merlin/ec.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/087eba2e_5e9f8e2e PS29, Line 247: { NULL, ITE_SMFI, PNP_IRQ0, 0xfff0, }, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/40b50dda_13753166 PS29, Line 250: /* Power Mangement I/F Channel 1 (PMC1) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/1f2c0383_8978e8c5 PS29, Line 252: /* Power Mangement I/F Channel 2 (PMC2) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/f1d6956a_09a3d272 PS29, Line 258: /* Power Mangement I/F Channel 3 (PMC3) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/1f2b2904_7222fa8b PS29, Line 260: /* Power Mangement I/F Channel 4 (PMC4) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/1c12903b_c8e3a509 PS29, Line 262: /* Power Mangement I/F Channel 5 (PMC5) */ 'Mangement' may be misspelled - perhaps 'Management'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133032): https://review.coreboot.org/c/coreboot/+/58343/comment/0dec4382_dbbfabc3 PS29, Line 274: }; adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 29 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP soc: Added dram information to cbmem WIP
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59195 ) Change subject: WIP soc: Added dram information to cbmem WIP ...................................................................... Patch Set 1: (80 comments) File src/soc/qualcomm/common/qclib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/fae039a8_0a379c78 PS1, Line 27: #if TEST_CODE /* Added this structure for testing purpose, will be remove once changes are reviewd */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/e3ab2d15_7c6dc4e2 PS1, Line 30: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/27ac3bde_bf8aaa6b PS1, Line 31: uint64_t type; // enum that differentiates DDR3, LPDDR3, LPDDR4, etc. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/8359daa1_333391b0 PS1, Line 32: uint64_t num_channels; // To know how may channels are available. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/3b3e421f_4a9036ea PS1, Line 33: uint64_t reserved[6]; // Reserved [6] please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/851d6bfa_b4b2a7fc PS1, Line 34: struct please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/53bbbadc_5b6207a1 PS1, Line 35: { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/91da5399_865e0c64 PS1, Line 35: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/ec7d334b_f91cc901 PS1, Line 36: uint64_t density; // Total density Seen on channel code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/1673a5ab_aa5fce0d PS1, Line 36: uint64_t density; // Total density Seen on channel please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/02ead1b1_ef29502a PS1, Line 37: uint64_t io_width; // JEDEC MR8 - io width code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/3b881acd_5d83e3af PS1, Line 37: uint64_t io_width; // JEDEC MR8 - io width please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/825aec77_9a58d3eb PS1, Line 38: uint64_t manufacturer_id; // JEDEC MR5 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/206a19d7_0bd5c073 PS1, Line 38: uint64_t manufacturer_id; // JEDEC MR5 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/321a0e26_1e6571ee PS1, Line 39: uint64_t revision_id[2]; // JEDEC MR6, MR7 code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/6862f096_84a04760 PS1, Line 39: uint64_t revision_id[2]; // JEDEC MR6, MR7 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/6e4b1a2d_1e884861 PS1, Line 40: uint64_t reserved[4]; // Reserved code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/df2ebca9_8cc6c1c3 PS1, Line 40: uint64_t reserved[4]; // Reserved please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/104c77a1_a6a0f2c2 PS1, Line 41: uint64_t serial_id[8]; // for potential future LPDDR5 expansion code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/71a23342_a96e856e PS1, Line 41: uint64_t serial_id[8]; // for potential future LPDDR5 expansion please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/707fee58_ea7a6525 PS1, Line 42: } channels[DDR_MAX_NUM_CH_TEST]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/01cdb3e8_d6794858 PS1, Line 43: }dram_info; space required after that close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/47391b56_3341e6ce PS1, Line 48: /* Save MEM CHIP info in SRAM region to share with ramstage */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/b43b885c_315dea76 PS1, Line 49: mem_chip_offset = (void *)te->blob_address; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/e3bb96ae_561c3307 PS1, Line 49: mem_chip_offset = (void *)te->blob_address; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/d7413119_1235c1bd PS1, Line 50: mem_chip_size = te->size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a033afcd_e8bcfd22 PS1, Line 50: mem_chip_size = te->size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a56fe37d_2c56fd40 PS1, Line 55: printk(BIOS_INFO, "%s:%s: Test Code to print memchip information before adding cbmem_add\n", __FILE__, __func__); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/01d6915d_fc10ed14 PS1, Line 56: memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/6d6b193c_1c3b5cf3 PS1, Line 56: memcpy(&memchip, (struct dram_info *)te->blob_address, sizeof(memchip)); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/4b7d7fb4_83308f0f PS1, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/7e3fe7fd_da6f2dac PS1, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/0e724200_2d62dbd8 PS1, Line 57: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)te->blob_address, (int)mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/cf455f2f_ccfce561 PS1, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/cfd33e12_12eef5c8 PS1, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/b81a78d6_e322de4b PS1, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/ba7a642a_b77b5bd7 PS1, Line 58: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/e6e2eaf4_586157ba PS1, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/1c198298_75d1e049 PS1, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/7a99bc08_19aa204e PS1, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/5cad7504_8f03671e PS1, Line 59: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/05b810fc_38f52b28 PS1, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/ff551c12_48beeb63 PS1, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/7f79f89c_96ae44df PS1, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/28c7981a_fbe20658 PS1, Line 60: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/40cdb1c9_6f6f2490 PS1, Line 66: void *mem_region_base; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/e40bace1_84e2857b PS1, Line 66: void *mem_region_base; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/0df03514_415da94a PS1, Line 69: mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a18b5e83_8e23cd21 PS1, Line 69: mem_region_base = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/99601c41_9d38b33d PS1, Line 70: ASSERT(mem_region_base != NULL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/e3843c3c_9cb5f26b PS1, Line 70: ASSERT(mem_region_base != NULL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/17cecb21_7693c71f PS1, Line 72: /* Migrate the data into CBMEM */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/58fe8cfa_99b6b446 PS1, Line 73: memcpy(mem_region_base, mem_chip_offset, mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/618b6b39_14e2e1f7 PS1, Line 73: memcpy(mem_region_base, mem_chip_offset, mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/ed1c0e7a_02eb2a5f PS1, Line 77: /* Test Code to print memchip information after adding cbmem_addd */ 'addd' may be misspelled - perhaps 'add'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/013dbf91_003d0eb8 PS1, Line 78: printk(BIOS_INFO, "%s:%s: Test Code to print memchip information after adding cbmem_add\n", __FILE__, __func__); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/d4267af6_971d4257 PS1, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/60847b5a_8fa5d3eb PS1, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/051dc19c_186fcbf5 PS1, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/4518ffef_33d323bd PS1, Line 80: printk(BIOS_INFO, "COREBOOT: MEM CHIP region offset: %p, size: %d\n", (void *)mem_region_base , (int)mem_chip_size); space prohibited before that ',' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/80505a27_ba03ea3a PS1, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/1e9309a4_f3c6dbb9 PS1, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/ef8e188c_c885a029 PS1, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a4a4fbec_3b107a9c PS1, Line 81: printk(BIOS_INFO, "COREBOOT: %s : %s : line:%d MEM CHIP : manufacturee_id : %lld \n", __FILE__, __func__, __LINE__, memchip.channels[0].manufacturer_id); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/da93b019_8468a704 PS1, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/b849a26c_346e7cb2 PS1, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/5f5031e1_581148b6 PS1, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/9128cd80_a535669c PS1, Line 82: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : density : %lld \n", __FILE__, __func__, memchip.channels[0].io_width); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a4431cad_0885e31a PS1, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/dfdaf51f_eb6ab805 PS1, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/ed1adaf9_6fc6ffaa PS1, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/4f7d98a6_970d2f38 PS1, Line 83: printk(BIOS_INFO, "COREBOOT: %s : %s : MEM CHIP : io-width : %lld \n", __FILE__, __func__, memchip.channels[0].density); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/9b252f95_1679eaa7 PS1, Line 157: sizeof(te->name))) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/cef8b2fa_cab1f483 PS1, Line 157: sizeof(te->name))) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/e99d5aa3_a5b6393d PS1, Line 158: write_mem_chip_information(te); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/06d548dc_ad42bc30 PS1, Line 158: write_mem_chip_information(te); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/8d2802fb_b37053d9 PS1, Line 213: qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a6cf87a6_4a2883c2 PS1, Line 213: qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/a9df5d6d_fdc57b7d PS1, Line 214: _mem_chip_info, REGION_SIZE(mem_chip_info), 0); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133031): https://review.coreboot.org/c/coreboot/+/59195/comment/de7585f6_6aa97b48 PS1, Line 214: _mem_chip_info, REGION_SIZE(mem_chip_info), 0); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:47:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: WIP libpayload: Parse DDR Information through coreboot tables WIP
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: WIP libpayload: Parse DDR Information through coreboot tables WIP ...................................................................... Patch Set 1: (4 comments) File payloads/libpayload/libc/coreboot.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/1c757a9e_4f7d0845 PS1, Line 357: cb_parse_mem_chip_info(ptr, info); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/07e6b2c9_f32cc133 PS1, Line 357: cb_parse_mem_chip_info(ptr, info); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/1ea7b3c3_fdf41090 PS1, Line 358: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/97a45a43_2f4885d0 PS1, Line 358: break; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:42:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Ravi kumar, Shelley Chen, Sudheer Amrabadi, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57025 ) Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes ...................................................................... Patch Set 30: (2 comments) File src/soc/qualcomm/common/qclib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133026): https://review.coreboot.org/c/coreboot/+/57025/comment/63b2579f_d851d493 PS30, Line 294: mainboard_blob_fix(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133026): https://review.coreboot.org/c/coreboot/+/57025/comment/9c9a3dbe_3bb0e86f PS30, Line 294: mainboard_blob_fix(); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/57025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c43d120ebb49800c82aec263ff8c215b60c5201 Gerrit-Change-Number: 57025 Gerrit-PatchSet: 30 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:41:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Pack out-of-bounds check into a function and move
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58764 ) Change subject: amdfwtool: Pack out-of-bounds check into a function and move ...................................................................... amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c 1 file changed, 15 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 049755b..b10315e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -354,6 +354,16 @@ #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) +void assert_fw_entry(uint32_t count, uint32_t max, context *ctx) +{ + if (count >= max) { + fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " + "(%d)\n", count, max); + free(ctx->rom); + exit(1); + } +} + static void *new_psp_dir(context *ctx, int multi) { void *ptr; @@ -653,6 +663,8 @@ if (!(fw_table[i].level & level)) continue; + assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); + if (fw_table[i].type == AMD_TOKEN_UNLOCK) { if (!fw_table[i].other) continue; @@ -719,6 +731,7 @@ } if (pspdir2) { + assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); pspdir->entries[count].type = AMD_FW_L2_PTR; pspdir->entries[count].subprog = 0; pspdir->entries[count].rsvd = 0; @@ -730,12 +743,6 @@ count++; } - if (count > MAX_PSP_ENTRIES) { - fprintf(stderr, "Error: PSP entries exceed max allowed items\n"); - free(ctx->rom); - exit(1); - } - fill_dir_header(pspdir, count, cookie, ctx); } @@ -888,6 +895,7 @@ if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM && (!fw_table[i].dest || !fw_table[i].size)) continue; + assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); biosdir->entries[count].type = fw_table[i].type; biosdir->entries[count].region_type = fw_table[i].region_type; @@ -977,6 +985,7 @@ } if (biosdir2) { + assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx); biosdir->entries[count].type = AMD_BIOS_L2_PTR; biosdir->entries[count].region_type = 0; biosdir->entries[count].size = @@ -994,13 +1003,6 @@ count++; } - if (count > MAX_BIOS_ENTRIES) { - fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " - "(%d)\n", count, MAX_BIOS_ENTRIES); - free(ctx->rom); - exit(1); - } - fill_dir_header(biosdir, count, cookie, ctx); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Gerrit-Change-Number: 58764 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sudheer Amrabadi, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK ...................................................................... Patch Set 92: (2 comments) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133024): https://review.coreboot.org/c/coreboot/+/50586/comment/f7bd7e71_750a8c66 PS92, Line 533: while (1) suspect code indent for conditional statements (24, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133024): https://review.coreboot.org/c/coreboot/+/50586/comment/d14d4926_f2843ace PS92, Line 554: while (1) suspect code indent for conditional statements (24, 24) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 92 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <quic_c_sbhanu(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:39:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... Patch Set 6: (1 comment) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133020): https://review.coreboot.org/c/coreboot/+/58545/comment/19a2d911_954531de PS6, Line 27: if (soc_modem_carve_out(&start, &end)) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:35:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: fix apusys coding defects
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59038 ) Change subject: soc/mediatek/mt8195: fix apusys coding defects ...................................................................... soc/mediatek/mt8195: fix apusys coding defects Use size_t for count variables. Reduce debug log level and fix typo. Fix commit: https://review.coreboot.org/c/coreboot/+/58794 BUG=b:203145462 BRANCH=cherry TEST=boot cherry correctly Signed-off-by: Flora Fu <flora.fu(a)mediatek.com> Change-Id: Ic03f71b7a9038edb5877ebd9b6aed5e9bd63c918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59038 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/apusys.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved flora.fu(a)mediatek.com: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8195/apusys.c b/src/soc/mediatek/mt8195/apusys.c index bc3c4ab..fc95cab 100644 --- a/src/soc/mediatek/mt8195/apusys.c +++ b/src/soc/mediatek/mt8195/apusys.c @@ -10,10 +10,10 @@ static void dump_apusys_reg(void) { - int i; + size_t i; for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) { - printk(BIOS_INFO, "APU_MBOX %p = %#x\n", + printk(BIOS_DEBUG, "APU_MBOX %p = %#x\n", (void *)&mt8195_apu_mbox[i]->mbox_func_cfg, read32(&mt8195_apu_mbox[i]->mbox_func_cfg)); } @@ -21,9 +21,9 @@ void apusys_init(void) { - int i; + size_t i; - /* Setup MBOX MPU for non secure access */ + /* Set up MBOX MPU for non secure access */ for (i = 0; i < ARRAY_SIZE(mt8195_apu_mbox); i++) SET32_BITFIELDS(&mt8195_apu_mbox[i]->mbox_func_cfg, NO_MPU, 1, LOCK, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/59038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic03f71b7a9038edb5877ebd9b6aed5e9bd63c918 Gerrit-Change-Number: 59038 Gerrit-PatchSet: 3 Gerrit-Owner: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: flora.fu(a)mediatek.com <flora.fu(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update typeC EC mux port
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59012 ) Change subject: mb/google/brya/var/felwinter: Update typeC EC mux port ...................................................................... mb/google/brya/var/felwinter: Update typeC EC mux port We need to put USB setting in mux order. BUG=b:204230406 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 9bd7ab5..2c4f6f7 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -133,15 +133,15 @@ chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn - register "usb2_port_number" = "2" - register "usb3_port_number" = "2" - device generic 1 alias conn1 on end - end - chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "3" register "usb3_port_number" = "3" device generic 2 alias conn2 on end end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "2" + register "usb3_port_number" = "2" + device generic 1 alias conn1 on end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Gerrit-Change-Number: 59012 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/gimble: Update audio setting for SmartAMP
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59046 ) Change subject: mb/google/brya/variants/gimble: Update audio setting for SmartAMP ...................................................................... mb/google/brya/variants/gimble: Update audio setting for SmartAMP Divide dsm_param_file_name into dsm_param_R and dsm_param_L BUG=b:205684021 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/gimble/overridetree.cb 2 files changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Mark Hsieh: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index ed9d82c..8d58fa5 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -27,6 +27,7 @@ bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_DSM_CALIB if CHROMEOS + select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS select DRIVERS_I2C_MAX98390 config BOARD_GOOGLE_REDRIX diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 8448594..c015009 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -135,7 +135,7 @@ register "name" = ""MXW0"" register "r0_calib_key" = ""dsm_calib_r0_0"" register "temperature_calib_key" = ""dsm_calib_temp_0"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_R"" register "vmon_slot_no" = "0" register "imon_slot_no" = "1" device i2c 0x38 on @@ -147,7 +147,7 @@ register "name" = ""MXW1"" register "r0_calib_key" = ""dsm_calib_r0_1"" register "temperature_calib_key" = ""dsm_calib_temp_1"" - register "dsm_param_file_name" = ""dsm_param"" + register "dsm_param_file_name" = ""dsm_param_L"" register "vmon_slot_no" = "1" register "imon_slot_no" = "0" device i2c 0x3c on -- To view, visit https://review.coreboot.org/c/coreboot/+/59046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Gerrit-Change-Number: 59046 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2021