coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58734 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles ...................................................................... mb/google/dedede/var/galtic: update Wifi SAR for convertibles Add wifi sar for galtic/galtic360/galith360 Using convertible mode of SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) BUG=b:203741126 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/galtic/variant.c 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marco Chen: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c index 72d91ee..558cba6 100644 --- a/src/mainboard/google/dedede/variants/galtic/variant.c +++ b/src/mainboard/google/dedede/variants/galtic/variant.c @@ -1,9 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <ec/google/chromeec/ec.h> #include <fw_config.h> #include <sar.h> +enum { + GALTIC_SKU_START = 0x120000, + GALTIC_SKU_END = 0x12ffff, + GALITH_SKU_START = 0x130000, + GALITH_SKU_END = 0x13ffff, + GALLOP_SKU_START = 0x150000, + GALLOP_SKU_END = 0x15ffff, + GALTIC360_SKU_START = 0x260000, + GALTIC360_SKU_END = 0x26ffff, + GALITH360_SKU_START = 0x270000, + GALITH360_SKU_END = 0x27ffff, +}; const char *get_wifi_sar_cbfs_filename(void) { - return "wifi_sar-galtic.hex"; + uint32_t sku_id = google_chromeec_get_board_sku(); + + if (sku_id >= GALTIC_SKU_START && sku_id <= GALTIC_SKU_END) + return "wifi_sar-galtic.hex"; + if (sku_id >= GALTIC360_SKU_START && sku_id <= GALTIC360_SKU_END) + return "wifi_sar-galtic360.hex"; + if (sku_id >= GALITH360_SKU_START && sku_id <= GALITH360_SKU_END) + return "wifi_sar-galith360.hex"; + + return WIFI_SAR_CBFS_DEFAULT_FILENAME; } -- To view, visit https://review.coreboot.org/c/coreboot/+/58734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Gerrit-Change-Number: 58734 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp: Fix size_t type mismatch in print statement
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Christian Walter, Arthur Heymans, Patrick Rudolph, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59054 ) Change subject: soc/intel/xeon_sp: Fix size_t type mismatch in print statement ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5 Gerrit-Change-Number: 59054 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:31:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google,intel: Add ChromeOS GPIOs to onboard.h
by Angel Pons (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59000 ) Change subject: mb/google,intel: Add ChromeOS GPIOs to onboard.h ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/mainboard/google/stout/chromeos.c: https://review.coreboot.org/c/coreboot/+/59000/comment/fd7990e0_0219f89b PS4, Line 79: CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), > Split to CB:59192 Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/59000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Gerrit-Change-Number: 59000 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:31:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add config option for S3 ACPI
by Sean Rhodes (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Crawford, Tim Wawrzynczak, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59024 ) Change subject: soc/intel/tigerlake: Add config option for S3 ACPI ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/tigerlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/59024/comment/c72831f2_61b4d895 PS16, Line 280: If ((TUID == 0) || (TUID == 1)) { : Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) : } Else { : Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) : > nit: Use tabs for indentation Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Gerrit-Change-Number: 59024 Gerrit-PatchSet: 17 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:31:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: comment

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Change in coreboot[master]: google/stout: Removed duplicate recovery mode switch entry
by Angel Pons (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59192 ) Change subject: google/stout: Removed duplicate recovery mode switch entry ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59192/comment/2aae2320_de74d3ab PS1, Line 7: Removed nit: present tense: `Remove` -- To view, visit https://review.coreboot.org/c/coreboot/+/59192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Gerrit-Change-Number: 59192 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:31:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Spell Intel Cooper Lake-SP with a space
by Felix Held (Code Review) 11 Nov '21

11 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59036 ) Change subject: Spell Intel Cooper Lake-SP with a space ...................................................................... Spell Intel Cooper Lake-SP with a space Use the official spelling. [1] [1]: https://ark.intel.com/content/www/us/en/ark/products/codename/189143/produc… Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59036 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/releases/coreboot-4.14-relnotes.md M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/chip.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index 40589a1..4f2b00e 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -142,7 +142,7 @@ coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory. This release has support for SkyLake-SP (SKX-SP) which is the 2nd -generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation +generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation or the latest generation [2] on market. With this release, the codebase for multiple generations of Xeon-SP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index d912f17..0f025ac 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -20,7 +20,7 @@ select PLATFORM_USES_FSP2_2 select CACHE_MRC_SETTINGS help - Intel Cooperlake-SP support + Intel Cooper Lake-SP support if XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 19bf2af..a4da344 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -186,7 +186,7 @@ } struct chip_operations soc_intel_xeon_sp_cpx_ops = { - CHIP_NAME("Intel Cooperlake-SP") + CHIP_NAME("Intel Cooper Lake-SP") .enable_dev = chip_enable_dev, .init = chip_init, .final = chip_final, -- To view, visit https://review.coreboot.org/c/coreboot/+/59036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dbd332600caa7c04fc4f6bac53880e832e97bda Gerrit-Change-Number: 59036 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58343 to look at the new patch set (#30). Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... ec/starlabs: Add standardised ITE EC support Add EC support that supports different Q Events and EC memory. Created from the ITE IT5570E and IT8987E datasheets, all using data port 0x4e. Tested with Ubuntu 20.04.3 and Windows 10 on: * StarBook Mk V (TGL + IT5570E): * ITE Firmware 1.00 * Merlin Firmware 1.00 * LabTop Mk IV (CML + IT8987E): * ITE Firmware 1.04 * LabTop Mk III (KBL + IT8987E): * ITE Firmware 3.12 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 --- A src/ec/starlabs/merlin/Kconfig A src/ec/starlabs/merlin/Makefile.inc A src/ec/starlabs/merlin/acpi/ac.asl A src/ec/starlabs/merlin/acpi/battery.asl A src/ec/starlabs/merlin/acpi/cmos.asl A src/ec/starlabs/merlin/acpi/ec.asl A src/ec/starlabs/merlin/acpi/hid.asl A src/ec/starlabs/merlin/acpi/keyboard.asl A src/ec/starlabs/merlin/acpi/lid.asl A src/ec/starlabs/merlin/acpi/suspend.asl A src/ec/starlabs/merlin/acpi/typec.asl A src/ec/starlabs/merlin/acpi/ubtc.asl A src/ec/starlabs/merlin/ec.c A src/ec/starlabs/merlin/ec.h A src/ec/starlabs/merlin/variants/apl/ecdefs.h A src/ec/starlabs/merlin/variants/apl/emem.asl A src/ec/starlabs/merlin/variants/apl/events.asl A src/ec/starlabs/merlin/variants/cml/ecdefs.h A src/ec/starlabs/merlin/variants/cml/emem.asl A src/ec/starlabs/merlin/variants/cml/events.asl A src/ec/starlabs/merlin/variants/glk/ecdefs.h A src/ec/starlabs/merlin/variants/glk/emem.asl A src/ec/starlabs/merlin/variants/glk/events.asl A src/ec/starlabs/merlin/variants/kbl/ecdefs.h A src/ec/starlabs/merlin/variants/kbl/emem.asl A src/ec/starlabs/merlin/variants/kbl/events.asl A src/ec/starlabs/merlin/variants/merlin/ecdefs.h A src/ec/starlabs/merlin/variants/merlin/emem.asl A src/ec/starlabs/merlin/variants/merlin/events.asl A src/ec/starlabs/merlin/variants/tgl/ecdefs.h A src/ec/starlabs/merlin/variants/tgl/emem.asl A src/ec/starlabs/merlin/variants/tgl/events.asl 32 files changed, 3,684 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58343/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 30 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add config option for S3 ACPI
by Tim Crawford (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Sean Rhodes, Tim Wawrzynczak, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59024 ) Change subject: soc/intel/tigerlake: Add config option for S3 ACPI ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/tigerlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/59024/comment/7df97941_4c3cce3c PS16, Line 280: If ((TUID == 0) || (TUID == 1)) { : Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) : } Else { : Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) : nit: Use tabs for indentation -- To view, visit https://review.coreboot.org/c/coreboot/+/59024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4 Gerrit-Change-Number: 59024 Gerrit-PatchSet: 16 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:25:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by Kyösti Mälkki (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Tim Wawrzynczak. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58896 ) Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... Patch Set 5: (2 comments) Patchset: PS2: > I'll look into it, but would probably need a new Kconfig. My plan about these "mode switches" and their weak alternatives: Advice to build the files with switch implementations (mb or variant bootmode.c) with all-y. We can make the builds fail for cases where these functions are called too early. Like attempting to read lid in bootblock where EC comms might not be possible. Put some if (ENV_ROMSTAGE_OR_BEFORE) call unresolved symbol? We could also declare the default switch states as weak functions in one common file. Part of the weak implementation is to keep track that we hit the weak function and to have a one/two line entry in console logs telling that the requested switch has not been implemented (yet). File src/mainboard/google/butterfly/chromeos.c: https://review.coreboot.org/c/coreboot/+/58896/comment/62904e06_6b06e5ce PS5, Line 14: void fill_lb_gpios(struct lb_gpios *gpios) I do not see a "EC in RW" entry here. -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:14:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by build bot (Jenkins) (Code Review) 11 Nov '21

11 Nov '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: Add CPUCP firmware support ...................................................................... Patch Set 88: (2 comments) File src/soc/qualcomm/sc7280/include/soc/cpucp.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133010): https://review.coreboot.org/c/coreboot/+/49768/comment/3d486e77_62fb8fa2 PS88, Line 6: #define EPSSTOP_EPSS_TOP (void *)0x18598000 Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133010): https://review.coreboot.org/c/coreboot/+/49768/comment/b76440fb_82e28aad PS88, Line 7: #define EPSSFAST_BASE_ADDR (void *)0x18580000 Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 88 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Thu, 11 Nov 2021 14:06:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021