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Hello build bot (Jenkins), Martin Roth, Marshall Dawson, Richard Spiegel, Zheng Bao, Matt Papageorge, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Call the set_efs_table for Stoneyridge
......................................................................
amdfwtool: Call the set_efs_table for Stoneyridge
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.
But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.
Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/mainboard/amd/gardenia/Kconfig
M src/mainboard/amd/padmelon/Kconfig
M src/mainboard/google/kahlee/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
M util/amdfwtool/amdfwtool.c
5 files changed, 34 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/58871/8
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 38:
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133544):
https://review.coreboot.org/c/coreboot/+/57131/comment/8fd79b88_002024c8
PS38, Line 1888: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER);
line over 96 characters
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Change subject: amdfwtool: copy
......................................................................
Abandoned
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Change subject: [WIP]soc/amd/mendocino: Add mendocino and mainboard
......................................................................
Abandoned
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Change subject: amdfwtool: Medocino
......................................................................
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Change subject: amdfwtool: Upgrade "relative address" to four address modes
......................................................................
Patch Set 5:
(6 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133540):
https://review.coreboot.org/c/coreboot/+/59308/comment/83117886_cd4f75dc
PS5, Line 355: ((mode) == 2 ? (offset) - ctx.current_table : (offset)) ))
space prohibited before that close parenthesis ')'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133540):
https://review.coreboot.org/c/coreboot/+/59308/comment/3f32e04d_721b4235
PS5, Line 357: #define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == 0 ? (run) - RUN_BASE(ctx) : (run)) /* TODO: */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133540):
https://review.coreboot.org/c/coreboot/+/59308/comment/df083602_7ba18760
PS5, Line 478: bdir->header.additional_info_fields.dir_size = table_size / 0x1000;;
Statements terminations use 1 semicolon
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133540):
https://review.coreboot.org/c/coreboot/+/59308/comment/3c19e76c_bf043444
PS5, Line 955: biosdir->entries[count].address_mode = SET_ADDR_MODE(1, biosdir);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133540):
https://review.coreboot.org/c/coreboot/+/59308/comment/934d24a7_c24174e4
PS5, Line 961: biosdir->entries[count].address_mode = SET_ADDR_MODE(1, biosdir);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133540):
https://review.coreboot.org/c/coreboot/+/59308/comment/e4d77c7e_3c439d62
PS5, Line 974: biosdir->entries[count].address_mode = SET_ADDR_MODE(1, biosdir);
line over 96 characters
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Change subject: [WIP]soc/amd/mendocino: Add mendocino and mainboard
......................................................................
Patch Set 1:
(12 comments)
File src/soc/amd/mendocino/fsp_m_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/369a454c_40f0f634
PS1, Line 109: for (i = 0; i < num; i++) {
braces {} are not necessary for single statement blocks
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/5dfc0fcf_4371d80c
PS1, Line 122: for (i = 0; i < num; i++) {
braces {} are not necessary for single statement blocks
File src/soc/amd/mendocino/psp_verstage/svc.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/0d6f1670_388d4d56
PS1, Line 6: #define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/3c0931ec_e0a71b3d
PS1, Line 19: #define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/d85160ca_6c958a96
PS1, Line 30: #define SVC_CALL2(SVC_ID, R0, R1, Ret) \
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/855e514f_828afa32
PS1, Line 40: #define SVC_CALL1(SVC_ID, R0, Ret) \
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/f37c190a_737282b5
PS1, Line 49: #define SVC_CALL0(SVC_ID, Ret) \
Macros with complex values should be enclosed in parentheses
File src/soc/amd/mendocino/root_complex.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/b09fd3f8_c2f7197a
PS1, Line 72: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/060ed702_92590bb8
PS1, Line 75: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/85b1c271_13b0e7fd
PS1, Line 80: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/7120ea71_e84a6998
PS1, Line 82: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133538):
https://review.coreboot.org/c/coreboot/+/59370/comment/f4faf3a1_347f837d
PS1, Line 85: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE
line over 96 characters
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Change subject: amdfwtool: Medocino
......................................................................
Patch Set 1:
(1 comment)
File util/amdfwtool/amdfwtool.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133537):
https://review.coreboot.org/c/coreboot/+/59369/comment/96decf57_8e895e5d
PS1, Line 58: AMD_FW_DMCUB =0x71,
spaces required around that '=' (ctx:WxV)
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Hello Jason Glenesk, Raul Rangel, Martin Roth, Patrick Georgi, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59370
to look at the new patch set (#2).
Change subject: [WIP]soc/amd/mendocino: Add mendocino and mainboard
......................................................................
[WIP]soc/amd/mendocino: Add mendocino and mainboard
Sample for amdfwtool.
Change-Id: Ie94272a220b187758865585a785ab8082821eaa8
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M Makefile.inc
A src/mainboard/amd/chausie/Kconfig
A src/mainboard/amd/chausie/Kconfig.name
A src/mainboard/amd/chausie/Makefile.inc
A src/mainboard/amd/chausie/board.fmd
A src/mainboard/amd/chausie/board_info.txt
A src/mainboard/amd/chausie/bootblock.c
A src/mainboard/amd/chausie/chromeos.c
A src/mainboard/amd/chausie/chromeos.fmd
A src/mainboard/amd/chausie/devicetree.cb
A src/mainboard/amd/chausie/dsdt.asl
A src/mainboard/amd/chausie/early_gpio.c
A src/mainboard/amd/chausie/gpio.h
A src/mainboard/amd/chausie/mainboard.c
A src/mainboard/amd/chausie/port_descriptors.c
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
A src/soc/amd/mendocino/Kconfig
A src/soc/amd/mendocino/Makefile.inc
A src/soc/amd/mendocino/acpi.c
A src/soc/amd/mendocino/acpi/globalnvs.asl
A src/soc/amd/mendocino/acpi/mmio.asl
A src/soc/amd/mendocino/acpi/pci0.asl
A src/soc/amd/mendocino/acpi/pci_int_defs.asl
A src/soc/amd/mendocino/acpi/soc.asl
A src/soc/amd/mendocino/agesa_acpi.c
A src/soc/amd/mendocino/aoac.c
A src/soc/amd/mendocino/bootblock.c
A src/soc/amd/mendocino/chip.c
A src/soc/amd/mendocino/chip.h
A src/soc/amd/mendocino/chipset.cb
A src/soc/amd/mendocino/config.c
A src/soc/amd/mendocino/cppc.c
A src/soc/amd/mendocino/cpu.c
A src/soc/amd/mendocino/data_fabric.c
A src/soc/amd/mendocino/early_fch.c
A src/soc/amd/mendocino/fch.c
A src/soc/amd/mendocino/fsp_m_params.c
A src/soc/amd/mendocino/fsp_s_params.c
A src/soc/amd/mendocino/fw.cfg
A src/soc/amd/mendocino/gpio.c
A src/soc/amd/mendocino/graphics.c
A src/soc/amd/mendocino/i2c.c
A src/soc/amd/mendocino/include/soc/acpi.h
A src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h
A src/soc/amd/mendocino/include/soc/aoac_defs.h
A src/soc/amd/mendocino/include/soc/cppc.h
A src/soc/amd/mendocino/include/soc/cpu.h
A src/soc/amd/mendocino/include/soc/data_fabric.h
A src/soc/amd/mendocino/include/soc/gpio.h
A src/soc/amd/mendocino/include/soc/i2c.h
A src/soc/amd/mendocino/include/soc/iomap.h
A src/soc/amd/mendocino/include/soc/lpc.h
A src/soc/amd/mendocino/include/soc/msr.h
A src/soc/amd/mendocino/include/soc/nvs.h
A src/soc/amd/mendocino/include/soc/pci_devs.h
A src/soc/amd/mendocino/include/soc/platform_descriptors.h
A src/soc/amd/mendocino/include/soc/psp_transfer.h
A src/soc/amd/mendocino/include/soc/psp_verstage_addr.h
A src/soc/amd/mendocino/include/soc/smi.h
A src/soc/amd/mendocino/include/soc/smu.h
A src/soc/amd/mendocino/include/soc/southbridge.h
A src/soc/amd/mendocino/include/soc/uart.h
A src/soc/amd/mendocino/mca.c
A src/soc/amd/mendocino/psp_verstage/Makefile.inc
A src/soc/amd/mendocino/psp_verstage/chipset.c
A src/soc/amd/mendocino/psp_verstage/svc.c
A src/soc/amd/mendocino/psp_verstage/svc.h
A src/soc/amd/mendocino/reset.c
A src/soc/amd/mendocino/romstage.c
A src/soc/amd/mendocino/root_complex.c
A src/soc/amd/mendocino/smihandler.c
A src/soc/amd/mendocino/smu.c
A src/soc/amd/mendocino/uart.c
A src/soc/amd/mendocino/xhci.c
A src/vendorcode/amd/fsp/mendocino/FspGuids.h
A src/vendorcode/amd/fsp/mendocino/FspUpd.h
A src/vendorcode/amd/fsp/mendocino/FspUsb.h
A src/vendorcode/amd/fsp/mendocino/FspmUpd.h
A src/vendorcode/amd/fsp/mendocino/FspsUpd.h
A src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S
A src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_header.inc
A src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S
A src/vendorcode/amd/fsp/mendocino/dmi_info.h
A src/vendorcode/amd/fsp/mendocino/fsp_h_c99.h
A src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_errorcodes_public.h
A src/vendorcode/amd/fsp/mendocino/include/bl_uapp/bl_syscall_public.h
A src/vendorcode/amd/fsp/mendocino/platform_descriptors.h
M util/cbfstool/cbfs_image.c
88 files changed, 7,123 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/59370/2
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Gerrit-Change-Id: Ie94272a220b187758865585a785ab8082821eaa8
Gerrit-Change-Number: 59370
Gerrit-PatchSet: 2
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Zheng Bao
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Gerrit-MessageType: newpatchset
Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57133
to look at the new patch set (#39).
Change subject: [DEMO]soc/amd/picasso: Add command parameters for recovery
......................................................................
[DEMO]soc/amd/picasso: Add command parameters for recovery
Change-Id: Icb49d0c09f42c7e5df714864fc42418ca84f8120
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/picasso/Makefile.inc
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57133/39
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icb49d0c09f42c7e5df714864fc42418ca84f8120
Gerrit-Change-Number: 57133
Gerrit-PatchSet: 39
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-MessageType: newpatchset