coreboot-gerrit November 2021

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Change in coreboot[master]: ec/starlabs: Add USB Type-C Mailbox interface
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59388 ) Change subject: ec/starlabs: Add USB Type-C Mailbox interface ...................................................................... Abandoned Added in other commit -- To view, visit https://review.coreboot.org/c/coreboot/+/59388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c9a0afec4ad3ad54a0a67d7ab68b7cabca2db6 Gerrit-Change-Number: 59388 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Sean Rhodes, Paul Menzel, Angel Pons, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58343 to look at the new patch set (#45). Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... ec/starlabs: Add standardised ITE EC support Add EC support that supports different Q Events and EC memory. Created from the ITE IT5570E and IT8987E datasheets, all using data port 0x4e. Tested with Ubuntu 20.04.3 and Windows 10 on: * StarBook Mk V (TGL + IT5570E): * ITE Firmware 1.00 * Merlin Firmware 1.00 * LabTop Mk IV (CML + IT8987E): * ITE Firmware 1.04 * LabTop Mk III (KBL + IT8987E): * ITE Firmware 3.12 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 --- A src/ec/starlabs/merlin/Kconfig A src/ec/starlabs/merlin/Makefile.inc A src/ec/starlabs/merlin/acpi/ac.asl A src/ec/starlabs/merlin/acpi/battery.asl A src/ec/starlabs/merlin/acpi/cmos.asl A src/ec/starlabs/merlin/acpi/ec.asl A src/ec/starlabs/merlin/acpi/hid.asl A src/ec/starlabs/merlin/acpi/keyboard.asl A src/ec/starlabs/merlin/acpi/lid.asl A src/ec/starlabs/merlin/acpi/suspend.asl A src/ec/starlabs/merlin/acpi/typec.asl A src/ec/starlabs/merlin/acpi/ubtc.asl A src/ec/starlabs/merlin/ec.c A src/ec/starlabs/merlin/ec.h A src/ec/starlabs/merlin/variants/apl/ecdefs.h A src/ec/starlabs/merlin/variants/apl/emem.asl A src/ec/starlabs/merlin/variants/apl/events.asl A src/ec/starlabs/merlin/variants/cml/ecdefs.h A src/ec/starlabs/merlin/variants/cml/emem.asl A src/ec/starlabs/merlin/variants/cml/events.asl A src/ec/starlabs/merlin/variants/glk/ecdefs.h A src/ec/starlabs/merlin/variants/glk/emem.asl A src/ec/starlabs/merlin/variants/glk/events.asl A src/ec/starlabs/merlin/variants/kbl/ecdefs.h A src/ec/starlabs/merlin/variants/kbl/emem.asl A src/ec/starlabs/merlin/variants/kbl/events.asl A src/ec/starlabs/merlin/variants/merlin/ecdefs.h A src/ec/starlabs/merlin/variants/merlin/emem.asl A src/ec/starlabs/merlin/variants/merlin/events.asl A src/ec/starlabs/merlin/variants/tgl/ecdefs.h A src/ec/starlabs/merlin/variants/tgl/emem.asl A src/ec/starlabs/merlin/variants/tgl/events.asl 32 files changed, 3,667 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58343/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 45 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Compile IA common thermal block in romstage
by EricR Lai (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59391 ) Change subject: soc/intel/../thermal: Compile IA common thermal block in romstage ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Will check and feedback here. LGTM, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/59391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8 Gerrit-Change-Number: 59391 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 11:00:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/../thermal: Drop unused `dev` variable in pch_get_ltt_value()
by EricR Lai (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59390 ) Change subject: soc/intel/../thermal: Drop unused `dev` variable in pch_get_ltt_value() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Gerrit-Change-Number: 59390 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 10:59:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Andy Pont (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Sean Rhodes, Paul Menzel, Angel Pons, Felix Held. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 44: (2 comments) File src/ec/starlabs/merlin/ec.c: https://review.coreboot.org/c/coreboot/+/58343/comment/b2b36b61_ce432f30 PS44, Line 14: u16 it_get_version(void) This file seems to have developed a mismatched use of type definitions i.e we have u16 and uint8_t. Need to stick with one or the other! https://review.coreboot.org/c/coreboot/+/58343/comment/651692ad_2c123fe4 PS44, Line 47: static u16 ite_get_chip_id(unsigned int port) : { : return (pnp_read_index(port, ITE_CHIPID1) << 8) | : pnp_read_index(port, ITE_CHIPID2); : } : This probably needs moving up to the top next to the it_get_version() function. -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 44 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 17 Nov 2021 10:57:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 44: (19 comments) File src/ec/starlabs/merlin/Makefile.inc: https://review.coreboot.org/c/coreboot/+/58343/comment/0a4b68d6_729a346e PS42, Line 7: $(CONFIG_EC_VARIANT_DIR) > I'm pretty sure you need to use `strip_quotes` here, in CB:29447 I ran into the same issue: […] Done https://review.coreboot.org/c/coreboot/+/58343/comment/4f81e55e_fcd2b253 PS42, Line 9: ifeq ($(CONFIG_EC_STARLABS_ITE),y) > This should also guard the lines above, this file is unconditionally included. Done https://review.coreboot.org/c/coreboot/+/58343/comment/e5552865_156aa5fb PS42, Line 11: smm-$(CONFIG_DEBUG_SMI) += ec.c > I'm pretty sure this isn't needed, and causes build errors when `DEBUG_SMI` is enabled. […] Done https://review.coreboot.org/c/coreboot/+/58343/comment/89065efc_e78968b8 PS42, Line 18: files_added:: warn_no_ite_fw : : PHONY+=warn_no_ite_fw : warn_no_ite_fw: : printf "\n\t** WARNING **\n" : printf "coreboot has been built without the ITE EC Firmware.\n" : printf "Do not flash this image. Your laptop's power button\n" : printf "may not respond when you press it.\n\n" > Shouldn't this be in the `else` branch of `ifeq ($(CONFIG_EC_STARLABS_IT_BIN),y)`? Currently, the wa […] That's what it was meant to do - only CML and TGL need the EC bin, and if they are built without it, the world will end. File src/ec/starlabs/merlin/ec.c: https://review.coreboot.org/c/coreboot/+/58343/comment/07256f39_66d8c597 PS42, Line 47: u8 chipid1 = pnp_read_index(dev->path.pnp.port, ITE_CHIPID1); : u8 chipid2 = pnp_read_index(dev->path.pnp.port, ITE_CHIPID2); > nit: `chipid1` and `chipid2` can be const. […] Done https://review.coreboot.org/c/coreboot/+/58343/comment/44a7e3ee_2a2a2b86 PS42, Line 50: printk(BIOS_ERR, "ITE: Device not found.\n"); > Idea: print the expected and actual IDs? […] Nice! https://review.coreboot.org/c/coreboot/+/58343/comment/0efa8893_2f092212 PS42, Line 54: printk(BIOS_DEBUG, "ITE: Initializing keyboard.\n"); > Strictly speaking, coreboot only does keyboard init if `DRIVERS_PS2_KEYBOARD` is set, which is only […] Done File src/ec/starlabs/merlin/variants/apl/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/96aac706_c3597fe4 PS42, Line 13: IT5570 > Looks like IT8987 Done File src/ec/starlabs/merlin/variants/apl/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/72668a37_4ff7bd9b PS42, Line 3: 0xFF > This makes the OperationRegion 0xff = 255 bytes long. […] Done File src/ec/starlabs/merlin/variants/cml/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/85bfd845_f062406c PS42, Line 10: IT5570 > Looks like IT8987 Done File src/ec/starlabs/merlin/variants/cml/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/b8fd8596_5613c796 PS42, Line 3: 0xFF > This makes the OperationRegion 0xff = 255 bytes long. […] Done File src/ec/starlabs/merlin/variants/glk/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/bc2d60ac_49a8c1e8 PS42, Line 13: IT5570 > Looks like IT8987 Done File src/ec/starlabs/merlin/variants/glk/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/56eab6f0_8046d0e0 PS42, Line 3: 0xFF > This makes the OperationRegion 0xff = 255 bytes long. […] Done File src/ec/starlabs/merlin/variants/kbl/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/2c82dd27_890c9ee0 PS42, Line 10: IT5570 > Looks like IT8987 Done File src/ec/starlabs/merlin/variants/kbl/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/bc7268ff_884eeb36 PS42, Line 3: 0xFF > This makes the OperationRegion 0xff = 255 bytes long. […] Done File src/ec/starlabs/merlin/variants/merlin/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/b462f4e3_5115951e PS42, Line 3: 0xFF > This makes the OperationRegion 0xff = 255 bytes long. […] Done https://review.coreboot.org/c/coreboot/+/58343/comment/6773b8f3_3e89e30e PS42, Line 160: H > nit: lowercase `h` Done File src/ec/starlabs/merlin/variants/tgl/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/e8b4961d_b9c98cdd PS42, Line 3: 0xFF > This makes the OperationRegion 0xff = 255 bytes long. […] Done https://review.coreboot.org/c/coreboot/+/58343/comment/8dbe210d_5108dc3b PS42, Line 167: H > nit: lowercase `h` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 44 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 17 Nov 2021 10:48:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58343 to look at the new patch set (#44). Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... ec/starlabs: Add standardised ITE EC support Add EC support that supports different Q Events and EC memory. Created from the ITE IT5570E and IT8987E datasheets, all using data port 0x4e. Tested with Ubuntu 20.04.3 and Windows 10 on: * StarBook Mk V (TGL + IT5570E): * ITE Firmware 1.00 * Merlin Firmware 1.00 * LabTop Mk IV (CML + IT8987E): * ITE Firmware 1.04 * LabTop Mk III (KBL + IT8987E): * ITE Firmware 3.12 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 --- A src/ec/starlabs/merlin/Kconfig A src/ec/starlabs/merlin/Makefile.inc A src/ec/starlabs/merlin/acpi/ac.asl A src/ec/starlabs/merlin/acpi/battery.asl A src/ec/starlabs/merlin/acpi/cmos.asl A src/ec/starlabs/merlin/acpi/ec.asl A src/ec/starlabs/merlin/acpi/hid.asl A src/ec/starlabs/merlin/acpi/keyboard.asl A src/ec/starlabs/merlin/acpi/lid.asl A src/ec/starlabs/merlin/acpi/suspend.asl A src/ec/starlabs/merlin/ec.c A src/ec/starlabs/merlin/ec.h A src/ec/starlabs/merlin/variants/apl/ecdefs.h A src/ec/starlabs/merlin/variants/apl/emem.asl A src/ec/starlabs/merlin/variants/apl/events.asl A src/ec/starlabs/merlin/variants/cml/ecdefs.h A src/ec/starlabs/merlin/variants/cml/emem.asl A src/ec/starlabs/merlin/variants/cml/events.asl A src/ec/starlabs/merlin/variants/glk/ecdefs.h A src/ec/starlabs/merlin/variants/glk/emem.asl A src/ec/starlabs/merlin/variants/glk/events.asl A src/ec/starlabs/merlin/variants/kbl/ecdefs.h A src/ec/starlabs/merlin/variants/kbl/emem.asl A src/ec/starlabs/merlin/variants/kbl/events.asl A src/ec/starlabs/merlin/variants/merlin/ecdefs.h A src/ec/starlabs/merlin/variants/merlin/emem.asl A src/ec/starlabs/merlin/variants/merlin/events.asl A src/ec/starlabs/merlin/variants/tgl/ecdefs.h A src/ec/starlabs/merlin/variants/tgl/emem.asl A src/ec/starlabs/merlin/variants/tgl/events.asl 30 files changed, 3,532 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58343/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 44 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/../thermal: Compile IA common thermal block in romstage
by Subrata Banik (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59391 ) Change subject: soc/intel/../thermal: Compile IA common thermal block in romstage ...................................................................... soc/intel/../thermal: Compile IA common thermal block in romstage This patch ensures IA common thermal block is now able to compile under romstage with necessary compilation issues fixed. BUG=b:193774296 Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/thermal/Makefile.inc M src/soc/intel/common/block/thermal/thermal.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/59391/1 diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc index 6f216b3..951065c 100644 --- a/src/soc/intel/common/block/thermal/Makefile.inc +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -1 +1,2 @@ +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index d6e401e..4a2d8d8 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -43,7 +43,7 @@ uint16_t reg16; uintptr_t thermalbar; uintptr_t thermalbar_pm; - struct device *dev; + const struct device *dev; struct resource *res; dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); -- To view, visit https://review.coreboot.org/c/coreboot/+/59391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8 Gerrit-Change-Number: 59391 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/../thermal: Drop unused `dev` variable in pch_get_ltt_value()
by Subrata Banik (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59390 ) Change subject: soc/intel/../thermal: Drop unused `dev` variable in pch_get_ltt_value() ...................................................................... soc/intel/../thermal: Drop unused `dev` variable in pch_get_ltt_value() `struct device *dev` as part of the pch_get_ltt_value() argument is being used hence, replaced with `void`. BUG=b:193774296 Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/59390/1 diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 11a6108..d6e401e 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -23,7 +23,7 @@ } /* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(struct device *dev) +static uint32_t pch_get_ltt_value(void) { uint8_t thermal_config; @@ -68,6 +68,6 @@ reg16 = read16((uint16_t *)thermalbar_pm); reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(dev); + reg16 |= pch_get_ltt_value(); write16((uint16_t *)thermalbar_pm, reg16); } -- To view, visit https://review.coreboot.org/c/coreboot/+/59390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116 Gerrit-Change-Number: 59390 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Hook up common code for thermal configuration
by Subrata Banik (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Felix Singer, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59271 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Hook up common code for thermal configuration ...................................................................... soc/intel/alderlake: Hook up common code for thermal configuration Thermal configuration registers are now located behind PMC PWRMBASE for Alder Lake Point PCH. Hence, ADL SoC to select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold is being set as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. BUG=b:193774296 TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/59271/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/59271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796 Gerrit-Change-Number: 59271 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2021