coreboot-gerrit November 2021

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Change in coreboot[master]: mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nippe...
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59051 ) Change subject: mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin ...................................................................... mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin For Guybrush Board Version 2, Nipperking Board Version 1, update SPKR GPIO to match H/W schematic: SPKR: GPIO31 For Nipperkin Board Version 2, update SPKR GPIO to match H/W schematic: SPKR: GPIO70 BUG=b:202992077 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051 Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 4 files changed, 13 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 82956dc..0720bc2 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -66,8 +66,8 @@ PAD_GPO(GPIO_29, LOW), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* EN_SPKR */ - PAD_GPO(GPIO_31, HIGH), + /* Unused */ + PAD_NC(GPIO_31), /* Unused */ PAD_NC(GPIO_32), /* GPIO_33 - GPIO_39: Not available */ @@ -83,8 +83,8 @@ PAD_GPO(GPIO_68, HIGH), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_69, HIGH), - /* Unused TP27 */ - PAD_NC(GPIO_70), + /* EN_SPKR */ + PAD_GPO(GPIO_70, HIGH), /* GPIO_71 - GPIO_73: Not available */ /* Unused TP49 */ PAD_NC(GPIO_74), diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 6309ec2..e90f4a3 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -9,8 +9,6 @@ /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { - /* Unused TP183 */ - PAD_NC(GPIO_31), /* EN_SPKR */ PAD_GPO(GPIO_69, HIGH), /* SD_AUX_RESET_L */ @@ -37,6 +35,10 @@ PAD_NC(GPIO_85), /* EN_PWR_FP */ PAD_GPO(GPIO_32, LOW), + /* EN_SPKR */ + PAD_GPO(GPIO_31, HIGH), + /* Unused TP27 */ + PAD_NC(GPIO_70), }; static const struct soc_amd_gpio override_early_gpio_table[] = { diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 2c502df..a2a0e93 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -22,6 +22,10 @@ PAD_NC(GPIO_85), /* EN_PWR_FP */ PAD_GPO(GPIO_32, LOW), + /* EN_SPKR */ + PAD_GPO(GPIO_31, HIGH), + /* Unused TP27 */ + PAD_NC(GPIO_70), }; /* This table is used by nipperkin variant with board version >= 2. */ diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 3599b28..2d3b162 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -166,7 +166,7 @@ chip drivers/generic/max98357a register "hid" = ""MX98360A"" - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_31)" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_70)" register "sdmode_delay" = "5" device generic 0.1 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/59051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e Gerrit-Change-Number: 59051 Gerrit-PatchSet: 7 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/psp_verstage: Split up verstage_soc_init
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59318 ) Change subject: soc/amd/psp_verstage: Split up verstage_soc_init ...................................................................... soc/amd/psp_verstage: Split up verstage_soc_init Make psp verstage initialization more granular be splitting verstage_soc_init into separate functions. Specifically, create soc init functions for espi, i2c spi, and aoac. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c 3 files changed, 36 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index f578bcb..fca4c9a 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -152,15 +152,29 @@ return map_fch_devices(); } -void verstage_soc_init(void) +void verstage_soc_espi_init(void) { - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) - espi_setup(); + if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) + return; + printk(BIOS_DEBUG, "Setting up espi\n"); + espi_setup(); +} - enable_aoac_devices(); +void verstage_soc_i2c_init(void) +{ printk(BIOS_DEBUG, "Setting up i2c\n"); i2c_soc_early_init(); - printk(BIOS_DEBUG, "i2c setup\n"); +} + +void verstage_soc_aoac_init(void) +{ + printk(BIOS_DEBUG, "Setting up aoac\n"); + enable_aoac_devices(); +} + +void verstage_soc_spi_init(void) +{ + printk(BIOS_DEBUG, "Setting up spi\n"); fch_spi_config_modes(); show_spi_speeds_and_modes(); } diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 976bc69..dbdf2f2 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -49,7 +49,10 @@ uint32_t unmap_fch_devices(void); uint32_t verstage_soc_early_init(void); void verstage_mainboard_espi_init(void); -void verstage_soc_init(void); +void verstage_soc_aoac_init(void); +void verstage_soc_espi_init(void); +void verstage_soc_i2c_init(void); +void verstage_soc_spi_init(void); uintptr_t *map_spi_rom(void); uint32_t get_max_workbuf_size(uint32_t *size); diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index f3b4256..8fc2732 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -243,7 +243,19 @@ svc_write_postcode(POSTCODE_LATE_INIT); fch_io_enable_legacy_io(); - verstage_soc_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_espi_init\n"); + verstage_soc_espi_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_aoac_init\n"); + verstage_soc_aoac_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_i2c_init\n"); + verstage_soc_i2c_init(); + + printk(BIOS_DEBUG, "calling verstage_soc_spi_init\n"); + verstage_soc_spi_init(); + verstage_mainboard_init(); post_code(POSTCODE_VERSTAGE_MAIN); -- To view, visit https://review.coreboot.org/c/coreboot/+/59318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60 Gerrit-Change-Number: 59318 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/octopus: Add missing VBTs for variants
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59327 ) Change subject: mb/google/octopus: Add missing VBTs for variants ...................................................................... mb/google/octopus: Add missing VBTs for variants Add VBTs for all octopus variants currently supported by ChromeOS recovery images. For variants which use multiple VBTs and select at runtime, ensure these are added directly to CBFS. Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name M src/mainboard/google/octopus/variants/bloog/Makefile.inc A src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt A src/mainboard/google/octopus/variants/bloog/data.vbt A src/mainboard/google/octopus/variants/bobba/data.vbt A src/mainboard/google/octopus/variants/casta/data.vbt A src/mainboard/google/octopus/variants/fleex/data.vbt M src/mainboard/google/octopus/variants/garg/Makefile.inc A src/mainboard/google/octopus/variants/garg/data.vbt A src/mainboard/google/octopus/variants/garg/garfour-data.vbt A src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt A src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt A src/mainboard/google/octopus/variants/lick/data.vbt M src/mainboard/google/octopus/variants/meep/Makefile.inc A src/mainboard/google/octopus/variants/meep/data.vbt A src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt A src/mainboard/google/octopus/variants/meep/vortininja-data.vbt A src/mainboard/google/octopus/variants/phaser/data.vbt A src/mainboard/google/octopus/variants/yorp/data.vbt 20 files changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index eb6cbc6..25d08eb8 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -18,7 +18,6 @@ select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_AMPTON select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_ESPI diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index 4fcc3e1..4168411 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -4,12 +4,14 @@ bool "-> Ampton (ASUS Chromebook Flip C214)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_RT5682 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_BLOOG bool "-> Bloog (HP Chromebook x360 12b, 14a, x360 14b)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS @@ -17,6 +19,7 @@ bool "-> Bobba (Acer Chromebook 311 / Spin 511)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS @@ -24,6 +27,7 @@ bool "-> Bluebird/Casta (Samsung Chromebook 4, 4+)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_DOOD @@ -36,6 +40,7 @@ bool "-> Fleex (Dell Chromebook 3100)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS @@ -49,6 +54,7 @@ bool "-> Garg" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS @@ -56,12 +62,14 @@ bool "-> Lick (Ideapad 3 Chromebook)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_MEEP bool "-> Meep (HP Chromebook x360 11 G2 EE)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS @@ -74,6 +82,7 @@ bool "-> Phaser (Lenovo 100e/300e/500e Chromebook 2nd Gen (Intel))" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS @@ -81,4 +90,5 @@ bool "-> Yorp" select BOARD_GOOGLE_BASEBOARD_OCTOPUS select BASEBOARD_OCTOPUS_LAPTOP + select INTEL_GMA_HAVE_VBT select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/bloog/Makefile.inc b/src/mainboard/google/octopus/variants/bloog/Makefile.inc index ba865e9..98c1e44 100644 --- a/src/mainboard/google/octopus/variants/bloog/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bloog/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += gpio.c ramstage-y += variant.c + +$(call add_vbt_to_cbfs, vbt_blooguard.bin, blooguard-data.vbt) diff --git a/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt b/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt new file mode 100644 index 0000000..1d93571 --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/bloog/data.vbt b/src/mainboard/google/octopus/variants/bloog/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/bloog/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/bobba/data.vbt b/src/mainboard/google/octopus/variants/bobba/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/bobba/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/casta/data.vbt b/src/mainboard/google/octopus/variants/casta/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/casta/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/fleex/data.vbt b/src/mainboard/google/octopus/variants/fleex/data.vbt new file mode 100644 index 0000000..2848abe --- /dev/null +++ b/src/mainboard/google/octopus/variants/fleex/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/garg/Makefile.inc b/src/mainboard/google/octopus/variants/garg/Makefile.inc index 7ee7e70..a443e8d 100644 --- a/src/mainboard/google/octopus/variants/garg/Makefile.inc +++ b/src/mainboard/google/octopus/variants/garg/Makefile.inc @@ -4,3 +4,7 @@ ramstage-y += variant.c smm-y += variant.c + +$(call add_vbt_to_cbfs, vbt_garg_hdmi.bin, garg-hdmi-data.vbt) +$(call add_vbt_to_cbfs, vbt_garfour.bin, garfour-data.vbt) +$(call add_vbt_to_cbfs, vbt_garfour_hdmi.bin, garfour-hdmi-data.vbt) diff --git a/src/mainboard/google/octopus/variants/garg/data.vbt b/src/mainboard/google/octopus/variants/garg/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/garg/garfour-data.vbt b/src/mainboard/google/octopus/variants/garg/garfour-data.vbt new file mode 100644 index 0000000..1d93571 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/garfour-data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt b/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt new file mode 100644 index 0000000..abf1d88 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt b/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt new file mode 100644 index 0000000..2073536 --- /dev/null +++ b/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/lick/data.vbt b/src/mainboard/google/octopus/variants/lick/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/lick/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/meep/Makefile.inc b/src/mainboard/google/octopus/variants/meep/Makefile.inc index ba865e9..7a6301c 100644 --- a/src/mainboard/google/octopus/variants/meep/Makefile.inc +++ b/src/mainboard/google/octopus/variants/meep/Makefile.inc @@ -2,3 +2,6 @@ ramstage-y += gpio.c ramstage-y += variant.c + +$(call add_vbt_to_cbfs, vbt_dorp_hdmi.bin, dorp-hdmi-data.vbt) +$(call add_vbt_to_cbfs, vbt_vortininja.bin, vortininja-data.vbt) diff --git a/src/mainboard/google/octopus/variants/meep/data.vbt b/src/mainboard/google/octopus/variants/meep/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt b/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt new file mode 100644 index 0000000..ac58bd4 --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt b/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt new file mode 100644 index 0000000..1d93571 --- /dev/null +++ b/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/phaser/data.vbt b/src/mainboard/google/octopus/variants/phaser/data.vbt new file mode 100644 index 0000000..fbcf46e --- /dev/null +++ b/src/mainboard/google/octopus/variants/phaser/data.vbt Binary files differ diff --git a/src/mainboard/google/octopus/variants/yorp/data.vbt b/src/mainboard/google/octopus/variants/yorp/data.vbt new file mode 100644 index 0000000..764ee94 --- /dev/null +++ b/src/mainboard/google/octopus/variants/yorp/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/59327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830 Gerrit-Change-Number: 59327 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/octopus: Alphabetize variants in Kconfig.name
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59326 ) Change subject: mb/google/octopus: Alphabetize variants in Kconfig.name ...................................................................... mb/google/octopus: Alphabetize variants in Kconfig.name Change-Id: I2e57c4f1baa8a42bde2642e7f76ddead7bfd6a58 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59326 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig.name 1 file changed, 41 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index f5cb536..4fcc3e1 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -1,31 +1,13 @@ comment "Octopus" -config BOARD_GOOGLE_OCTOPUS - bool "-> Octopus" - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select BASEBOARD_OCTOPUS_LAPTOP - -config BOARD_GOOGLE_YORP - bool "-> Yorp" - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select BASEBOARD_OCTOPUS_LAPTOP - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_PHASER - bool "-> Phaser (Lenovo 100e/300e/500e Chromebook 2nd Gen (Intel))" +config BOARD_GOOGLE_AMPTON + bool "-> Ampton (ASUS Chromebook Flip C214)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS -config BOARD_GOOGLE_LICK - bool "-> Lick (Ideapad 3 Chromebook)" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_FLEEX - bool "-> Fleex (Dell Chromebook 3100)" +config BOARD_GOOGLE_BLOOG + bool "-> Bloog (HP Chromebook x360 12b, 14a, x360 14b)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS @@ -38,32 +20,31 @@ select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS -config BOARD_GOOGLE_MEEP - bool "-> Meep (HP Chromebook x360 11 G2 EE)" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_DA7219 if INCLUDE_NHLT_BLOBS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - -config BOARD_GOOGLE_AMPTON - bool "-> Ampton (ASUS Chromebook Flip C214)" - select BASEBOARD_OCTOPUS_LAPTOP - select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select NHLT_RT5682 if INCLUDE_NHLT_BLOBS - config BOARD_GOOGLE_CASTA bool "-> Bluebird/Casta (Samsung Chromebook 4, 4+)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS -config BOARD_GOOGLE_BLOOG - bool "-> Bloog (HP Chromebook x360 12b, 14a, x360 14b)" +config BOARD_GOOGLE_DOOD + bool "-> Dood" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_FLEEX + bool "-> Fleex (Dell Chromebook 3100)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS +config BOARD_GOOGLE_FOOB + bool "-> Foob" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + config BOARD_GOOGLE_GARG bool "-> Garg" select BASEBOARD_OCTOPUS_LAPTOP @@ -71,14 +52,33 @@ select NHLT_DA7219 if INCLUDE_NHLT_BLOBS select NHLT_RT5682 if INCLUDE_NHLT_BLOBS -config BOARD_GOOGLE_DOOD - bool "-> Dood" +config BOARD_GOOGLE_LICK + bool "-> Lick (Ideapad 3 Chromebook)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS -config BOARD_GOOGLE_FOOB - bool "-> Foob" +config BOARD_GOOGLE_MEEP + bool "-> Meep (HP Chromebook x360 11 G2 EE)" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_OCTOPUS + bool "-> Octopus" + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select BASEBOARD_OCTOPUS_LAPTOP + +config BOARD_GOOGLE_PHASER + bool "-> Phaser (Lenovo 100e/300e/500e Chromebook 2nd Gen (Intel))" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + select NHLT_RT5682 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_YORP + bool "-> Yorp" + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select BASEBOARD_OCTOPUS_LAPTOP + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS -- To view, visit https://review.coreboot.org/c/coreboot/+/59326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e57c4f1baa8a42bde2642e7f76ddead7bfd6a58 Gerrit-Change-Number: 59326 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/slippy/peppy: use shared touchpad interrupts
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59330 ) Change subject: mb/google/slippy/peppy: use shared touchpad interrupts ...................................................................... mb/google/slippy/peppy: use shared touchpad interrupts Windows (10/11) freaks out and generates an interrupt storm if two ACPI devices are enabled and share an interrupt, even when only one device is actually present. To mitigate this, mark Peppy's interrupts as Shared rather than the default of Exclusive. Test: build/boot Windows 10 on Peppy, observe normal CPU usage in Task Manager for System Interrupts task when touchpad in use. Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index babf9a0..e793090 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -18,7 +18,7 @@ AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0" // ResourceSource ) - Interrupt (ResourceConsumer, Level, ActiveLow) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared) { BOARD_TRACKPAD_IRQ } @@ -60,7 +60,7 @@ AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0" // ResourceSource ) - Interrupt (ResourceConsumer, Edge, ActiveLow) + Interrupt (ResourceConsumer, Edge, ActiveLow, Shared) { BOARD_TRACKPAD_IRQ } -- To view, visit https://review.coreboot.org/c/coreboot/+/59330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a Gerrit-Change-Number: 59330 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59347 ) Change subject: mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI ...................................................................... mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI This board does not have a LPC or eSPI connection to the NC FPGA anymore and therefore IO port 0x80 is not useable for POST codes anymore. Enable the feature of sending the POST codes to the NC FPGA via PCI so that the POST codes are visbile again in coreboot. Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c 3 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig index fbee7b0..0b0ffe5 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig @@ -4,6 +4,7 @@ def_bool y select DRIVER_INTEL_I210 select INTEL_LPSS_UART_FOR_CONSOLE + select NC_FPGA_POST_CODE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" @@ -12,4 +13,19 @@ int default 2 +config EARLY_PCI_BRIDGE_DEVICE + hex + depends on NC_FPGA_POST_CODE + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + depends on NC_FPGA_POST_CODE + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + depends on NC_FPGA_POST_CODE + default 0xfe800000 + endif # BOARD_SIEMENS_MC_EHL1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc index e011999..3036363 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc @@ -4,6 +4,8 @@ romstage-y += memory.c ramstage-y += gpio.c +all-$(CONFIG_NC_FPGA_POST_CODE) += post.c + SPD_SOURCES = mc_ehl1 # 0b000 LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \ src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c new file mode 100644 index 0000000..c34e253 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/post.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <nc_fpga.h> +#include <types.h> + +void mainboard_post(uint8_t value) +{ + nc_fpga_post(value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Gerrit-Change-Number: 59347 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/siemens/nc_fpga: Add POST code over PCI
by Felix Held (Code Review) 17 Nov '21

17 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59346 ) Change subject: drivers/siemens/nc_fpga: Add POST code over PCI ...................................................................... drivers/siemens/nc_fpga: Add POST code over PCI So far POST codes were mapped on IO port 0x80 inside the NC FPGA which was connected via the LPC bus to the host CPU. On recent x86 generations the LPC bus was replaced with eSPI and not all Siemens boards have the eSPI routed to the NC FPGA. In order to have POST codes visible on those boards the display is accessible via PCI in addition. This patch adds the feature of sending the POST codes to the NC FPGA via a PCI mapped register. Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/drivers/siemens/nc_fpga/Kconfig M src/drivers/siemens/nc_fpga/Makefile.inc M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/siemens/nc_fpga/nc_fpga.h A src/drivers/siemens/nc_fpga/nc_fpga_early.c 5 files changed, 77 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/drivers/siemens/nc_fpga/Kconfig b/src/drivers/siemens/nc_fpga/Kconfig index 1cd7977..f4f1e97 100644 --- a/src/drivers/siemens/nc_fpga/Kconfig +++ b/src/drivers/siemens/nc_fpga/Kconfig @@ -5,3 +5,8 @@ config NC_FPGA_NOTIFY_CB_READY bool default n + +config NC_FPGA_POST_CODE + bool + default n + select EARLY_PCI_BRIDGE diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc index ac2875f..95ec00a 100644 --- a/src/drivers/siemens/nc_fpga/Makefile.inc +++ b/src/drivers/siemens/nc_fpga/Makefile.inc @@ -1,3 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_SIEMENS_NC_FPGA) += nc_fpga.c + +all-$(CONFIG_NC_FPGA_POST_CODE) += nc_fpga_early.c + +ifeq ($(CONFIG_NC_FPGA_POST_CODE),y) +CPPFLAGS_common += -I$(src)/drivers/siemens/nc_fpga +endif diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index 08e8856..0b4c7d4 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -142,9 +142,21 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_fw_done, NULL); #endif +static void nc_fpga_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + + if (CONFIG(NC_FPGA_POST_CODE)) { + /* Re-initialize base address after set_resources for POST display + to work properly.*/ + nc_fpga_remap(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf); + } +} + + static struct device_operations nc_fpga_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = nc_fpga_set_resources, .enable_resources = pci_dev_enable_resources, .init = nc_fpga_init, }; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index 2096de7..39cc04e 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -17,6 +17,7 @@ #define NC_DIAG_FW_DONE 0x10000 #define NC_BL_BRIGHTNESS_OFFSET 0x88 #define NC_BL_PWM_OFFSET 0x8C +#define NC_FPGA_POST_OFFSET 0xE0 #define NC_FANMON_CTRL_OFFSET 0x400 #define MAX_NUM_SENSORS 8 @@ -58,4 +59,7 @@ uint32_t fanmon; } __packed fan_ctrl_t; +void nc_fpga_post(uint8_t value); +void nc_fpga_remap(uint32_t new_mmio); + #endif /* _SIEMENS_NC_FPGA_H_ */ diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c new file mode 100644 index 0000000..6ec0349 --- /dev/null +++ b/src/drivers/siemens/nc_fpga/nc_fpga_early.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmio.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <types.h> + +#include "nc_fpga.h" + +static DEVTREE_CONST uint32_t fpga_bar = CONFIG_EARLY_PCI_MMIO_BASE; +static bool nc_fpga_present = false; + +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0); + uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID); + + if (id != (0x4091 << 16 | PCI_VENDOR_ID_SIEMENS)) + return -1; + + /* Setup base address for BAR0. */ + pci_s_write_config32(pci_dev, PCI_BASE_ADDRESS_0, mmio_base); + /* Enable memory access for pci_dev. */ + u16 reg16 = pci_s_read_config16(pci_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_s_write_config16(pci_dev, PCI_COMMAND, reg16); + nc_fpga_present = true; + + return 0; +} + +void nc_fpga_remap(uint32_t new_mmio) +{ +#if ENV_RAMSTAGE + fpga_bar = new_mmio; +#endif +} + +void nc_fpga_post(uint8_t value) +{ + /* The function pci_earyl_device_probe is called in bootblock and romstage. Make sure + that in these stages the initialization code was successful before the POST code + value is written to the register. */ + if ((ENV_BOOTBLOCK || ENV_ROMSTAGE) && nc_fpga_present == false) + return; + write32((void *)(fpga_bar + NC_FPGA_POST_OFFSET), value); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0 Gerrit-Change-Number: 59346 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Subrata Banik (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59392/comment/9225a858_c5b7f28b PS1, Line 9: please refer to the commit hash 3fd39467b and title that causes this regression ? -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 13:45:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: fsp: Change post codes to lower case
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59393 ) Change subject: fsp: Change post codes to lower case ...................................................................... fsp: Change post codes to lower case Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 --- M src/drivers/intel/fsp1_1/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59393/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index e20d527..6a19b87 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -181,7 +181,7 @@ pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2A) + post_code(0x2a) /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index cac7854..1c905a4 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -295,7 +295,7 @@ #endif before_carstage: - post_code(0x2A) + post_code(0x2a) call bootblock_c_entry /* Never reached */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 Gerrit-Change-Number: 59393 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2
by Meera Ravindranath (Code Review) 17 Nov '21

17 Nov '21

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59392 ) Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2 ...................................................................... mb/intel/adlrvp: Enable CPU PCIe RP 2 Disabling CPU PCIe RP 2 causes regression in NVMe boot on ADL-P RVP boards. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59392/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 8926887..1205234 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -48,6 +48,12 @@ .flags = PCIE_RP_CLK_REQ_DETECT, }" + # Enable CPU PCIE RP 2 using CLK 3 + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_req = 3, + .clk_src = 3, + }" + # Enable PCH PCIE RP 6 using CLK 5 register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 5, -- To view, visit https://review.coreboot.org/c/coreboot/+/59392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882 Gerrit-Change-Number: 59392 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021