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Hello build bot (Jenkins), Subrata Banik,
I'd like you to reexamine a change. Please visit
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Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2
......................................................................
mb/intel/adlrvp: Enable CPU PCIe RP 2
Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59392/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59390 )
Change subject: soc/intel/../thermal: Drop unused `dev` variable in pch_get_ltt_value()
......................................................................
Patch Set 1: Code-Review+2
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59390/comment/f3f51cd5_8e6d2580
PS1, Line 7: variable
parameter
https://review.coreboot.org/c/coreboot/+/59390/comment/4aaffd27_ceef72e8
PS1, Line 9: being
nit: move to next line
https://review.coreboot.org/c/coreboot/+/59390/comment/7b216c8e_81d66438
PS1, Line 10: replaced
present tense (no final `d`): `replace`
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Change subject: soc/intel/../thermal: Compile IA common thermal block in romstage
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/guybrush: Add variant_tpm_gpio_table
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
seems that this patch needs a manual rebase
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