coreboot-gerrit November 2021

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Change in coreboot[master]: mb/intel/adlrvp: Use dedicated VBT files for ADL-M
by Subrata Banik (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58202 ) Change subject: mb/intel/adlrvp: Use dedicated VBT files for ADL-M ...................................................................... Patch Set 3: (1 comment) File src/mainboard/intel/adlrvp/mainboard.c: https://review.coreboot.org/c/coreboot/+/58202/comment/cb9c003d_ef880b9e PS3, Line 79: case ADL_M_LP5: : return "vbt_adlrvp_m_lp5.bin"; nit: if you could move this at line 84 to club ADL-M board Also, in future we can consider adding scalable (as below) structures rather switch cases for multiple level code. This way, we can grow the different SKUs easily. struct vbt_config { uint8_t sku_id; char *file_name; } config[] = { { ADL_P_LP5_1, "vbt_adlrvp_lp5.bin" }, .... }; uint8_t sku_id = get_board_id(); for (int i = 0; i < ARRAY_SIZE(config); i++) if (config[i].sku_id == sku_id) return config[i].file_name; -- To view, visit https://review.coreboot.org/c/coreboot/+/58202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f Gerrit-Change-Number: 58202 Gerrit-PatchSet: 3 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:27:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in qc_blobs[master]: sc7280/ boot and shrm blobs updated
by Julius Werner (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Shelley Chen, Sudheer Amrabadi. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/59076 ) Change subject: sc7280/ boot and shrm blobs updated ...................................................................... Patch Set 2: Verified+1 Code-Review+2 -- To view, visit https://review.coreboot.org/c/qc_blobs/+/59076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I312248e23568c6e1641fd091dd02892d50bd9517 Gerrit-Change-Number: 59076 Gerrit-PatchSet: 2 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:24:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons, Felix Held. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 51: (1 comment) File src/ec/starlabs/merlin/Makefile.inc: https://review.coreboot.org/c/coreboot/+/58343/comment/60bae460_ec21f6ed PS42, Line 18: files_added:: warn_no_ite_fw : : PHONY+=warn_no_ite_fw : warn_no_ite_fw: : printf "\n\t** WARNING **\n" : printf "coreboot has been built without the ITE EC Firmware.\n" : printf "Do not flash this image. Your laptop's power button\n" : printf "may not respond when you press it.\n\n" > Ok, then we need another Kconfig option: `EC_STARLABS_NEED_ITE_BIN` or similar name: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 51 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:07:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume
by Karthik Ramasubramanian (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Andrey Pronin, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 ) Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume ...................................................................... Patch Set 17: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/58870/comment/e33b0b2f_bd516bb2 PS17, Line 403: config PSP_INIT_TPM_ON_S0I3_RESUME Wondering if it should be done in soc/amd/common/psp_verstage/Kconfig. Since Zork also uses PSP Verstage, I think it is required - atleast psp_verstage.c is referring to this config item. -- To view, visit https://review.coreboot.org/c/coreboot/+/58870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Gerrit-Change-Number: 58870 Gerrit-PatchSet: 17 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 16:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp: Rewrite post code hex values in lowercase
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Lee Leahy, Huang Jin, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59393 ) Change subject: drivers/fsp: Rewrite post code hex values in lowercase ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59393/comment/86c3f8ca_f3c3547c PS1, Line 7: fsp: Change post codes to lower case > How about: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 Gerrit-Change-Number: 59393 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 16:52:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/fsp: Rewrite post code hex values in lowercase
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Sean Rhodes, Lee Leahy, Huang Jin, Patrick Rudolph. Hello build bot (Jenkins), Lee Leahy, Angel Pons, Huang Jin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59393 to look at the new patch set (#2). Change subject: drivers/fsp: Rewrite post code hex values in lowercase ...................................................................... drivers/fsp: Rewrite post code hex values in lowercase Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 --- M src/drivers/intel/fsp1_1/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59393/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 Gerrit-Change-Number: 59393 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add variant_tpm_gpio_table
by Karthik Ramasubramanian (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59083 ) Change subject: mb/google/guybrush: Add variant_tpm_gpio_table ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Gerrit-Change-Number: 59083 Gerrit-PatchSet: 8 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 16:38:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Use BusLimit during PCI bus allocation
by Arthur Heymans (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59396 to review the following change. Change subject: soc/intel/xeon_sp: Use BusLimit during PCI bus allocation ...................................................................... soc/intel/xeon_sp: Use BusLimit during PCI bus allocation When probing PCI buses use the stack buslimit instead of 0xff. This could avoid overflowing bus numbers into the next stack. Change-Id: I5f698e3ddb73282d2351cde24091085cd02b9d97 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/chip_common.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/59396/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 47d8f5c..a38aae7 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -497,8 +497,11 @@ get_iiostack_info(&stack_info); for (int s = 0; s < stack_info.no_of_stacks; ++s) { /* only non zero bus no. needs to be enumerated */ - if (stack_info.res[s].BusBase == 0) + if (stack_info.res[s].BusBase == 0) { + /* Update BUS 0 BusLimit */ + dev->link_list->max_subordinate = stack_info.res[s]. BusLimit; continue; + } iiostack_bus = malloc(sizeof(struct bus)); if (iiostack_bus == NULL) @@ -507,6 +510,7 @@ memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); iiostack_bus->secondary = stack_info.res[s].BusBase; iiostack_bus->subordinate = stack_info.res[s].BusBase; + iiostack_bus->max_subordinate = stack_info.res[s].BusLimit; iiostack_bus->dev = NULL; iiostack_bus->children = NULL; iiostack_bus->next = NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/59396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f698e3ddb73282d2351cde24091085cd02b9d97 Gerrit-Change-Number: 59396 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]device/pci_device.c: Add way to limit max bus numbers
by Arthur Heymans (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59395 to review the following change. Change subject: [RFC]device/pci_device.c: Add way to limit max bus numbers ...................................................................... [RFC]device/pci_device.c: Add way to limit max bus numbers By default this limits PCI buses to CONFIG_MMCONF_BUS_NUMBER. Some platforms have multiple PCI root busses (e.g. xeon_sp), where bus numbers are limited. This provides a basic check. On some platforms it looks like programming 0xff to the subordinate bus number confuses and hangs the hardware. Change-Id: I0582b156df1a5f76119a3687886c4d58f2d3ad6f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/pci_device.c M src/include/device/device.h 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59395/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index ba7a1db..ad7a83f 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1339,6 +1339,18 @@ if (state == PCI_ROUTE_SCAN) { link->secondary = parent->subordinate + 1; link->subordinate = link->secondary + dev->hotplug_buses; + link->max_subordinate = parent->max_subordinate + ? parent->max_subordinate + : (CONFIG_MMCONF_BUS_NUMBER - 1); + } + + if (link->secondary > link->max_subordinate) + die("%s: No more busses available!\n", __func__); + + /* This ought to only happen with hotplug buses. */ + if (link->subordinate > link->max_subordinate) { + printk(BIOS_WARNING, "%s: Limiting subordinate busses\n", __func__); + link->subordinate = link->max_subordinate; } if (state == PCI_ROUTE_CLOSE) { @@ -1348,7 +1360,7 @@ } else if (state == PCI_ROUTE_SCAN) { primary = parent->secondary; secondary = link->secondary; - subordinate = 0xff; /* MAX PCI_BUS number here */ + subordinate = link->max_subordinate; } else if (state == PCI_ROUTE_FINAL) { primary = parent->secondary; secondary = link->secondary; diff --git a/src/include/device/device.h b/src/include/device/device.h index 8610e0a..f8e81b6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -82,7 +82,8 @@ uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ - uint16_t subordinate; /* max subordinate bus number */ + uint16_t subordinate; /* subordinate bus number */ + uint16_t max_subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ uint32_t hcdn_reg; /* For HyperTransport link */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582b156df1a5f76119a3687886c4d58f2d3ad6f Gerrit-Change-Number: 59395 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Add variant_tpm_gpio_table
by Rob Barnes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59083 ) Change subject: mb/google/guybrush: Add variant_tpm_gpio_table ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Rebased and resolved conflicts. -- To view, visit https://review.coreboot.org/c/coreboot/+/59083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f Gerrit-Change-Number: 59083 Gerrit-PatchSet: 8 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 16:33:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2021