coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: crossgcc: Upgrade acpica to 20210930 version
by HAOUAS Elyes (Code Review) 17 Nov '21

17 Nov '21

HAOUAS Elyes has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/59174 ) Change subject: crossgcc: Upgrade acpica to 20210930 version ...................................................................... crossgcc: Upgrade acpica to 20210930 version Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20210930_iasl.patch D util/crossgcc/sum/acpica-unix2-20210331.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20210930.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59174/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37 Gerrit-Change-Number: 59174 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya/var/taeko: Correct touchpad GPE settings
by Tim Wawrzynczak (Code Review) 17 Nov '21

17 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59345 ) Change subject: mb/google/brya/var/taeko: Correct touchpad GPE settings ...................................................................... mb/google/brya/var/taeko: Correct touchpad GPE settings Correct GPE settings so touchpad can wake up DUT. BUG=b:206526991 TEST=emerge-brya coreboot and builds without error Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index a482363..04cf51b 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -330,7 +330,7 @@ register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "wake" = "GPE0_DW2_15" + register "wake" = "GPE0_DW2_14" register "probed" = "1" device i2c 15 on end end @@ -338,7 +338,7 @@ register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "generic.wake" = "GPE0_DW2_15" + register "generic.wake" = "GPE0_DW2_14" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end -- To view, visit https://review.coreboot.org/c/coreboot/+/59345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24 Gerrit-Change-Number: 59345 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/taeko: disabled autonomous GPIO power management
by Tim Wawrzynczak (Code Review) 17 Nov '21

17 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59325 ) Change subject: mb/google/brya/var/taeko: disabled autonomous GPIO power management ...................................................................... mb/google/brya/var/taeko: disabled autonomous GPIO power management Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:205315500 TEST=emerge-brya coreboot and test that DUT can boot to OS. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index d6d7c9b..a482363 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -41,6 +41,16 @@ end end chip soc/intel/alderlake + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, -- To view, visit https://review.coreboot.org/c/coreboot/+/59325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Gerrit-Change-Number: 59325 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/taeko: disabled autonomous GPIO power management
by Tim Wawrzynczak (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Joey Peng. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59325 ) Change subject: mb/google/brya/var/taeko: disabled autonomous GPIO power management ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Hi Tim, I have tested the CLs in your link but seems that it cannot boot up Taeko with older Cr50 fi […] Hm, that CL shouldn't take effect until after booting to the OS... I meant in combination with this one if that was not clear 😊 but I got confirmation from another ODM about the behavior, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8 Gerrit-Change-Number: 59325 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 18:43:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/variants/brask: Set PL and PsysPL
by Tim Wawrzynczak (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee, Alan Huang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58241 ) Change subject: mb/google/brya/variants/brask: Set PL and PsysPL ...................................................................... Patch Set 12: (5 comments) File src/mainboard/google/brya/variants/baseboard/brask/ramstage.c: https://review.coreboot.org/c/coreboot/+/58241/comment/1f51d9fb_2ece8b0e PS12, Line 20: bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, if you make this a static function then you don't need the prototype above. https://review.coreboot.org/c/coreboot/+/58241/comment/6f954e8f_61861689 PS12, Line 121: nit: extra blank line File src/mainboard/google/brya/variants/brask/ramstage.c: PS12: Adding this file should be a separate change on top of the rest https://review.coreboot.org/c/coreboot/+/58241/comment/62b930f6_0228b28a PS12, Line 21: * nit: space after `)` https://review.coreboot.org/c/coreboot/+/58241/comment/6924eb62_8fcaeedb PS12, Line 41: barral `barrel` -- To view, visit https://review.coreboot.org/c/coreboot/+/58241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248 Gerrit-Change-Number: 58241 Gerrit-PatchSet: 12 Gerrit-Owner: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hou-hsun Lee <hou-hsun.lee(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 18:20:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ChromeOS: Add legacy mainboard_ec_running_ro()
by Julius Werner (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Kyösti Mälkki. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58896 ) Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ...................................................................... Patch Set 7: (1 comment) File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/58896/comment/369d675e_442681b4 PS7, Line 67: } > I am asking the same question in pathcset #5, I don't know what should be done with this ACPI table […] I think ideally it just keeps containing the same data it had on boot? None of the info here would change across S3 and need to be regenerated. I don't know how these ACPI tables work, do they have to be rewritten from scratch on resume or can you just keep the same table you had before suspend around? What does the existing code do? -- To view, visit https://review.coreboot.org/c/coreboot/+/58896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Gerrit-Change-Number: 58896 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:59:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in qc_blobs[master]: sc7280/ boot and shrm blobs updated
by Shelley Chen (Code Review) 17 Nov '21

17 Nov '21

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/qc_blobs/+/59076 ) Change subject: sc7280/ boot and shrm blobs updated ...................................................................... sc7280/ boot and shrm blobs updated Change-Id: I312248e23568c6e1641fd091dd02892d50bd9517 --- M sc7280/boot/Pmic.bin M sc7280/boot/QcLib.elf M sc7280/boot/Release_Notes.txt M sc7280/shrm/Release_Notes.txt M sc7280/shrm/shrm.elf 5 files changed, 42 insertions(+), 0 deletions(-) Approvals: Julius Werner: Verified; Looks good to me, approved Shelley Chen: Looks good to me, approved diff --git a/sc7280/boot/Pmic.bin b/sc7280/boot/Pmic.bin index 3238f89..25a65b4 100644 --- a/sc7280/boot/Pmic.bin +++ b/sc7280/boot/Pmic.bin Binary files differ diff --git a/sc7280/boot/QcLib.elf b/sc7280/boot/QcLib.elf index ea1a05e..423dffc 100644 --- a/sc7280/boot/QcLib.elf +++ b/sc7280/boot/QcLib.elf Binary files differ diff --git a/sc7280/boot/Release_Notes.txt b/sc7280/boot/Release_Notes.txt index 6c647ac..0718f2b 100644 --- a/sc7280/boot/Release_Notes.txt +++ b/sc7280/boot/Release_Notes.txt @@ -1,3 +1,25 @@ +================== Release 00020 ================================ +This Release Notes file covers these blobs: + * dcb.bin + * Pmic.bin + * QcLib.elf + +Version : 00020 + +Release Date : Nov, 2021 + +Supported Silicon : SC7280 + +Changes since last version: + * DDR Struct info pass + +Above Bins were used to generate coreboot image. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report + ================== Release 00016 ================================ This Release Notes file covers these blobs: * dcb.bin diff --git a/sc7280/shrm/Release_Notes.txt b/sc7280/shrm/Release_Notes.txt index efa6434..82559d5 100644 --- a/sc7280/shrm/Release_Notes.txt +++ b/sc7280/shrm/Release_Notes.txt @@ -1,3 +1,23 @@ +================== Release 00020 ================================ +This Release Notes file covers these blobs: + * shrm.elf + +Version : 00020 + +Release Date : Nov, 2021 + +Supported Silicon : SC7280 + +Changes since last version: + * DDR Struct info pass + +Above Bins were used to generate coreboot image. + +No special instructions, requirements or dependencies, files must be +present in this folder to be pulled in during coreboot build + +Errata : Nothing to report + ================== Release 00016 ================================ This Release Notes file covers these blobs: * shrm.elf diff --git a/sc7280/shrm/shrm.elf b/sc7280/shrm/shrm.elf index e940e33..57666a0 100644 --- a/sc7280/shrm/shrm.elf +++ b/sc7280/shrm/shrm.elf Binary files differ -- To view, visit https://review.coreboot.org/c/qc_blobs/+/59076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I312248e23568c6e1641fd091dd02892d50bd9517 Gerrit-Change-Number: 59076 Gerrit-PatchSet: 2 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: merged

1 0

Change in qc_blobs[master]: sc7280/boot-shrm: Updated qclib blobs binaries and release notes
by Shelley Chen (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/59009 ) Change subject: sc7280/boot-shrm: Updated qclib blobs binaries and release notes ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: is this still needed? I see a later update: CB:59076 -- To view, visit https://review.coreboot.org/c/qc_blobs/+/59009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I9e50d097cc757a2ad8638c9e1b9641a75da530d0 Gerrit-Change-Number: 59009 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:30:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Add Acoustic noise mitigation UPDs
by Tim Wawrzynczak (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Chen Wisley, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58944 ) Change subject: soc/intel/alderlake: Add Acoustic noise mitigation UPDs ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6 Gerrit-Change-Number: 58944 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:29:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/../thermal: Add support for thermal config behind PMC device
by Tim Wawrzynczak (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Maulik V Vaghela, Subrata Banik, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59209 ) Change subject: soc/intel/../thermal: Add support for thermal config behind PMC device ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/thermal/thermal.c: https://review.coreboot.org/c/coreboot/+/59209/comment/401eced1_72fdd1c2 PS8, Line 106: /* Enable thermal sensor power management using PMC PCH device */ : static void pch_pmc_thermal_configuration(void) : { : struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); : uintptr_t pmc_bar = soc_read_pmc_base(); : : struct pmc_thermal_config { : void (*func)(uintptr_t addr, uint32_t data); : uint16_t offset; : uint32_t value; : } config[] = { : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_CTEN, : .value = PMC_PWRM_THERMAL_CTEN_CPDEN | PMC_PWRM_THERMAL_CTEN_CTENLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_ECRPTEN, : .value = PMC_PWRM_THERMAL_ECRPTEN_EN_RPT : | PMC_PWRM_THERMAL_ECRPTEN_ECRPTENLOCK, : }, : { : .func = write32p, : .offset = PMC_PWRM_THERMAL_TL, : .value = pch_get_ltt_value(dev) | PMC_PWRM_THERMAL_TL_TTEN : | PMC_PWRM_THERMAL_TL_TLLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_PHLC, : .value = PMC_PWRM_THERMAL_PHLC_PHLCLOCK, : }, : { : .func = thermal_or32, : .offset = PMC_PWRM_THERMAL_TLEN, : .value = PMC_PWRM_THERMAL_TLEN_TLENLOCK, : }, : }; : : for (int i = 0; i < ARRAY_SIZE(config); i++) : config[i].func(pmc_bar + config[i].offset, config[i].value); : } : > @Tim, any further thoughts ? I am really not liking the #define PCH_DEVFN_THERMAL DEADCODE thing... Here's my suggestion: 1) Add a new file thermal-pmc.c here in this folder 2) thermal.c and thermal-pmc.c both provide the same public interface, i.e., the functions exported in intelblocks/thermal.h, but their implementation can be different, and then the Makefile.inc just builds the correct one depending on SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC. They have different register layouts for LTT, etc. so instead of just using the preprocessor everywhere, a separate file would be cleaner. -- To view, visit https://review.coreboot.org/c/coreboot/+/59209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0 Gerrit-Change-Number: 59209 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 17:28:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021