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Change in coreboot[master]: soc/mediatek/mt8186: Add I2C driver support
by Hung-Te Lin (Code Review) 17 Nov '21

17 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59296 ) Change subject: soc/mediatek/mt8186: Add I2C driver support ...................................................................... soc/mediatek/mt8186: Add I2C driver support Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang <housong.zhang(a)mediatek.corp-partner.google.com> Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/Makefile.inc A src/soc/mediatek/mt8186/i2c.c A src/soc/mediatek/mt8186/include/soc/i2c.h 3 files changed, 217 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index cb472ce..0646f6c 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += ../common/flash_controller.c bootblock-y += gic.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -16,6 +17,7 @@ verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c @@ -26,6 +28,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c @@ -37,6 +40,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8186/i2c.c b/src/soc/mediatek/mt8186/i2c.c new file mode 100644 index 0000000..a7f72ac --- /dev/null +++ b/src/soc/mediatek/mt8186/i2c.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#include <assert.h> +#include <console/console.h> +#include <device/mmio.h> +#include <device/i2c_simple.h> +#include <soc/i2c.h> +#include <soc/gpio.h> +#include <timer.h> + +struct mtk_i2c mtk_i2c_bus_controller[] = { + [0] = { + .i2c_regs = (void *)(I2C0_BASE), + .i2c_dma_regs = (void *)(I2C0_DMA_BASE), + }, + [1] = { + .i2c_regs = (void *)(I2C1_BASE), + .i2c_dma_regs = (void *)(I2C1_DMA_BASE), + }, + [2] = { + .i2c_regs = (void *)(I2C2_BASE), + .i2c_dma_regs = (void *)(I2C2_DMA_BASE), + }, + [3] = { + .i2c_regs = (void *)(I2C3_BASE), + .i2c_dma_regs = (void *)(I2C3_DMA_BASE), + }, + [4] = { + .i2c_regs = (void *)(I2C4_BASE), + .i2c_dma_regs = (void *)(I2C4_DMA_BASE), + }, + [5] = { + .i2c_regs = (void *)(I2C5_BASE), + .i2c_dma_regs = (void *)(I2C5_DMA_BASE), + }, + [6] = { + .i2c_regs = (void *)(I2C6_BASE), + .i2c_dma_regs = (void *)(I2C6_DMA_BASE), + }, + [7] = { + .i2c_regs = (void *)(I2C7_BASE), + .i2c_dma_regs = (void *)(I2C7_DMA_BASE), + }, + [8] = { + .i2c_regs = (void *)(I2C8_BASE), + .i2c_dma_regs = (void *)(I2C8_DMA_BASE), + }, + [9] = { + .i2c_regs = (void *)(I2C9_BASE), + .i2c_dma_regs = (void *)(I2C9_DMA_BASE), + }, +}; + +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + [0] = { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + [1] = { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + [2] = { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + [3] = { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + [4] = { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + [5] = { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + [6] = { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + [7] = { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + [8] = { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + [9] = { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) +{ + mtk_i2c_speed_init(bus, speed); + mtk_i2c_set_gpio_pinmux(bus); +} + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) +{ + printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n", + read32(&regs->ltiming), + read32(&regs->clock_div)); +} + +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div); + write32(&regs->timing, bus_ctrl->ac_timing.htiming); + write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming); + write32(&regs->hs, bus_ctrl->ac_timing.hs); + write32(&regs->ext_conf, bus_ctrl->ac_timing.ext); +} diff --git a/src/soc/mediatek/mt8186/include/soc/i2c.h b/src/soc/mediatek/mt8186/include/soc/i2c.h new file mode 100644 index 0000000..4024e7d --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/i2c.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#ifndef SOC_MEDIATEK_MT8186_I2C_H +#define SOC_MEDIATEK_MT8186_I2C_H + +#include <soc/i2c_common.h> +#include <soc/pll.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, + I2C8, + I2C9, +}; + +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIV2PLL_HZ / 20) + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); + +#endif /* SOC_MEDIATEK_MT8186_I2C_H */ 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Gerrit-Change-Number: 59296 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: move i2c function to common folder
by Hung-Te Lin (Code Review) 17 Nov '21

17 Nov '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59295 ) Change subject: soc/mediatek: move i2c function to common folder ...................................................................... soc/mediatek: move i2c function to common folder Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/i2c.h M src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/i2c.h M src/soc/mediatek/mt8195/i2c.c M src/soc/mediatek/mt8195/include/soc/i2c.h 10 files changed, 297 insertions(+), 258 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 1e713db..b9b02cd 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -8,6 +8,7 @@ #include <symbols.h> #include <device/mmio.h> #include <soc/i2c.h> +#include <soc/i2c_common.h> #include <device/i2c_simple.h> const struct i2c_spec_values standard_mode_spec = { @@ -31,7 +32,15 @@ .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, }; -__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { /* do nothing */ } +__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) +{ + /* do nothing */ +} + +__weak void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + /* do nothing */ +} const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed) { @@ -281,6 +290,14 @@ seg[0].slave == seg[1].slave); } +static int mtk_i2c_max_step_cnt(uint32_t target_speed) +{ + if (target_speed > I2C_SPEED_FAST_PLUS) + return MAX_HS_STEP_CNT_DIV; + else + return MAX_STEP_CNT_DIV; +} + int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int seg_count) { @@ -307,3 +324,230 @@ return ret; } + +/* + * Check and calculate i2c ac-timing. + * + * Hardware design: + * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src + * xxx_cnt_div = spec->min_xxx_ns / sample_ns + * + * The calculation of sample_ns is rounded down; + * otherwise xxx_cnt_div would be greater than the smallest spec. + * The sda_timing is chosen as the middle value between + * the largest and smallest. + */ +int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, + uint32_t check_speed, + uint32_t step_cnt, + uint32_t sample_cnt) +{ + const struct i2c_spec_values *spec; + uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt; + uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100; + uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src; + struct mtk_i2c_ac_timing *ac_timing; + + spec = mtk_i2c_get_spec(check_speed); + + clk_ns = NSECS_PER_SEC / clk_src; + + su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); + if (su_sta_cnt > max_sta_cnt) + return -1; + + low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); + max_step_cnt = mtk_i2c_max_step_cnt(check_speed); + if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) { + if (low_cnt > step_cnt) { + high_cnt = 2 * step_cnt - low_cnt; + } else { + high_cnt = step_cnt; + low_cnt = step_cnt; + } + } else { + return -2; + } + + sda_max = spec->max_hd_dat_ns / sample_ns; + if (sda_max > low_cnt) + sda_max = 0; + + sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); + if (sda_min < low_cnt) + sda_min = 0; + + if (sda_min > sda_max) + return -3; + + ac_timing = &mtk_i2c_bus_controller[bus].ac_timing; + if (check_speed > I2C_SPEED_FAST_PLUS) { + ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8); + ac_timing->ltiming &= ~GENMASK(15, 9); + ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9); + ac_timing->ext &= ~GENMASK(7, 1); + ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0); + } else { + ac_timing->htiming = (sample_cnt << 8) | (high_cnt); + ac_timing->ltiming = (sample_cnt << 6) | (low_cnt); + ac_timing->ext = (su_sta_cnt << 8) | (1 << 0); + } + + return 0; +} + +/* + * Calculate i2c port speed. + * + * Hardware design: + * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) + * clock_div: fixed in hardware, but may be various in different SoCs + * + * To calculate sample_cnt and step_cnt, we pick the highest bus frequency + * that is still no larger than i2c->speed_hz. + */ +int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, + uint32_t target_speed, + uint32_t *timing_step_cnt, + uint32_t *timing_sample_cnt) +{ + uint32_t step_cnt; + uint32_t sample_cnt; + uint32_t max_step_cnt; + uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV; + uint32_t base_step_cnt; + uint32_t opt_div; + uint32_t best_mul; + uint32_t cnt_mul; + uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div; + int32_t clock_div_constraint = 0; + int success = 0; + + if (target_speed > I2C_SPEED_HIGH) + target_speed = I2C_SPEED_HIGH; + + max_step_cnt = mtk_i2c_max_step_cnt(target_speed); + base_step_cnt = max_step_cnt; + + /* Find the best combination */ + opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); + best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; + + /* Search for the best pair (sample_cnt, step_cnt) with + * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV + * 0 < step_cnt < max_step_cnt + * sample_cnt * step_cnt >= opt_div + * optimizing for sample_cnt * step_cnt being minimal + */ + for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { + if (sample_cnt == 1) { + if (clk_div != 0) + clock_div_constraint = 1; + else + clock_div_constraint = 0; + } else { + if (clk_div > 1) + clock_div_constraint = 1; + else if (clk_div == 0) + clock_div_constraint = -1; + else + clock_div_constraint = 0; + } + + step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt); + if (step_cnt > max_step_cnt) + continue; + + cnt_mul = step_cnt * sample_cnt; + if (cnt_mul >= best_mul) + continue; + + if (mtk_i2c_check_ac_timing(bus, clk_src, + target_speed, step_cnt - 1, + sample_cnt - 1)) + continue; + + success = 1; + best_mul = cnt_mul; + base_sample_cnt = sample_cnt; + base_step_cnt = step_cnt; + if (best_mul == opt_div + clock_div_constraint) + break; + + } + + if (!success) + return -1; + + sample_cnt = base_sample_cnt; + step_cnt = base_step_cnt; + + if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) > + target_speed) + return -1; + + *timing_step_cnt = step_cnt - 1; + *timing_sample_cnt = sample_cnt - 1; + + return 0; +} + +void mtk_i2c_speed_init(uint8_t bus, uint32_t speed) +{ + uint32_t max_clk_div = MAX_CLOCK_DIV; + uint32_t clk_src, clk_div, step_cnt, sample_cnt; + uint32_t l_step_cnt, l_sample_cnt; + uint32_t timing_reg_value, ltiming_reg_value; + struct mtk_i2c *bus_ctrl; + + if (bus >= I2C_BUS_NUMBER) { + printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus); + return; + } + + bus_ctrl = &mtk_i2c_bus_controller[bus]; + + for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { + clk_src = I2C_CLK_HZ / clk_div; + bus_ctrl->ac_timing.inter_clk_div = clk_div - 1; + + if (speed > I2C_SPEED_FAST_PLUS) { + /* Set master code speed register */ + if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST, + &l_step_cnt, &l_sample_cnt)) + continue; + + timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; + + /* Set the high speed mode register */ + if (mtk_i2c_calculate_speed(bus, clk_src, speed, + &step_cnt, &sample_cnt)) + continue; + + ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | + (sample_cnt << 12) | (step_cnt << 9); + bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); + } else { + if (mtk_i2c_calculate_speed(bus, clk_src, speed, + &l_step_cnt, &l_sample_cnt)) + continue; + + timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; + + /* Disable the high speed transaction */ + bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; + + ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; + } + + break; + } + + if (clk_div > max_clk_div) { + printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus); + return; + } + + /* Init i2c bus timing register. */ + mtk_i2c_config_timing(bus_ctrl->i2c_regs, bus_ctrl); +} diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 72ec46a..7df1ac5 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -143,4 +143,15 @@ const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed); void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs); +int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, + uint32_t check_speed, + uint32_t step_cnt, + uint32_t sample_cnt); +int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, + uint32_t target_speed, + uint32_t *timing_step_cnt, + uint32_t *timing_sample_cnt); +void mtk_i2c_speed_init(uint8_t bus, uint32_t speed); +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl); + #endif diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index ff803c3..dd4629d 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -6,9 +6,6 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/i2c.h> -#include <soc/pll.h> - -#define I2C_CLK_HZ (AXI_HZ / 16) struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ @@ -52,6 +49,9 @@ } }; +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + #define I2CTAG "[I2C][PL] " #if CONFIG(DEBUG_I2C) diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h index e6f0140..02a2181 100644 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8173_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -35,6 +36,10 @@ uint32_t transfer_aux_len; }; +#define I2C_CLK_HZ (AXI_HZ / 16) +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 + check_member(mt_i2c_regs, debug_stat, 0x64); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index 3e53a72..193f4b9 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -2,12 +2,9 @@ #include <assert.h> #include <device/mmio.h> -#include <soc/pll.h> #include <soc/i2c.h> #include <soc/gpio.h> -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) - struct mtk_i2c mtk_i2c_bus_controller[] = { /* i2c0 setting */ { @@ -52,7 +49,8 @@ }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -103,7 +101,7 @@ } } -static void mtk_i2c_speed_init(uint8_t bus) +static void mtk_i2c_speed_init_soc(uint8_t bus) { uint8_t step_div; const uint8_t clock_div = 5; @@ -132,7 +130,7 @@ void mtk_i2c_bus_init(uint8_t bus) { - mtk_i2c_speed_init(bus); + mtk_i2c_speed_init_soc(bus); mtk_i2c_set_gpio_pinmux(bus); } diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h index e70cf47..ebe75fa 100644 --- a/src/soc/mediatek/mt8183/include/soc/i2c.h +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -39,6 +40,10 @@ uint32_t rollback; }; +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +#define I2C_BUS_NUMBER 7 +#define MAX_CLOCK_DIV 32 + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c index a76b039..5f1e3a0 100644 --- a/src/soc/mediatek/mt8192/i2c.c +++ b/src/soc/mediatek/mt8192/i2c.c @@ -2,11 +2,9 @@ #include <assert.h> #include <device/mmio.h> -#include <soc/pll.h> #include <soc/i2c.h> #include <soc/gpio.h> -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) #define I2C_FULL_DUTY 100 #define I2C_HALF_DUTY 50 #define I2C_ADJUSTED_DUTY 45 @@ -64,7 +62,8 @@ }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -127,7 +126,7 @@ } } -static void mtk_i2c_speed_init(uint8_t bus) +static void mtk_i2c_speed_init_soc(uint8_t bus) { uint8_t step_div; const uint8_t clock_div = 5; @@ -178,7 +177,7 @@ void mtk_i2c_bus_init(uint8_t bus) { - mtk_i2c_speed_init(bus); + mtk_i2c_speed_init_soc(bus); mtk_i2c_set_gpio_pinmux(bus); } diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h index 72a9af1..fbf41e6 100644 --- a/src/soc/mediatek/mt8192/include/soc/i2c.h +++ b/src/soc/mediatek/mt8192/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8192_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -39,6 +40,10 @@ uint32_t rollback; }; +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus); diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c index 1a10eef..b401b79 100644 --- a/src/soc/mediatek/mt8195/i2c.c +++ b/src/soc/mediatek/mt8195/i2c.c @@ -4,13 +4,10 @@ #include <console/console.h> #include <device/mmio.h> #include <device/i2c_simple.h> -#include <soc/pll.h> #include <soc/i2c.h> #include <soc/gpio.h> #include <timer.h> -#define I2C_CLK_HZ (UNIVPLL_HZ / 20) - struct mtk_i2c mtk_i2c_bus_controller[] = { [0] = { .i2c_regs = (void *)(I2C_BASE), @@ -54,7 +51,8 @@ }, }; -#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); struct pad_func { gpio_t gpio; @@ -111,245 +109,6 @@ } } -static int mtk_i2c_max_step_cnt(uint32_t target_speed) -{ - if (target_speed > I2C_SPEED_FAST_PLUS) - return MAX_HS_STEP_CNT_DIV; - else - return MAX_STEP_CNT_DIV; -} - -/* - * Check and calculate i2c ac-timing. - * - * Hardware design: - * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src - * xxx_cnt_div = spec->min_xxx_ns / sample_ns - * - * The calculation of sample_ns is rounded down; - * otherwise xxx_cnt_div would be greater than the smallest spec. - * The sda_timing is chosen as the middle value between - * the largest and smallest. - */ -static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, - uint32_t check_speed, - uint32_t step_cnt, - uint32_t sample_cnt) -{ - const struct i2c_spec_values *spec; - uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt; - uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100; - uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src; - struct mtk_i2c_ac_timing *ac_timing; - - spec = mtk_i2c_get_spec(check_speed); - - clk_ns = NSECS_PER_SEC / clk_src; - - su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); - if (su_sta_cnt > max_sta_cnt) - return -1; - - low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); - max_step_cnt = mtk_i2c_max_step_cnt(check_speed); - if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) { - if (low_cnt > step_cnt) { - high_cnt = 2 * step_cnt - low_cnt; - } else { - high_cnt = step_cnt; - low_cnt = step_cnt; - } - } else { - return -2; - } - - sda_max = spec->max_hd_dat_ns / sample_ns; - if (sda_max > low_cnt) - sda_max = 0; - - sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); - if (sda_min < low_cnt) - sda_min = 0; - - if (sda_min > sda_max) - return -3; - - ac_timing = &mtk_i2c_bus_controller[bus].ac_timing; - if (check_speed > I2C_SPEED_FAST_PLUS) { - ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8); - ac_timing->ltiming &= ~GENMASK(15, 9); - ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9); - ac_timing->ext &= ~GENMASK(7, 1); - ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0); - } else { - ac_timing->htiming = (sample_cnt << 8) | (high_cnt); - ac_timing->ltiming = (sample_cnt << 6) | (low_cnt); - ac_timing->ext = (su_sta_cnt << 8) | (1 << 0); - } - - return 0; -} - -/* - * Calculate i2c port speed. - * - * Hardware design: - * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) - * clock_div: fixed in hardware, but may be various in different SoCs - * - * To calculate sample_cnt and step_cnt, we pick the highest bus frequency - * that is still no larger than i2c->speed_hz. - */ -static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, - uint32_t target_speed, - uint32_t *timing_step_cnt, - uint32_t *timing_sample_cnt) -{ - uint32_t step_cnt; - uint32_t sample_cnt; - uint32_t max_step_cnt; - uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV; - uint32_t base_step_cnt; - uint32_t opt_div; - uint32_t best_mul; - uint32_t cnt_mul; - uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div; - int32_t clock_div_constraint = 0; - int success = 0; - - if (target_speed > I2C_SPEED_HIGH) - target_speed = I2C_SPEED_HIGH; - - max_step_cnt = mtk_i2c_max_step_cnt(target_speed); - base_step_cnt = max_step_cnt; - - /* Find the best combination */ - opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); - best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; - - /* Search for the best pair (sample_cnt, step_cnt) with - * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV - * 0 < step_cnt < max_step_cnt - * sample_cnt * step_cnt >= opt_div - * optimizing for sample_cnt * step_cnt being minimal - */ - for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { - if (sample_cnt == 1) { - if (clk_div != 0) - clock_div_constraint = 1; - else - clock_div_constraint = 0; - } else { - if (clk_div > 1) - clock_div_constraint = 1; - else if (clk_div == 0) - clock_div_constraint = -1; - else - clock_div_constraint = 0; - } - - step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt); - if (step_cnt > max_step_cnt) - continue; - - cnt_mul = step_cnt * sample_cnt; - if (cnt_mul >= best_mul) - continue; - - if (mtk_i2c_check_ac_timing(bus, clk_src, - target_speed, step_cnt - 1, - sample_cnt - 1)) - continue; - - success = 1; - best_mul = cnt_mul; - base_sample_cnt = sample_cnt; - base_step_cnt = step_cnt; - if (best_mul == opt_div + clock_div_constraint) - break; - - } - - if (!success) - return -1; - - sample_cnt = base_sample_cnt; - step_cnt = base_step_cnt; - - if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) > - target_speed) - return -1; - - *timing_step_cnt = step_cnt - 1; - *timing_sample_cnt = sample_cnt - 1; - - return 0; -} - -static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed) -{ - uint32_t max_clk_div = MAX_CLOCK_DIV; - uint32_t clk_src, clk_div, step_cnt, sample_cnt; - uint32_t l_step_cnt, l_sample_cnt; - uint32_t timing_reg_value, ltiming_reg_value; - struct mtk_i2c *bus_ctrl; - - if (bus >= I2C_BUS_NUMBER) { - printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus); - return; - } - - bus_ctrl = &mtk_i2c_bus_controller[bus]; - - for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { - clk_src = I2C_CLK_HZ / clk_div; - bus_ctrl->ac_timing.inter_clk_div = clk_div - 1; - - if (speed > I2C_SPEED_FAST_PLUS) { - /* Set master code speed register */ - if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST, - &l_step_cnt, &l_sample_cnt)) - continue; - - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - - /* Set the high speed mode register */ - if (mtk_i2c_calculate_speed(bus, clk_src, speed, - &step_cnt, &sample_cnt)) - continue; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | - (sample_cnt << 12) | (step_cnt << 9); - bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); - } else { - if (mtk_i2c_calculate_speed(bus, clk_src, speed, - &l_step_cnt, &l_sample_cnt)) - continue; - - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - - /* Disable the high speed transaction */ - bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; - } - - break; - } - - if (clk_div > max_clk_div) { - printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus); - return; - } - - /* Init i2c bus timing register */ - write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div); - write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming); - write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming); - write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs); - write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext); -} - void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) { mtk_i2c_speed_init(bus, speed); @@ -362,3 +121,12 @@ read32(&regs->ltiming), read32(&regs->clock_div)); } + +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div); + write32(&regs->timing, bus_ctrl->ac_timing.htiming); + write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming); + write32(&regs->hs, bus_ctrl->ac_timing.hs); + write32(&regs->ext_conf, bus_ctrl->ac_timing.ext); +} diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h index 743faa1..bbdc9e8 100644 --- a/src/soc/mediatek/mt8195/include/soc/i2c.h +++ b/src/soc/mediatek/mt8195/include/soc/i2c.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8195_I2C_H #include <soc/i2c_common.h> +#include <soc/pll.h> /* I2C Register */ struct mt_i2c_regs { @@ -52,7 +53,10 @@ I2C7, }; +#define I2C_BUS_NUMBER 8 #define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) + check_member(mt_i2c_regs, multi_dma, 0xf8c); void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); -- To view, visit https://review.coreboot.org/c/coreboot/+/59295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Gerrit-Change-Number: 59295 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common:[TEST] Disable CSE RW Update
by Sridhar Siricilla (Code Review) 17 Nov '21

17 Nov '21

Sridhar Siricilla has removed Patrick Rudolph from this change. ( https://review.coreboot.org/c/coreboot/+/59387 ) Change subject: soc/intel/common:[TEST] Disable CSE RW Update ...................................................................... Removed reviewer Patrick Rudolph. -- To view, visit https://review.coreboot.org/c/coreboot/+/59387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234b53943edeac7a16d57ac28dbe9055f3509010 Gerrit-Change-Number: 59387 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: soc/intel/common:[TEST] Disable CSE RW Update
by Sridhar Siricilla (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59387 to look at the new patch set (#2). Change subject: soc/intel/common:[TEST] Disable CSE RW Update ...................................................................... soc/intel/common:[TEST] Disable CSE RW Update Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I234b53943edeac7a16d57ac28dbe9055f3509010 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/59387/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234b53943edeac7a16d57ac28dbe9055f3509010 Gerrit-Change-Number: 59387 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Angel Pons (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Sean Rhodes, Andy Pont, Paul Menzel, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58343 ) Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... Patch Set 43: Code-Review+1 (22 comments) File src/ec/starlabs/merlin/Makefile.inc: https://review.coreboot.org/c/coreboot/+/58343/comment/74ee936d_5e6b7e11 PS42, Line 7: $(CONFIG_EC_VARIANT_DIR) I'm pretty sure you need to use `strip_quotes` here, in CB:29447 I ran into the same issue: EC_VARIANT_DIR := $(call strip_quotes, $(CONFIG_EC_VARIANT_DIR)) CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR) https://review.coreboot.org/c/coreboot/+/58343/comment/8a77e12d_7fe632ed PS42, Line 9: ifeq ($(CONFIG_EC_STARLABS_ITE),y) This should also guard the lines above, this file is unconditionally included. https://review.coreboot.org/c/coreboot/+/58343/comment/e01709ac_def8d011 PS42, Line 11: smm-$(CONFIG_DEBUG_SMI) += ec.c I'm pretty sure this isn't needed, and causes build errors when `DEBUG_SMI` is enabled. I'd remove it. https://review.coreboot.org/c/coreboot/+/58343/comment/6cd6ddb3_223ab2c6 PS42, Line 18: files_added:: warn_no_ite_fw : : PHONY+=warn_no_ite_fw : warn_no_ite_fw: : printf "\n\t** WARNING **\n" : printf "coreboot has been built without the ITE EC Firmware.\n" : printf "Do not flash this image. Your laptop's power button\n" : printf "may not respond when you press it.\n\n" Shouldn't this be in the `else` branch of `ifeq ($(CONFIG_EC_STARLABS_IT_BIN),y)`? Currently, the warning is only printed when `EC_STARLABS_IT_BIN` is set but `EC_STARLABS_IT_BIN_PATH` is completely empty (which I think never happens). File src/ec/starlabs/merlin/ec.c: https://review.coreboot.org/c/coreboot/+/58343/comment/71991a51_d9cd8918 PS42, Line 47: u8 chipid1 = pnp_read_index(dev->path.pnp.port, ITE_CHIPID1); : u8 chipid2 = pnp_read_index(dev->path.pnp.port, ITE_CHIPID2); nit: `chipid1` and `chipid2` can be const. Alternatively, why not combine the two bytes as in `it_get_version()`? static u16 ite_get_chip_id(unsigned int port) { return (pnp_read_index(port, ITE_CHIPID1) << 8) | pnp_read_index(port, ITE_CHIPID2); } I've used the `unsigned int` type for the `port` parameter because it's the type of `dev->path.pnp.port` (c.f. `struct pnp_path` in `src/include/device/path.h`), even though `pnp_read_index()` expects an `u16`. In any case, this would be used as follows: const u16 chip_id = ite_get_chip_id(dev->path.pnp.port); if (chip_id != ITE_CHIPID_VAL) { printk(BIOS_ERR, "ITE: Device not found.\n"); return; } The chip ID defines would need to be adapted as follows: #define ITE_CHIPID_VAL 0x8987 I'd also remove the preceding comments (several of which are wrong, I commented about it). I'm pretty sure you can see that this ID corresponds to the ITE IT8987 😜 https://review.coreboot.org/c/coreboot/+/58343/comment/f513a716_d0f90b95 PS42, Line 50: printk(BIOS_ERR, "ITE: Device not found.\n"); Idea: print the expected and actual IDs? printk(BIOS_ERR, "ITE: Expected chip ID 0x%04x, but got 0x%04x instead.\n", ITE_CHIPID_VAL, chip_id); https://review.coreboot.org/c/coreboot/+/58343/comment/6c4fcf7e_6ff57bc4 PS42, Line 54: printk(BIOS_DEBUG, "ITE: Initializing keyboard.\n"); Strictly speaking, coreboot only does keyboard init if `DRIVERS_PS2_KEYBOARD` is set, which is only needed when the payload doesn't do keyboard init. To avoid potential confusion, I'd remove this log message. `pc_keyboard_init()` already prints stuff when doing keyboard init. File src/ec/starlabs/merlin/variants/apl/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/7594e63c_4cea90b3 PS42, Line 13: IT5570 Looks like IT8987 File src/ec/starlabs/merlin/variants/apl/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/c862f081_badbc145 PS42, Line 3: 0xFF This makes the OperationRegion 0xff = 255 bytes long. Shouldn't it be 256? https://review.coreboot.org/c/coreboot/+/58343/comment/573f137a_26869e45 PS42, Line 172: // TODO: : // Causes build failure, but 0xff is in range : // EJ8E, 8, // EJ898A Error See comment on OperationRegion declaration at the start of the file File src/ec/starlabs/merlin/variants/cml/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/315c3ef0_1dede964 PS42, Line 10: IT5570 Looks like IT8987 File src/ec/starlabs/merlin/variants/cml/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/581b1222_6cdb17e3 PS42, Line 3: 0xFF This makes the OperationRegion 0xff = 255 bytes long. Shouldn't it be 256? File src/ec/starlabs/merlin/variants/glk/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/3c835239_9e5091c5 PS42, Line 13: IT5570 Looks like IT8987 File src/ec/starlabs/merlin/variants/glk/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/0439802b_62b30ba2 PS42, Line 3: 0xFF This makes the OperationRegion 0xff = 255 bytes long. Shouldn't it be 256? https://review.coreboot.org/c/coreboot/+/58343/comment/cc2d2872_5550c621 PS42, Line 172: // TODO: : // Causes build failure, but 0xff is in range : // EJ8E, 8, // EJ898A Error See comment on OperationRegion declaration at the start of the file File src/ec/starlabs/merlin/variants/kbl/ecdefs.h: https://review.coreboot.org/c/coreboot/+/58343/comment/c79075a3_ed2034f7 PS42, Line 10: IT5570 Looks like IT8987 File src/ec/starlabs/merlin/variants/kbl/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/cfd954c5_76bd6fba PS42, Line 3: 0xFF This makes the OperationRegion 0xff = 255 bytes long. Shouldn't it be 256? https://review.coreboot.org/c/coreboot/+/58343/comment/c2ee76ee_7a4ac92a PS42, Line 159: // TODO: : // Causes build failure, but 0xff is in range : // EJ8E, 8, // EJ898A Error See comment on OperationRegion declaration at the start of the file File src/ec/starlabs/merlin/variants/merlin/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/ada869ae_4f3230c2 PS42, Line 3: 0xFF This makes the OperationRegion 0xff = 255 bytes long. Shouldn't it be 256? https://review.coreboot.org/c/coreboot/+/58343/comment/3d1566e1_0a42dd0c PS42, Line 160: H nit: lowercase `h` File src/ec/starlabs/merlin/variants/tgl/emem.asl: https://review.coreboot.org/c/coreboot/+/58343/comment/2e3a8ffe_a6d47f64 PS42, Line 3: 0xFF This makes the OperationRegion 0xff = 255 bytes long. Shouldn't it be 256? https://review.coreboot.org/c/coreboot/+/58343/comment/6d63438f_0a5e06ff PS42, Line 167: H nit: lowercase `h` -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 43 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 17 Nov 2021 10:22:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Add helper functions to look up size and type of a file
by Lean Sheng Tan (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Julius Werner. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59312 ) Change subject: cbfs: Add helper functions to look up size and type of a file ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba Gerrit-Change-Number: 59312 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 17 Nov 2021 10:20:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [NOTWORKING]mb/prodrive/hermes: WOL i211 driver??
by Arthur Heymans (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59389 to review the following change. Change subject: [NOTWORKING]mb/prodrive/hermes: WOL i211 driver?? ...................................................................... [NOTWORKING]mb/prodrive/hermes: WOL i211 driver?? Does not work... Change-Id: Ia984020b969bfc5e59cfc74730cc34ccd63f3e00 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/net/Kconfig M src/drivers/net/Makefile.inc A src/drivers/net/i211.c A src/drivers/net/i211.h M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/prodrive/hermes/mainboard.c 6 files changed, 78 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59389/1 diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig index 7e111f6..c6abf80 100644 --- a/src/drivers/net/Kconfig +++ b/src/drivers/net/Kconfig @@ -53,3 +53,8 @@ It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a hexadecimal number for it to be valid. Failing to do so will result in the default MAC address being used. + +config INTEL_I211_WOL + bool + help + Select this to be able to configure the WOL state of the NIC. diff --git a/src/drivers/net/Makefile.inc b/src/drivers/net/Makefile.inc index 33c8211..6a1bde9 100644 --- a/src/drivers/net/Makefile.inc +++ b/src/drivers/net/Makefile.inc @@ -22,3 +22,5 @@ atl1e-macaddress-file := $(obj)/atl1e-macaddress atl1e-macaddress-type := raw endif + +ramstage-$(CONFIG_INTEL_I211_WOL) += i211.c diff --git a/src/drivers/net/i211.c b/src/drivers/net/i211.c new file mode 100644 index 0000000..8fcdecb --- /dev/null +++ b/src/drivers/net/i211.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmio.h> +#include <console/console.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci.h> + +#include "commonlib/loglevel.h" +#include "i211.h" + +#define E1000_WUC 0x05800 /* Wakeup Control - RW */ +#define E1000_WUC_APME 0x00000001 /* APM Enable */ +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ +#define E1000_WUFC 0x05808 + +static void i211_init(struct device *dev) +{ + /* Get the resource of the NIC mmio */ + struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); + + if (nic_res == NULL) { + printk(BIOS_ERR, "i211: resource not found\n"); + return; + } + + void *wuc = res2mmio(nic_res, E1000_WUC, 0); + void *wufc = res2mmio(nic_res, E1000_WUFC, 0); + printk(BIOS_DEBUG, "i211: WUC 0x%x, WUFC 0x%x\n", read32(wuc), read32(wufc)); + if (i211_disable_wol()) + clrbits32(wuc, E1000_WUC_APME | E1000_WUC_PME_EN | E1000_WUC_APMPME); + else + setbits32(wuc, E1000_WUC_APME | E1000_WUC_PME_EN | E1000_WUC_APMPME); + printk(BIOS_DEBUG, "i211: WUC 0x%x, WUFC 0x%x\n", read32(wuc), read32(wufc)); +} + +static struct device_operations i211_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = i211_init, +}; + +static const struct pci_driver i211_driver __pci_driver = { + .ops = &i211_ops, + .vendor = 0x8086, + .device = 0x1539, +}; diff --git a/src/drivers/net/i211.h b/src/drivers/net/i211.h new file mode 100644 index 0000000..c8070d3 --- /dev/null +++ b/src/drivers/net/i211.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +#ifndef __DRIVERS_INTEL_I211_H__ +#define __DRIVERS_INTEL_I211_H__ + +bool i211_disable_wol(void); + +#endif diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index 2fecc06..acd2c58 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -16,6 +16,7 @@ select ONBOARD_VGA_IS_PRIMARY select HAVE_ACPI_RESUME if !HERMES_USES_SPS_FIRMWARE select DISABLE_ACPI_HIBERNATE if HERMES_USES_SPS_FIRMWARE + select INTEL_I211_WOL if BOARD_PRODRIVE_HERMES_BASEBOARD diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index addd110..73d8643 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -8,6 +8,7 @@ #include <bootstate.h> #include <device/device.h> #include <device/dram/spd.h> +#include <drivers/net/i211.h> #include <intelblocks/pmclib.h> #include <types.h> #include <smbios.h> @@ -179,11 +180,14 @@ acpigen_write_method("\\_SB.MPTS", 1); { - if (board_cfg->wol == 0) { - acpigen_write_if_lequal_op_int(ARG0_OP, 3); + if (board_cfg->wol == 0 || 1) { + acpigen_write_if(); + acpigen_emit_byte(LLESS_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(6); { /* Disable the NIC so WOL is also disabled. */ - acpigen_soc_set_tx_gpio(GPD11); + acpigen_soc_clear_tx_gpio(GPD11); } acpigen_pop_len(); } @@ -198,6 +202,11 @@ } #endif +bool i211_disable_wol(void) +{ + return true; +} + static void mainboard_enable(struct device *dev) { /* FIXME: Do runtime configuration once the board is production ready */ -- To view, visit https://review.coreboot.org/c/coreboot/+/59389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia984020b969bfc5e59cfc74730cc34ccd63f3e00 Gerrit-Change-Number: 59389 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/sconfig: Expose apic devices
by build bot (Jenkins) (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Martin Roth, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59313 ) Change subject: util/sconfig: Expose apic devices ...................................................................... Patch Set 2: (3 comments) File util/sconfig/main.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133608): https://review.coreboot.org/c/coreboot/+/59313/comment/95fb6049_9c0a6a4d PS2, Line 1371: fprintf(head, "extern DEVTREE_CONST void *const __apic_%04x_%d_config;\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133608): https://review.coreboot.org/c/coreboot/+/59313/comment/5f70aa04_f2343a4c PS2, Line 1373: fprintf(fil, "DEVTREE_CONST void *const __apic_%04x_%d_config = &%s_info_%d;\n", line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133608): https://review.coreboot.org/c/coreboot/+/59313/comment/ca894b07_02b4d555 PS2, Line 1374: ptr->path_a, ptr->path_b, chip_ins->chip->name_underscore, chip_ins->id); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 17 Nov 2021 10:01:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Add standardised ITE EC support
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Andy Pont, Paul Menzel, Angel Pons, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58343 to look at the new patch set (#43). Change subject: ec/starlabs: Add standardised ITE EC support ...................................................................... ec/starlabs: Add standardised ITE EC support Add EC support that supports different Q Events and EC memory. Created from the ITE IT5570E and IT8987E datasheets, all using data port 0x4e. Tested with Ubuntu 20.04.3 and Windows 10 on: * StarBook Mk V (TGL + IT5570E): * ITE Firmware 1.00 * Merlin Firmware 1.00 * LabTop Mk IV (CML + IT8987E): * ITE Firmware 1.04 * LabTop Mk III (KBL + IT8987E): * ITE Firmware 3.12 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 --- A src/ec/starlabs/merlin/Kconfig A src/ec/starlabs/merlin/Makefile.inc A src/ec/starlabs/merlin/acpi/ac.asl A src/ec/starlabs/merlin/acpi/battery.asl A src/ec/starlabs/merlin/acpi/cmos.asl A src/ec/starlabs/merlin/acpi/ec.asl A src/ec/starlabs/merlin/acpi/hid.asl A src/ec/starlabs/merlin/acpi/keyboard.asl A src/ec/starlabs/merlin/acpi/lid.asl A src/ec/starlabs/merlin/acpi/suspend.asl A src/ec/starlabs/merlin/ec.c A src/ec/starlabs/merlin/ec.h A src/ec/starlabs/merlin/variants/apl/ecdefs.h A src/ec/starlabs/merlin/variants/apl/emem.asl A src/ec/starlabs/merlin/variants/apl/events.asl A src/ec/starlabs/merlin/variants/cml/ecdefs.h A src/ec/starlabs/merlin/variants/cml/emem.asl A src/ec/starlabs/merlin/variants/cml/events.asl A src/ec/starlabs/merlin/variants/glk/ecdefs.h A src/ec/starlabs/merlin/variants/glk/emem.asl A src/ec/starlabs/merlin/variants/glk/events.asl A src/ec/starlabs/merlin/variants/kbl/ecdefs.h A src/ec/starlabs/merlin/variants/kbl/emem.asl A src/ec/starlabs/merlin/variants/kbl/events.asl A src/ec/starlabs/merlin/variants/merlin/ecdefs.h A src/ec/starlabs/merlin/variants/merlin/emem.asl A src/ec/starlabs/merlin/variants/merlin/events.asl A src/ec/starlabs/merlin/variants/tgl/ecdefs.h A src/ec/starlabs/merlin/variants/tgl/emem.asl A src/ec/starlabs/merlin/variants/tgl/events.asl 30 files changed, 3,537 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/58343/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/58343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32 Gerrit-Change-Number: 58343 Gerrit-PatchSet: 43 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/starlabs: Add USB Type-C Mailbox interface
by Sean Rhodes (Code Review) 17 Nov '21

17 Nov '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59388 ) Change subject: ec/starlabs: Add USB Type-C Mailbox interface ...................................................................... ec/starlabs: Add USB Type-C Mailbox interface Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I77c9a0afec4ad3ad54a0a67d7ab68b7cabca2db6 --- M src/ec/starlabs/merlin/acpi/ec.asl A src/ec/starlabs/merlin/acpi/typec.asl A src/ec/starlabs/merlin/acpi/ubtc.asl 3 files changed, 135 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/59388/1 diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl index 8458818..93b3470 100644 --- a/src/ec/starlabs/merlin/acpi/ec.asl +++ b/src/ec/starlabs/merlin/acpi/ec.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "ubtc.asl" + Scope (\_SB.PCI0.LPCB) { #include "cmos.asl" @@ -169,6 +171,7 @@ #include "battery.asl" #include "events.asl" #include "lid.asl" + #include "typec.asl" Method (_REG, 2, NotSerialized) { diff --git a/src/ec/starlabs/merlin/acpi/typec.asl b/src/ec/starlabs/merlin/acpi/typec.asl new file mode 100644 index 0000000..1acc8a4 --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/typec.asl @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (UCSW, 0, Serialized) +{ + Sleep (50) + MGO0 = ^^^^UBTC.MGO0 + MGO1 = ^^^^UBTC.MGO1 + MGO2 = ^^^^UBTC.MGO2 + MGO3 = ^^^^UBTC.MGO3 + MGO4 = ^^^^UBTC.MGO4 + MGO5 = ^^^^UBTC.MGO5 + MGO6 = ^^^^UBTC.MGO6 + MGO7 = ^^^^UBTC.MGO7 + MGO8 = ^^^^UBTC.MGO7 + MGO9 = ^^^^UBTC.MGO9 + MGOA = ^^^^UBTC.MGOA + MGOB = ^^^^UBTC.MGOB + MGOC = ^^^^UBTC.MGOC + MGOD = ^^^^UBTC.MGOD + MGOE = ^^^^UBTC.MGOE + MGOF = ^^^^UBTC.MGOF + CTL0 = ^^^^UBTC.CTL0 + CTL1 = ^^^^UBTC.CTL1 + CTL2 = ^^^^UBTC.CTL2 + CTL3 = ^^^^UBTC.CTL3 + CTL4 = ^^^^UBTC.CTL4 + CTL5 = ^^^^UBTC.CTL5 + CTL6 = ^^^^UBTC.CTL6 + CTL7 = ^^^^UBTC.CTL7 + OPWE = 0xE0 +} + +Method (UCSR, 0, Serialized) +{ + Sleep (50) + ^^^^UBTC.MGI0 = MGI0 + ^^^^UBTC.MGI1 = MGI1 + ^^^^UBTC.MGI2 = MGI2 + ^^^^UBTC.MGI3 = MGI3 + ^^^^UBTC.MGI4 = MGI4 + ^^^^UBTC.MGI5 = MGI5 + ^^^^UBTC.MGI6 = MGI6 + ^^^^UBTC.MGI7 = MGI7 + ^^^^UBTC.MGI8 = MGI8 + ^^^^UBTC.MGI9 = MGI9 + ^^^^UBTC.MGIA = MGIA + ^^^^UBTC.MGIB = MGIB + ^^^^UBTC.MGIC = MGIC + ^^^^UBTC.MGID = MGID + ^^^^UBTC.MGIE = MGIE + ^^^^UBTC.MGIF = MGIF + ^^^^UBTC.CCI0 = CCI0 + ^^^^UBTC.CCI1 = CCI1 + ^^^^UBTC.CCI2 = CCI2 + ^^^^UBTC.CCI3 = CCI3 +} + +Method (UCEV, 0, Serialized) +{ + Sleep (50) + ^^^^UBTC.MGI0 = MGI0 + ^^^^UBTC.MGI1 = MGI1 + ^^^^UBTC.MGI2 = MGI2 + ^^^^UBTC.MGI3 = MGI3 + ^^^^UBTC.MGI4 = MGI4 + ^^^^UBTC.MGI5 = MGI5 + ^^^^UBTC.MGI6 = MGI6 + ^^^^UBTC.MGI7 = MGI7 + ^^^^UBTC.MGI8 = MGI8 + ^^^^UBTC.MGI9 = MGI9 + ^^^^UBTC.MGIA = MGIA + ^^^^UBTC.MGIB = MGIB + ^^^^UBTC.MGIC = MGIC + ^^^^UBTC.MGID = MGID + ^^^^UBTC.MGIE = MGIE + ^^^^UBTC.MGIF = MGIF + ^^^^UBTC.CCI0 = CCI0 + ^^^^UBTC.CCI1 = CCI1 + ^^^^UBTC.CCI2 = CCI2 + ^^^^UBTC.CCI3 = CCI3 + Notify (^^^^UBTC, 0x80) +} diff --git a/src/ec/starlabs/merlin/acpi/ubtc.asl b/src/ec/starlabs/merlin/acpi/ubtc.asl new file mode 100644 index 0000000..f29fb9d --- /dev/null +++ b/src/ec/starlabs/merlin/acpi/ubtc.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External(\_SB.UBTC, DeviceObj) +External(\_SB.UBTC.MGI0, IntObj) +External(\_SB.UBTC.MGI1, IntObj) +External(\_SB.UBTC.MGI2, IntObj) +External(\_SB.UBTC.MGI3, IntObj) +External(\_SB.UBTC.MGI4, IntObj) +External(\_SB.UBTC.MGI5, IntObj) +External(\_SB.UBTC.MGI6, IntObj) +External(\_SB.UBTC.MGI7, IntObj) +External(\_SB.UBTC.MGI8, IntObj) +External(\_SB.UBTC.MGI9, IntObj) +External(\_SB.UBTC.MGIA, IntObj) +External(\_SB.UBTC.MGIB, IntObj) +External(\_SB.UBTC.MGIC, IntObj) +External(\_SB.UBTC.MGID, IntObj) +External(\_SB.UBTC.MGIE, IntObj) +External(\_SB.UBTC.MGIF, IntObj) + +External(\_SB.UBTC.CTL0, IntObj) +External(\_SB.UBTC.CTL1, IntObj) +External(\_SB.UBTC.CTL2, IntObj) +External(\_SB.UBTC.CTL3, IntObj) +External(\_SB.UBTC.CTL4, IntObj) +External(\_SB.UBTC.CTL5, IntObj) +External(\_SB.UBTC.CTL6, IntObj) +External(\_SB.UBTC.CTL7, IntObj) + +External(\_SB.UBTC.MGO0, IntObj) +External(\_SB.UBTC.MGO1, IntObj) +External(\_SB.UBTC.MGO2, IntObj) +External(\_SB.UBTC.MGO3, IntObj) +External(\_SB.UBTC.MGO4, IntObj) +External(\_SB.UBTC.MGO5, IntObj) +External(\_SB.UBTC.MGO6, IntObj) +External(\_SB.UBTC.MGO7, IntObj) +External(\_SB.UBTC.MGO8, IntObj) +External(\_SB.UBTC.MGO9, IntObj) +External(\_SB.UBTC.MGOA, IntObj) +External(\_SB.UBTC.MGOB, IntObj) +External(\_SB.UBTC.MGOC, IntObj) +External(\_SB.UBTC.MGOD, IntObj) +External(\_SB.UBTC.MGOE, IntObj) +External(\_SB.UBTC.MGOF, IntObj) + +External(\_SB.UBTC.CCI0, IntObj) +External(\_SB.UBTC.CCI1, IntObj) +External(\_SB.UBTC.CCI2, IntObj) +External(\_SB.UBTC.CCI3, IntObj) -- To view, visit https://review.coreboot.org/c/coreboot/+/59388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77c9a0afec4ad3ad54a0a67d7ab68b7cabca2db6 Gerrit-Change-Number: 59388 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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coreboot-gerrit November 2021