coreboot-gerrit November 2021

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Change in coreboot[master]: soc/amd/picasso: Add bootloader for recovery
by Bao Zheng (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57132 to look at the new patch set (#43). Change subject: soc/amd/picasso: Add bootloader for recovery ...................................................................... soc/amd/picasso: Add bootloader for recovery PspRecoveryBootLoader_prod_RV.sbin is bootloader for AMD's recovery mode. It is amdfwtool which decides whether regular bootloader or recovery loader is loaded. Change-Id: Ib13f2c79cc6021694cb30a35f104b18ed8b2493b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/fw.cfg M util/amdfwtool/amdfwtool.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/57132/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/57132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib13f2c79cc6021694cb30a35f104b18ed8b2493b Gerrit-Change-Number: 57132 Gerrit-PatchSet: 43 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by Bao Zheng (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57131 to look at the new patch set (#42). Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... amdfwtool: Add support for AMD's BIOS recovery feature The BIOS recovery feature helps recover the computer from a Power On Self-Test (POST) or a boot failure that is caused by a corrupt BIOS. The system in BIOS recovery mode goes a different route, uses different FWs and different AMD FW layout. So the amdfwtool needs to change. Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 41 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/57131/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 42 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg
by Bao Zheng (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56937 to look at the new patch set (#43). Change subject: soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg ...................................................................... soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfg TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B recovery. Both bootloader can be put in the fw.cfg. The amdfwtool decides which booloader is dropped in the directory. Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/fw.cfg 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/56937/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/56937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e Gerrit-Change-Number: 56937 Gerrit-PatchSet: 43 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Add ISH header support for A/B recovery layout
by Bao Zheng (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57747 to look at the new patch set (#33). Change subject: amdfwtool: Add ISH header support for A/B recovery layout ...................................................................... amdfwtool: Add ISH header support for A/B recovery layout ISH is newly for Mendocino. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 4 files changed, 77 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/57747/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/57747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Gerrit-Change-Number: 57747 Gerrit-PatchSet: 33 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amdfwtool: Add ISH header support for A/B recovery layout
by Bao Zheng (Code Review) 17 Nov '21

17 Nov '21

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59384 ) Change subject: amdfwtool: Add ISH header support for A/B recovery layout ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/59384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4710df4098c08007d9aa8f009595fdbf594a7b7b Gerrit-Change-Number: 59384 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: abandon

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Change in coreboot[master]: amdfwtool: Add support for AMD's BIOS recovery feature
by build bot (Jenkins) (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Bao Zheng, Martin Roth, Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57131 ) Change subject: amdfwtool: Add support for AMD's BIOS recovery feature ...................................................................... Patch Set 41: (1 comment) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133586): https://review.coreboot.org/c/coreboot/+/57131/comment/a261b79f_bb34ce31 PS41, Line 1892: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/57131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2671b95fe089aafdaf61b55bc9d2e8dcf6a66dbc Gerrit-Change-Number: 57131 Gerrit-PatchSet: 41 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 17 Nov 2021 08:20:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct USB3 TCSS setting
by EricR Lai (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59385 to look at the new patch set (#3). Change subject: mb/google/brya/var/felwinter: Correct USB3 TCSS setting ...................................................................... mb/google/brya/var/felwinter: Correct USB3 TCSS setting Based on Intel Kit#615686, USB3 only needs to disable TBT and DAM per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59385/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Gerrit-Change-Number: 59385 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct USB3 TSCC setting
by EricR Lai (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59385 to look at the new patch set (#2). Change subject: mb/google/brya/var/felwinter: Correct USB3 TSCC setting ...................................................................... mb/google/brya/var/felwinter: Correct USB3 TSCC setting Based on Intel Kit#615686, USB3 only needs to disable TBT and DAM per port. And if uses USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59385/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Gerrit-Change-Number: 59385 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/felwinter: Correct USB3 TSCC setting
by EricR Lai (Code Review) 17 Nov '21

17 Nov '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59385 ) Change subject: mb/google/brya/var/felwinter: Correct USB3 TSCC setting ...................................................................... mb/google/brya/var/felwinter: Correct USB3 TSCC setting Based on Intel Kit#615686, USB3 only need to disable TBT and DAM pre port. And if USB3 directly you need to set TcssAuxOri accordingly. BUG=b:206716691,b:205235144 TEST=USB function work as expected at USB3 only sku. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59385/1 diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 5b90b9a..b1980f6 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -38,6 +38,12 @@ device domain 0 on device ref dtt on end device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 on + probe DB_USB USB4_KB8001 + end + device ref tbt_pcie_rp2 on + probe DB_USB USB4_KB8001 + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -45,6 +51,7 @@ end end device ref tcss_dma0 on + probe DB_USB USB4_KB8001 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" use tcss_usb3_port2 as dfp[0].typec_port @@ -52,12 +59,11 @@ end end device ref tcss_dma1 on + probe DB_USB USB4_KB8001 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" use tcss_usb3_port3 as dfp[0].typec_port - device generic 0 on - probe DB_USB USB4_KB8001 - end + device generic 0 on end end end device ref pcie_rp6 off end diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c index 9234019..ee39ef0 100644 --- a/src/mainboard/google/brya/variants/felwinter/variant.c +++ b/src/mainboard/google/brya/variants/felwinter/variant.c @@ -9,5 +9,6 @@ if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PS8815))) { config->typec_aux_bias_pads[2].pad_auxp_dc = GPP_A19; config->typec_aux_bias_pads[2].pad_auxn_dc = GPP_A20; + config->TcssAuxOri = 0x10; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/59385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8 Gerrit-Change-Number: 59385 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Add ISH header support for A/B recovery layout
by Bao Zheng (Code Review) 17 Nov '21

17 Nov '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/59384 to review the following change. Change subject: amdfwtool: Add ISH header support for A/B recovery layout ...................................................................... amdfwtool: Add ISH header support for A/B recovery layout ISH is newly for Mendocino. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> amdfwtool: ish Change-Id: I4710df4098c08007d9aa8f009595fdbf594a7b7b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 4 files changed, 77 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/59384/1 diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 1805459..7b77935 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -5,7 +5,7 @@ SRC = amdfwtool.c data_parse.c OBJ = $(SRC:%.c=%.o) TARGET = amdfwtool -WERROR=-Werror -Wno-unused-function +WERROR=-Werror CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} all: $(TARGET) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index f772299..4b7db76 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -2,7 +2,7 @@ amdfwtoolobj = amdfwtool.o data_parse.o -AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror -Wno-unused-function +AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror $(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index dede243..490c613 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -407,6 +407,15 @@ return ptr; } +static void *new_ish_dir(context *ctx) +{ + void *ptr; + ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); + ptr = BUFF_CURRENT(*ctx); + ctx->current += TABLE_ALIGNMENT; + return ptr; +} + #if PSP_COMBO static void *new_combo_dir(context *ctx) { @@ -657,7 +666,8 @@ } static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, - psp_directory_table *pspdir2, amd_fw_type ab) + psp_directory_table *pspdir2, ish_directory_table *ish, + amd_fw_type ab, enum platform soc_id) { uint32_t count; uint32_t current_table_save; @@ -666,14 +676,44 @@ ctx->current_table = 0; count = pspdir->header.num_entries; assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); + if (ish != NULL) { + switch (ab) { + case AMD_FW_RECOVERYAB_A: + ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, 1); + ish->boot_priority = 0xFFFFFFFF; + ish->update_retry_count = 0xf; + ish->glitch_retry_count = 0; + ish->psp_id = get_psp_id(soc_id); + ish->checksum = fletcher32(&ish->boot_priority, + sizeof(ish_directory_table) - sizeof(uint32_t)); + break; + case AMD_FW_RECOVERYAB_B: + ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, 1); + ish->boot_priority = 0x2; + ish->update_retry_count = 0xf; + ish->glitch_retry_count = 0; + ish->psp_id = get_psp_id(soc_id); + ish->checksum = fletcher32(&ish->boot_priority, + sizeof(ish_directory_table) - sizeof(uint32_t)); + break; + default: + break; + } + } pspdir->entries[count].type = (uint8_t)ab; pspdir->entries[count].subprog = 0; pspdir->entries[count].rsvd = 0; - pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, pspdir2, 1); - pspdir->entries[count].address_mode = SET_ADDR_MODE(1, pspdir); - pspdir->entries[count].size = pspdir2->header.num_entries * + if (ish != NULL) { + pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, ish, 1); + pspdir->entries[count].address_mode = SET_ADDR_MODE(1, pspdir); + pspdir->entries[count].size = TABLE_ALIGNMENT; + } else { + pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, pspdir2, 1); + pspdir->entries[count].address_mode = SET_ADDR_MODE(1, pspdir); + pspdir->entries[count].size = pspdir2->header.num_entries * sizeof(psp_directory_entry) + sizeof(psp_directory_header); + } count++; pspdir->header.num_entries = count; @@ -686,6 +726,7 @@ psp_directory_table *pspdir2_b, amd_fw_entry *fw_table, uint32_t cookie, + enum platform soc_id, amd_cb_config *cb_config) { ssize_t bytes; @@ -693,6 +734,7 @@ int level; uint32_t current_table_save; bool recovery_ab = cb_config->recovery_ab; + ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -798,10 +840,17 @@ } if (recovery_ab && (pspdir2 != NULL)) { + if (cb_config->need_ish) { /* Need ISH */ + ish_a_dir = new_ish_dir(ctx); + if (pspdir2_b != NULL) + ish_b_dir = new_ish_dir(ctx); + } pspdir->header.num_entries = count; - integrate_psp_ab(ctx, pspdir, pspdir2, AMD_FW_RECOVERYAB_A); + integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, + AMD_FW_RECOVERYAB_A, soc_id); if (pspdir2_b != NULL) - integrate_psp_ab(ctx, pspdir, pspdir2_b, AMD_FW_RECOVERYAB_B); + integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, + AMD_FW_RECOVERYAB_B, soc_id); count = pspdir->header.num_entries; } else if (pspdir2 != NULL) { assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); @@ -1430,6 +1479,7 @@ cb_config.s0i3 = false; cb_config.multi_level = false; cb_config.recovery_ab = false; + cb_config.need_ish = false; while (1) { int optindex = 0; @@ -1657,6 +1707,9 @@ retval = 1; } + if (soc_id == PLATFORM_MENDOCINO && cb_config.recovery_ab) + cb_config.need_ish = true; + if (retval) { usage(); return retval; @@ -1744,25 +1797,25 @@ /* Do 2nd PSP directory followed by 1st */ pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); if (cb_config.recovery_ab) { /* B is same as above directories for A */ /* Skip creating pspdir2_b here to save flash space. Related * biosdir2_b will be skipped automatically. */ pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); } else { pspdir2_b = NULL; /* More explicitly */ } pspdir = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b, - amd_psp_fw_table, PSP_COOKIE, &cb_config); + amd_psp_fw_table, PSP_COOKIE, soc_id, &cb_config); } else { /* flat: PSP 1 cookie and no pointer to 2nd table */ pspdir = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir, NULL, NULL, - amd_psp_fw_table, PSP_COOKIE, &cb_config); + amd_psp_fw_table, PSP_COOKIE, soc_id, &cb_config); } if (comboable) diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index cc270a4..face3bf 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -228,6 +228,17 @@ int level; } amd_bios_entry; +typedef struct _ish_directory_table { + uint32_t checksum; + uint32_t boot_priority; + uint32_t update_retry_count; + uint8_t glitch_retry_count; + uint8_t glitch_higherbits_reserved[3]; + uint32_t pl2_location; + uint32_t psp_id; + uint32_t slot_max_size; + uint32_t reserved; +} __attribute__((packed)) ish_directory_table; #define EMBEDDED_FW_SIGNATURE 0x55aa55aa #define PSP_COOKIE 0x50535024 /* 'PSP$' */ #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ @@ -257,6 +268,7 @@ bool multi_level; bool s0i3; bool recovery_ab; + bool need_ish; } amd_cb_config; void register_fw_fuse(char *str); -- To view, visit https://review.coreboot.org/c/coreboot/+/59384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4710df4098c08007d9aa8f009595fdbf594a7b7b Gerrit-Change-Number: 59384 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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coreboot-gerrit November 2021