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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 )
Change subject: soc/intel/common: Implements ACPI CPPCv3 package to support hybrid core
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/acpi/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/59359/comment/c43915ca_7a79989c
PS1, Line 28: SFBC, 16, // 0x48 - 0x49 Indicates Scaling factor for Big core
: SFSC, 16, // 0x50 - 0x51 Indicates Scaling Factor for Small Core
: NMFQ, 16, // 0x52 - 0x53 Indicates Nominal Frequency
: CORE, 32, // 0x54 - 0x57 Each marked bit indicates Big Core corresponding to core index
: INFS, 8, // 0x58 - Nominal Frequency is supported
:
where are these used? do these values have to be in gnvs in contrast to generating and adding them to DSDT?
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Change subject: sc7280/ boot and shrm blobs updated
......................................................................
Patch Set 1: Code-Review+2
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Change subject: amdfwtool: Check duplicated entry
......................................................................
Patch Set 1:
(5 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133575):
https://review.coreboot.org/c/coreboot/+/59381/comment/3478ac93_5f6a446e
PS1, Line 344: for (entry_i = table; entry_i->type != AMD_FW_INVALID; entry_i ++)
space prohibited before that '++' (ctx:WxB)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133575):
https://review.coreboot.org/c/coreboot/+/59381/comment/f3c5a2d5_fea78f95
PS1, Line 345: for (entry_j = entry_i + 1; entry_j->type != AMD_FW_INVALID; entry_j ++)
space prohibited before that '++' (ctx:WxB)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133575):
https://review.coreboot.org/c/coreboot/+/59381/comment/dcf61879_f14a7df6
PS1, Line 359: for (entry_i = table; entry_i->type != AMD_BIOS_INVALID; entry_i ++)
space prohibited before that '++' (ctx:WxB)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133575):
https://review.coreboot.org/c/coreboot/+/59381/comment/758f80f6_e193e360
PS1, Line 360: for (entry_j = entry_i + 1; entry_j->type != AMD_BIOS_INVALID; entry_j ++)
space prohibited before that '++' (ctx:WxB)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133575):
https://review.coreboot.org/c/coreboot/+/59381/comment/4d4506bd_df81a373
PS1, Line 364: fprintf(stderr, "duplicated entries:type=%x, inst=%x, subprog=%x\n",
line over 96 characters
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Change subject: ChromeOS: Add legacy mainboard_ec_running_ro()
......................................................................
Patch Set 7:
(1 comment)
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/58896/comment/0b9ccb31_2d7f0e2c
PS7, Line 67: }
> get_ec_trusted() is about a pin that doesn't always reflect the actual state (it's a latch that's in […]
I am asking the same question in pathcset #5, I don't know what should be done with this ACPI table data on S3 resume path.
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Change subject: soc/intel/denverton_ns: Add early SPI flash init
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57033/comment/9b5b4ca6_868635a2
PS4, Line 18: (Taken over on author request)
No fix has been merged.
The SPI master just needs WPD set, so fast_spi_disable_wp() call at a carefully selected location is the correct fix.
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 40:
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133573):
https://review.coreboot.org/c/coreboot/+/57131/comment/a27f8600_093fd2b2
PS40, Line 1892: btl_entry = search_entry(pspdir2, AMD_FW_PSP_BOOTLOADER);
line over 96 characters
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Kangheui Won, Paul Menzel, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59308
to look at the new patch set (#7).
Change subject: amdfwtool: Upgrade "relative address" to four address modes
......................................................................
amdfwtool: Upgrade "relative address" to four address modes
Address Mode 0: Physical Address, bit 63~56: 0x00
Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40
Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80
Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0
It is the expanding mode for simple relative address mode, for which
address_mode equals 1.
Only mode 2 is added. We need to record current table base address and
calculate the offset. The ctx.current_table is zero outside the
table. When it goes into the function to integrate the table, it
should backup the old value and get current table base. Before it goes
out the function, it should restore the value.
If the table address mode is 2, the address in each entry should be
also add address mode information. If not, the address mode in entry
is meanless.
The old mode 0,1 should be back compatible.
Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 84 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59308/7
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