coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Jeremy Soller, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59489 ) Change subject: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11266e93d1d11695edf21b6cd60e5d8add1fde8 Gerrit-Change-Number: 59489 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 16:39:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/haswell/*.c: Use static.c exposed lapic 0
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Tristan Corrick, Angel Pons, Alexander Couzens, Patrick Rudolph. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/haswell/*.c: Use static.c exposed lapic 0 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/mainboard/google/auron/devicetree.cb: https://review.coreboot.org/c/coreboot/+/59314/comment/391aa047_24e47381 PS2, Line 20: device lapic 0xacac off end Going back to my original question. Why do we need the lapic to hold the config? Right now it looks like the structure is: ``` chip soc/intel/broadwell device cpu_cluster 0 on chip cpu/intel/haswell register "s0ix_enable" = "1" device lapic 0 on end end end end ``` The problem was that we can't have 2 chips apply to the same device. We don't need to have the cpu_cluster nested under the soc chip do we? Does the following work? ``` chip cpu/intel/haswell register "s0ix_enable" = "1" device cpu_cluster 0 on device lapic 0 on end <- I think you could optionally get rid of this now end end chip soc/intel/broadwell ... device domain 0 on .... end ... end ``` I'm not going to block this CL or anything, just throwing out ideas. -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 16:35:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/sconfig: Expose apic devices
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Nico Huber, Furquan Shaikh, Martin Roth, Tim Wawrzynczak. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59313 ) Change subject: util/sconfig: Expose apic devices ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/59313/comment/93486f32_1d9d1c62 PS1, Line 391: B:D:F = 0:00:0 This needs updating. -- To view, visit https://review.coreboot.org/c/coreboot/+/59313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I800f089998f4a9be2216ed997cec5cedeb63f3db Gerrit-Change-Number: 59313 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 16:24:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib/hardwaremain: Run timers more frequently
by Raul Rangel (Code Review) 19 Nov '21

19 Nov '21

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58955 ) Change subject: lib/hardwaremain: Run timers more frequently ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58955/comment/a7e3466f_9c108754 PS2, Line 14: see SPI transactions progress faster > Basically, `bs_run_timers(0)` calls `timers_run()` once, which checks if the timer queue's first ele […] Yep exactly. That's why I said progress faster. The current SPI DMA transactions complete before the data is required, so it doesn't actually affect boot time. What this does allow though is more opportunities to enqueue more transactions in the same time, so it's possible to add more preloads. -- To view, visit https://review.coreboot.org/c/coreboot/+/58955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8 Gerrit-Change-Number: 58955 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 16:22:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add some notes about how to integrate FSP
by Felix Singer (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Add some notes about how to integrate FSP ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File Documentation/soc/intel/fsp/index.md: https://review.coreboot.org/c/coreboot/+/58886/comment/3b7f8034_40dcf6a7 PS2, Line 8: that affects : way FSP works I feel like that doesn't sound right. Dropped the "the" by mistake? -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 15:45:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree
by Felix Singer (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Jeremy Soller, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59489 ) Change subject: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59489/comment/0e02d77c_58ee2cc7 PS1, Line 7: Enable/Disable pci dev 4 based on devicetree How about: Hook up PCI dev 4 to the devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/59489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11266e93d1d11695edf21b6cd60e5d8add1fde8 Gerrit-Change-Number: 59489 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 15:37:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/chronicler: set DdrMemoryDown enable
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59373 ) Change subject: mb/google/volteer/var/chronicler: set DdrMemoryDown enable ...................................................................... mb/google/volteer/var/chronicler: set DdrMemoryDown enable as doc #632048, there is a fix in MRC for this sighting but DdrMemoryDown need to be set to 1. BUG=b:192478111 BRANCH=volteer TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59373 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/variants/chronicler/memory.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sheng-Liang Pan: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/chronicler/memory.c b/src/mainboard/google/volteer/variants/chronicler/memory.c index 8ec6996..8c67a2d 100644 --- a/src/mainboard/google/volteer/variants/chronicler/memory.c +++ b/src/mainboard/google/volteer/variants/chronicler/memory.c @@ -24,3 +24,9 @@ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } + +void memcfg_variant_init(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + mem_cfg->DdrMemoryDown = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/59373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Gerrit-Change-Number: 59373 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/chronicler: set DdrMemoryDown enable
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Nick Vaccaro, Derek Huang, Sheng-Liang Pan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59373 ) Change subject: mb/google/volteer/var/chronicler: set DdrMemoryDown enable ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > just want to double check that we have the correct MRC version Thanks for your patience, double-checked the version and we're good 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/59373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Gerrit-Change-Number: 59373 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 15:35:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/chronicler: set DdrMemoryDown enable
by Tim Wawrzynczak (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Nick Vaccaro, Derek Huang, Sheng-Liang Pan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59373 ) Change subject: mb/google/volteer/var/chronicler: set DdrMemoryDown enable ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4 Gerrit-Change-Number: 59373 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Derek Huang <derek.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 19 Nov 2021 15:34:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree
by Tim Crawford (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Arthur Heymans, Felix Singer, Jeremy Soller, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59489 ) Change subject: soc/intel/cannonlake: Enable/Disable pci dev 4 based on devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11266e93d1d11695edf21b6cd60e5d8add1fde8 Gerrit-Change-Number: 59489 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 15:26:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2021