coreboot-gerrit November 2021

coreboot-gerrit@coreboot.org

1 participants
6394 discussions

Change in coreboot[master]: util/inteltool/gpio.c: Correct register name
by Felix Singer (Code Review) 19 Nov '21

19 Nov '21

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59289 ) Change subject: util/inteltool/gpio.c: Correct register name ...................................................................... util/inteltool/gpio.c: Correct register name Document 319973-003 (ICH10 datasheet) and document 324645-006 (6-series PCH datasheet) indicate that the name of this register is `GP_LVL3`, not `GPIO_LVL3`. Correct the name. Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59289 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/inteltool/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Christian Walter: Looks good to me, approved diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 5808204..30b80d8 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -173,7 +173,7 @@ { 0x3C, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, - { 0x48, 4, "GPIO_LVL3" }, + { 0x48, 4, "GP_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, @@ -227,7 +227,7 @@ { 0x3c, 4, "RESERVED" }, { 0x40, 4, "GPIO_USE_SEL3" }, { 0x44, 4, "GP_IO_SEL3" }, - { 0x48, 4, "GPIO_LVL3" }, + { 0x48, 4, "GP_LVL3" }, { 0x4c, 4, "RESERVED" }, { 0x50, 4, "RESERVED" }, { 0x54, 4, "RESERVED" }, 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/59289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Gerrit-Change-Number: 59289 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: crossgcc: replace __builtin_trap in UB handling with _exit
by Patrick Georgi (Code Review) 19 Nov '21

19 Nov '21

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/14364 ) Change subject: crossgcc: replace __builtin_trap in UB handling with _exit ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/14364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib996e15045b8d2120a5825240bfb5dcfa3f89449 Gerrit-Change-Number: 14364 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEV...
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59260 ) Change subject: mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD ...................................................................... mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:199823938 TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED during boot. Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index dc1a424..e4119f6 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -276,6 +276,7 @@ register "num_freq_entries" = "1" register "link_freq[0]" = "DEFAULT_LINK_FREQ" register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "1" #Controls @@ -311,6 +312,7 @@ register "acpi_name" = ""CAM0"" register "chip_name" = ""Hi-556 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "ssdb.lanes_used" = "2" register "ssdb.link_used" = "1" @@ -351,8 +353,19 @@ register "acpi_name" = ""NVM0"" register "chip_name" = ""M24C64X"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" + register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" #EN_UCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/59260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea Gerrit-Change-Number: 59260 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arec <arec.kao(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: driver/intel/mipi_camera: Add support for _DSC field
by Felix Held (Code Review) 19 Nov '21

19 Nov '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58767 ) Change subject: driver/intel/mipi_camera: Add support for _DSC field ...................................................................... driver/intel/mipi_camera: Add support for _DSC field The _DSC (Device State for Configuration) object evaluates to an integer may be used to tell Linux the highest allowed D state for a device during probe. The support for _DSC requires support from the kernel bus type if the bus driver normally sets the device in D0 state for probe. The D states and thus also the allowed values for _DSC are listed below. Number State Description 0 D0 Device fully powered on 1 D1 2 D2 3 D3hot 4 D3cold Off More details can be found here https://lkml.org/lkml/2021/10/25/397 BUG=none BRANCH=none TEST=Add corresponding field in brya, boot and dump SSDT to check if _DSC field is as per expectation. Name (_ADR, Zero) // _ADR: Address Name (_HID, "OVTI8856") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_DSC, 0, NotSerialized) { Return (0x04) } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58767 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index ec79e39..a9af25c 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -847,6 +847,9 @@ acpigen_write_name_integer("_UID", config->acpi_uid); acpigen_write_name_string("_DDN", config->chip_name); acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_method("_DSC", 0); + acpigen_write_return_integer(config->max_dstate_for_probe); + acpigen_pop_len(); /* Method _DSC */ /* Resources */ acpigen_write_name("_CRS"); diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index c6ead1f..55e9f33f 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -257,6 +257,17 @@ bool has_power_resource; /* Perform low power probe */ bool low_power_probe; + /* + * This will create a _DSC method in ACPI which returns an integer, to tell the kernel + * the highest allowed D state for a device during probe + * Number State Description + * 0 D0 Device fully powered on + * 1 D1 + * 2 D2 + * 3 D3hot + * 4 D3cold Off + */ + uint8_t max_dstate_for_probe; }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/58767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Gerrit-Change-Number: 58767 Gerrit-PatchSet: 12 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/inteltool/gpio.c: Correct register name
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Nico Huber, Stefan Reinauer, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59289 ) Change subject: util/inteltool/gpio.c: Correct register name ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59289/comment/0c25cdc2_7d193018 PS1, Line 9: ICH10 and 6-series PCH datasheets > Please add the document numbers below. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Gerrit-Change-Number: 59289 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 14:50:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/inteltool/gpio.c: Correct register name
by Angel Pons (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Nico Huber, Stefan Reinauer, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Christian Walter, Stefan Reinauer, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59289 to look at the new patch set (#2). Change subject: util/inteltool/gpio.c: Correct register name ...................................................................... util/inteltool/gpio.c: Correct register name Document 319973-003 (ICH10 datasheet) and document 324645-006 (6-series PCH datasheet) indicate that the name of this register is `GP_LVL3`, not `GPIO_LVL3`. Correct the name. Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/59289/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Gerrit-Change-Number: 59289 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Documentation/lint: Use Super I/O instead of SuperIO
by Patrick Georgi (Code Review) 19 Nov '21

19 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39451 ) Change subject: Documentation/lint: Use Super I/O instead of SuperIO ...................................................................... Documentation/lint: Use Super I/O instead of SuperIO Change-Id: Idb16092b687ebffb319bc1908f08f350d612d36a Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/superio/nuvoton/nct5539d.md M util/lint/spelling.txt 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/39451/1 diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md index e91ebc3..009d329 100644 --- a/Documentation/superio/nuvoton/nct5539d.md +++ b/Documentation/superio/nuvoton/nct5539d.md @@ -1,9 +1,9 @@ -# NCT5539D SuperIO +# NCT5539D Super I/O -The SuperIO has the ID `0xd121` and the source can be found in +The Super I/O has the ID `0xd121` and the source can be found in `src/superio/nuvoton/nct5539d/`. ## For developers -The SuperIO generates ACPI using the +The Super I/O generates ACPI using the [SSDT generator for generic SuperIOs](../common/ssdt.md). diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 1263144..f74abf1 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -16,6 +16,7 @@ FTBS||FTBFS POSIX-complient||POSIX-compliant READEME||README +SuperIO||Super I/O aaccessibility||accessibility aaccession||accession abailable||available -- To view, visit https://review.coreboot.org/c/coreboot/+/39451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb16092b687ebffb319bc1908f08f350d612d36a Gerrit-Change-Number: 39451 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: util/kconfig: Add README.md documenting the uprev procedure
by Patrick Georgi (Code Review) 19 Nov '21

19 Nov '21

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57879 ) Change subject: util/kconfig: Add README.md documenting the uprev procedure ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/57879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db Gerrit-Change-Number: 57879 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: Documentation: Add some notes about how to integrate FSP
by Patrick Georgi (Code Review) 19 Nov '21

19 Nov '21

Attention is currently required from: Paul Menzel. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58886 ) Change subject: Documentation: Add some notes about how to integrate FSP ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58886/comment/4e54a9d2_d477973f PS1, Line 7: Documentation: Some notes about how to integrate FSP > Nit: Please add verb: Add some notes … Done File Documentation/soc/intel/fsp/index.md: https://review.coreboot.org/c/coreboot/+/58886/comment/b4776716_9d2a09f5 PS1, Line 8: has an effect on > affects Done https://review.coreboot.org/c/coreboot/+/58886/comment/a9eccb11_b4caba81 PS1, Line 11: * It should be possible to replace FSP based boot with a native : coreboot implementation for a given chipset without touching the : mainboard code. : * The devicetree configures coreboot and part of what coreboot does : with the information is setting some FSP UPDs. The devicetree isn't : supposed to directly configure FSP. > Reflow for full textwidth? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 19 Nov 2021 14:35:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation: Add some notes about how to integrate FSP
by Patrick Georgi (Code Review) 19 Nov '21

19 Nov '21

Hello build bot (Jenkins), Paul Menzel, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58886 to look at the new patch set (#2). Change subject: Documentation: Add some notes about how to integrate FSP ...................................................................... Documentation: Add some notes about how to integrate FSP While we don't _want_ FSP, we can't get around it sometimes. But when using it, we can still try to establish best practices to make life easier for everybody. Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/soc/intel/fsp/index.md 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/58886/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Gerrit-Change-Number: 58886 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2021