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Change subject: mb/google/brya/variants/primus: update gpios for power consumption
......................................................................
Patch Set 5: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: src/arch/ppc64/*: pass FDT address to payload
......................................................................
src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed first to
romstage, then to ramstage, where it's put into CMBEM to be read on
starting payload.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/arch/ppc64/boot.c
M src/arch/ppc64/bootblock_crt0.S
M src/commonlib/include/commonlib/cbmem_id.h
M src/mainboard/emulation/qemu-power8/memlayout.ld
M src/mainboard/emulation/qemu-power9/memlayout.ld
5 files changed, 44 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/20
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Change subject: payloads/external: add skiboot (for QEMU/Power9)
......................................................................
payloads/external: add skiboot (for QEMU/Power9)
Add an option to build skiboot as a payload. This makes QEMU Power9
board simpler to use as skiboot is necessary anyway.
Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372
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---
M Documentation/mainboard/emulation/qemu-power9.md
M payloads/Makefile.inc
M payloads/external/.gitignore
M payloads/external/Makefile.inc
A payloads/external/skiboot/Kconfig
A payloads/external/skiboot/Kconfig.name
A payloads/external/skiboot/Makefile
M src/mainboard/emulation/qemu-power9/Kconfig
8 files changed, 105 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58656/9
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I'd like you to reexamine a change. Please visit
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Change subject: src/arch/ppc64/*: pass FDT address to payload
......................................................................
src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed first to
romstage, then to ramstage, where it's put into CMBEM to be read on
starting payload.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M 3rdparty/blobs
M src/arch/ppc64/boot.c
M src/arch/ppc64/bootblock_crt0.S
M src/commonlib/include/commonlib/cbmem_id.h
M src/mainboard/emulation/qemu-power8/memlayout.ld
M src/mainboard/emulation/qemu-power9/memlayout.ld
6 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/57084/19
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Change subject: [WIP] src/drivers/intel/fsp2_0: Update GUID for new FSP_NON_VOLATILE_STORAGE_HOB2 HOB
......................................................................
[WIP] src/drivers/intel/fsp2_0: Update GUID for new FSP_NON_VOLATILE_STORAGE_HOB2 HOB
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
---
M src/drivers/intel/fsp2_0/hand_off_block.c
1 file changed, 8 insertions(+), 0 deletions(-)
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59449 )
Change subject: amdfwtool: clean up psp fw parsing
......................................................................
Patch Set 4:
(2 comments)
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/59449/comment/f785146b_51aa1e67
PS2, Line 110: psp_dir_valid_entries
> That's totally reasonable, I just wanted to check that this kind of refactoring would be acceptable […]
Done in CB:59584
https://review.coreboot.org/c/coreboot/+/59449/comment/a7b2eb60_d445c755
PS2, Line 178: if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) {
: if (!cb_config->have_whitelist)
: fw_type = AMD_FW_SKIP;
: }
> Yes that is on my mind for next cleanup, but again I didn't want it to be in this CL for keep this C […]
Done in CB:59583
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 )
Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Having read this code I'm very much unconvinced of the code to count big/small core into a bitmask a […]
Looking at code and referring to the sample implementation, I think below are only changes that we need to support
hybrid/heterogeneous cause for ADL.
#define SCALING_FACTOR_CORE_SMALL 100
#define SCALING_FACTOR_CORE_BIG 127
// note, this should come from SoC only not from common code, as there might be different value for MTL/LNL etc.
// max_non_turbo_ratio = https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block…
#define GET_OVERRIDE_NOMINAL_FREQ(max_non_turbo_ratio, core_type) ((max_non_turbo_ratio * SCALING_FACTOR_CORE_##core_type)/100)
get_core_type => preferably return an enum between BIG and SMALL
- Based on SOC Kconfig, for ADL-N, you can safely return ADL-N as SMALL
- For others, cpuid leaf fn can be implemented in IA-common core to return the core type
Sample Override Function:
1. We can use ADL SoC Kconfig for P/M/N to safely say the platform supports Nominal Freq override
2. Implement function/macro to calculate the Nominal overridden value for Big and Small core
- sample above GET_OVERRIDE_NOMINAL_FREQ macro
3. Check the core type, sample function above (get_core_type)
4. Based on the core type from #3 above.
- Override _CPC table nominal perf element using #2 macro implementation.
Scope(\_SB.PR00)
{
// Perform Nominal Freq override if support by platform
// (Supported platform are ADL-P/M and N)
// to _CPC fields for supporting heterogeneous core
Return (CPC3)
}
Scope(\_SB.PR01)
{
}
...
Scope(\_SB.PR0n)
{
}
Good part of coreboot implementation is that
1. We are using 'C' code to create a runtime SSDT hence, we can use
those checks as mentioned in #1 above easily.
2. Don't need any GNVS.
3. Don't need to create any new cpu_index() function that returns sorted cpu index.
4. You can run this entire implementation using coreboot MP code so that #3 can get satisfied.
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59558 )
Change subject: mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VS
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/zork/variants/shuboz/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/59558/comment/d784e54d_45147c1c
PS5, Line 2: fw_config
Can you work on using probe in devicetree like what's done in line 76-96 here?
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Change subject: emulation/qemu-i440fx: Use a 4MB ROM by default
......................................................................
Patch Set 2: Code-Review+2
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