coreboot-gerrit November 2021

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Change in coreboot[master]: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs i...
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59519 to look at the new patch set (#7). Change subject: security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS ...................................................................... security/intel/txt: Fix HEAP_ACM format depending on number of ACMs in CBFS Since we may have either BIOS ACM or both BIOS and SINIT ACMs in CBFS, the size of txt_heap_acm_element will be different. We cannot always hardcode the size of ACM addresses array for two ACMs. If only the BIOS was included, the BDR parsing failed in TBoot due to invalid size of HEAP_ACM element. Check if SINIT ACM is present in CBFS and push properly formatted BDR region onto the TXT heap. Use two separate txt_heap_acm_element structures with different lengths. TEST=Boot QubesOS 4.0 with TBoot 1.8.2 on Dell OptiPlex 9010 with and without SINTI ACM in CBFS and see that TBoot no longer complains on the wrong size of HEAP_ACM element Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e --- M src/security/intel/txt/ramstage.c M src/security/intel/txt/txt_register.h 2 files changed, 116 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/59519/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/59519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c37a66d96e1ca3fb4d3f665e3ad35c6f1c5c1e Gerrit-Change-Number: 59519 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Add SAR sensor for bugzzy
by Gwendal Grignou (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: SH Kim, Gwendal Grignou. Hello build bot (Jenkins), SH Kim, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59609 to look at the new patch set (#3). Change subject: mb/google/dedede: Add SAR sensor for bugzzy ...................................................................... mb/google/dedede: Add SAR sensor for bugzzy Present 2 SX9360 SAR sensor for bugzzy. Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/bugzzy/gpio.c M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb 3 files changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/59609/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/59609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9feef9d132c60738bafb22ceb7d3468c798fab9b Gerrit-Change-Number: 59609 Gerrit-PatchSet: 3 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59523 ) Change subject: nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXT ...................................................................... Patch Set 6: (4 comments) File src/northbridge/intel/sandybridge/romstage.c: https://review.coreboot.org/c/coreboot/+/59523/comment/8d25c3b6_2885c901 PS2, Line 78: #if CONFIG(INTEL_TXT) > > I'm afraid I don't follow. The only redundant MSR writing I see is the one CB:59521 adds. […] Done File src/northbridge/intel/sandybridge/romstage.c: https://review.coreboot.org/c/coreboot/+/59523/comment/0a5356e3_5a9f380a PS3, Line 28: #if CONFIG(INTEL_TXT) > Actually not, we can always configure the DPR Done https://review.coreboot.org/c/coreboot/+/59523/comment/e0869818_45c524c9 PS3, Line 35: /* 3 MiB should be enough */ > I'd omit this comment. Done https://review.coreboot.org/c/coreboot/+/59523/comment/cf0e86c1_20384e67 PS3, Line 36: pci_write_config32(HOST_BRIDGE, DPR, dpr.raw); > dpr. […] Added a comment to explain how it works inside the configure_dpr function. -- To view, visit https://review.coreboot.org/c/coreboot/+/59523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Gerrit-Change-Number: 59523 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 01:13:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59521 ) Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed ...................................................................... Abandoned Duplicates already present functionality -- To view, visit https://review.coreboot.org/c/coreboot/+/59521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d Gerrit-Change-Number: 59521 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Shon Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/0bba0306_60765237 PS6, Line 16: 40, 30, 30, 30, 30 > Done Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 7 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 01:12:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 ) Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Dropping this patch since it duplicates already present functionality -- To view, visit https://review.coreboot.org/c/coreboot/+/59521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d Gerrit-Change-Number: 59521 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 01:12:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: update memory settings
by Shon Wang (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Kevin Chiu, YH Lin, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph. Shon Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59334 ) Change subject: mb/google/brya/var/vell: update memory settings ...................................................................... Patch Set 7: (3 comments) File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/570ab283_ff4a479b PS5, Line 7: __weak > remove if you want to override Done https://review.coreboot.org/c/coreboot/+/59334/comment/9849d3e4_833c45f7 PS5, Line 26: __weak > remove if you want to override Done File src/mainboard/google/brya/variants/vell/memory.c: https://review.coreboot.org/c/coreboot/+/59334/comment/c2bb5da4_7f95f9ae PS6, Line 16: 40, 30, 30, 30, 30 > I believe Intel's recommended values for LP5 are […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Gerrit-Change-Number: 59334 Gerrit-PatchSet: 7 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 01:12:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/i2c: Add sx9360 driver
by Gwendal Grignou (Code Review) 25 Nov '21

25 Nov '21

Hello build bot (Jenkins), SH Kim, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59608 to look at the new patch set (#2). Change subject: driver/i2c: Add sx9360 driver ...................................................................... driver/i2c: Add sx9360 driver Add driver for setting up Semtech sx9360 SAR sensor. Registers are documented in the kernel tree: Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 --- A src/drivers/i2c/sx9360/Kconfig A src/drivers/i2c/sx9360/Makefile.inc A src/drivers/i2c/sx9360/chip.h A src/drivers/i2c/sx9360/sx9360.c 4 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59608/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a912f184e6f3501f894cca24c0d71a2c3087516 Gerrit-Change-Number: 59608 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/txt: Fix GETSEC checks in romstage
by Michał Żygowski (Code Review) 25 Nov '21

25 Nov '21

Attention is currently required from: Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59520 ) Change subject: security/intel/txt: Fix GETSEC checks in romstage ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59520/comment/49897f3a_4ad509da PS3, Line 11: Also noticed that the lock bit : of IA32_FEATURE_CONTROL cannot be cleared by issuing neither global : reset nor full reset on Sandybridge/Ivybridge platforms which results : in a reset loop. > Well, I was also surprised I cannot unlock this MSR with full_reset on Dell OptiPlex 9010. […] Nothing we can do about it probably. -- To view, visit https://review.coreboot.org/c/coreboot/+/59520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9 Gerrit-Change-Number: 59520 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 25 Nov 2021 01:11:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build ...
by David Wu (Code Review) 25 Nov '21

25 Nov '21

David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59560 ) Change subject: mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phase ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/59560/comment/964f6655_182f73cd PS4, Line 7: EVT > we usually try not to mention specific build phases, but rather just say "for the next build phase" Done. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/59560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465 Gerrit-Change-Number: 59560 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 25 Nov 2021 01:11:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2021