coreboot-gerrit January 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skl: add SLP_S0 residency register and enable LPIT support
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Justin TerAvest, Matt DeVillier, Duncan Laurie, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, Shaunak Saha, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49047 to look at the new patch set (#4). Change subject: soc/intel/skl: add SLP_S0 residency register and enable LPIT support ...................................................................... soc/intel/skl: add SLP_S0 residency register and enable LPIT support Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/pmc.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/49047/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f Gerrit-Change-Number: 49047 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Justin TerAvest, Matt DeVillier, Duncan Laurie, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, Shaunak Saha, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49046 to look at the new patch set (#4). Change subject: soc/intel/cnl: add SLP_S0 residency register and enable LPIT support ...................................................................... soc/intel/cnl: add SLP_S0 residency register and enable LPIT support Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Tested-By: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/49046/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/49046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Gerrit-Change-Number: 49046 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: acpi,soc/intel/common: add support for Intel Low Power Idle Table
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Hello Felix Singer, build bot (Jenkins), Shaunak Saha, Patrick Georgi, Furquan Shaikh, Justin TerAvest, Matt DeVillier, Duncan Laurie, Paul Menzel, Patrick Rudolph, Nico Huber, Martin Roth, Tim Wawrzynczak, Shaunak Saha, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49045 to look at the new patch set (#3). Change subject: acpi,soc/intel/common: add support for Intel Low Power Idle Table ...................................................................... acpi,soc/intel/common: add support for Intel Low Power Idle Table Add support for the Intel LPIT table to support reading Low Power Idle Residency counters by the OS. On platforms supporting S0ix sleep states there can be two types of residencies: * CPU package PC10 residency counter (read from MSR via FFH interface) * PCH SLP_S0 assertion residency counter (read via memory mapped interface) With presence of one or both of these counters in the LPIT table, Linux dynamically adds the corresponding attributes to the cpuidle sysfs interface, that can be used to read the residency timers: * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us The code in src/acpi implements generic LPIT support. Each SoC or platform has to implement `acpi_fill_lpit` to fill the table with platform-specific LPI state entries. This is done in this change for soc/intel/common, while being added as its own compilation unit, so SoCs not yet using common acpi code (like Skylake) can use it, too. Reference: https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle… Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. Windows and Linux tested on google/akemi together with CB:49046 Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Tested-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc M src/soc/intel/common/block/acpi/acpi.c A src/soc/intel/common/block/acpi/lpit.c 7 files changed, 182 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/49045/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/49045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Gerrit-Change-Number: 49045 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {soc,vc,mb}/intel: Remove support for Cannon Lake SoC
by Christian Walter (Code Review) 02 Jan '21

02 Jan '21

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48775 ) Change subject: {soc,vc,mb}/intel: Remove support for Cannon Lake SoC ...................................................................... Patch Set 10: -Code-Review Alright 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/48775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Gerrit-Change-Number: 48775 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Jan 2021 19:54:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48750 ) Change subject: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI ...................................................................... Patch Set 39: (1 comment) https://review.coreboot.org/c/coreboot/+/48750/39//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48750/39//COMMIT_MSG@15 PS39, Line 15: Test: Panel gets enabled when the payload starts on Clevo L141CU. > for unknown reasons this suddenly stopped working... need to debug this. […] problem was on my local branch -- To view, visit https://review.coreboot.org/c/coreboot/+/48750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Gerrit-Change-Number: 48750 Gerrit-PatchSet: 39 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Jan 2021 19:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: {soc,vc,mb}/intel: Remove support for Cannon Lake SoC
by Angel Pons (Code Review) 02 Jan '21

02 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48775 ) Change subject: {soc,vc,mb}/intel: Remove support for Cannon Lake SoC ...................................................................... Patch Set 10: > Patch Set 10: Code-Review-1 > > What's the downsite to have this in the tree? Skylake-SP FSP Binaries are also not available publicly (and most likely never will) - however this should also stay in the tree. I am a friend of having broad support here. The Core i3-8121U [1] is the only Cannon Lake product that has been released. CNL was soon superseded by Ice Lake. Not only are the FSP binaries for CNL missing, but the hardware itself is also hard to find. Moreover, no one seems to use or maintain CNL support anymore. Given that CNL support complicates maintenance of the other platforms supported in soc/intel/cannonlake, continuing to support an abandoned platform isn't worth the effort. While I'm not happy about the Skylake-SP situation, I know there's people with access to the FSP binaries that use the code, and there's people maintaining the code. The hardware is available as well (even though it's not cheap). If someone ever sends a patch to drop Skylake-SP support from coreboot, I know several people who would not be happy about it 😜 [1]: https://ark.intel.com/content/www/us/en/ark/products/136863/intel-core-i3-8… -- To view, visit https://review.coreboot.org/c/coreboot/+/48775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Gerrit-Change-Number: 48775 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Jan 2021 19:16:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: Add maintainer for ACPI
by Maxim Polyakov (Code Review) 02 Jan '21

02 Jan '21

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48970 ) Change subject: MAINTAINERS: Add maintainer for ACPI ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65fdee350273c58e027a002dba1f97a56115e195 Gerrit-Change-Number: 48970 Gerrit-PatchSet: 4 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Jan 2021 19:11:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: add macro for one internal panel in gfx struct
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49054 ) Change subject: drivers/intel/gma: add macro for one internal panel in gfx struct ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/49054/1/src/drivers/intel/gma/gma.h File src/drivers/intel/gma/gma.h: https://review.coreboot.org/c/coreboot/+/49054/1/src/drivers/intel/gma/gma.… PS1, Line 33: at port A > not sure what you mean. datasheet and prm mention these ports. […] . -- To view, visit https://review.coreboot.org/c/coreboot/+/49054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818 Gerrit-Change-Number: 49054 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Jan 2021 17:55:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: add macro for one internal panel in gfx struct
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49054 ) Change subject: drivers/intel/gma: add macro for one internal panel in gfx struct ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/49054/1/src/drivers/intel/gma/gma.h File src/drivers/intel/gma/gma.h: https://review.coreboot.org/c/coreboot/+/49054/1/src/drivers/intel/gma/gma.… PS1, Line 33: at port A > Actually, I'm not sure if/how Intel really uses the port encoding. not sure what you mean. datasheet and prm mention these ports. however, I have not yet found a proof that A==0, but the prm looks like that at least -- To view, visit https://review.coreboot.org/c/coreboot/+/49054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818 Gerrit-Change-Number: 49054 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Jan 2021 17:54:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: {soc,vc,mb}/intel: Remove support for Cannon Lake SoC
by Michael Niewöhner (Code Review) 02 Jan '21

02 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48775 ) Change subject: {soc,vc,mb}/intel: Remove support for Cannon Lake SoC ...................................................................... Patch Set 10: > Patch Set 10: Code-Review-1 > > What's the downsite to have this in the tree? Skylake-SP FSP Binaries are also not available publicly (and most likely never will) - however this should also stay in the tree. I am a friend of having broad support here. A friend of maintaining dead platforms that noone can test? ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/48775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Gerrit-Change-Number: 48775 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 02 Jan 2021 17:49:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2021