coreboot-gerrit January 2021

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Change in coreboot[master]: drivers/intel/gma: add macro for one internal panel in gfx struct
by Nico Huber (Code Review) 03 Jan '21

03 Jan '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49054 ) Change subject: drivers/intel/gma: add macro for one internal panel in gfx struct ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/49054/1/src/drivers/intel/gma/gma.h File src/drivers/intel/gma/gma.h: https://review.coreboot.org/c/coreboot/+/49054/1/src/drivers/intel/gma/gma.… PS1, Line 33: at port A > PRM (Doc Ref # IHD-OS-KBL-Vol 12-1.17) / intel-gfx-prm-osrc-kbl-vol12-display.pdf : Page 108 has a table with "DDI Equivalent Names": > > DDI A: Port 0, DDI-A, DDIA, Port A, DDI0, eDP > DDI B: Port 1, DDI-B, DDIB, Port B, DDI1 > ... In other words, it doesn't mention ACPI? At least i915 doesn't seem to use the field at all, cf. `ACPI_DISPLAY_PORT_ATTACHMENT_SHIFT` etc. in `display/intel_acpi.c`. -- To view, visit https://review.coreboot.org/c/coreboot/+/49054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818 Gerrit-Change-Number: 49054 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 03 Jan 2021 15:16:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2C
by Michael Niewöhner (Code Review) 03 Jan '21

03 Jan '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47984 ) Change subject: mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2C ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/47984/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47984/6//COMMIT_MSG@21 PS6, Line 21: successfully > But... what is success? If this change fixes something, please write it down. Well, in this case success is "it doesn't break and doesn't cause dmesg warnings/errors". This change is more like "do it right and comply to spec" than a fix for an actual problem. Also see related changes CB:47415, CB:47416, ... and discussion here https://review.coreboot.org/c/coreboot/+/47417/2/src/mainboard/google/hatch… -- To view, visit https://review.coreboot.org/c/coreboot/+/47984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia232c0a11546aa6d17614f4cab07c255e58f2fed Gerrit-Change-Number: 47984 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 03 Jan 2021 13:37:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2C
by Angel Pons (Code Review) 03 Jan '21

03 Jan '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47984 ) Change subject: mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2C ...................................................................... Patch Set 6: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/47984/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47984/6//COMMIT_MSG@21 PS6, Line 21: successfully But... what is success? If this change fixes something, please write it down. -- To view, visit https://review.coreboot.org/c/coreboot/+/47984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia232c0a11546aa6d17614f4cab07c255e58f2fed Gerrit-Change-Number: 47984 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 03 Jan 2021 11:59:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: add libgfxinit support
by Michael Niewöhner (Code Review) 03 Jan '21

03 Jan '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48751 ) Change subject: mb/clevo/l140cu: add libgfxinit support ...................................................................... mb/clevo/l140cu: add libgfxinit support Change-Id: Id58bb2ce5fdaeaf158d02d8c812ab2c331db352d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48751 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/clevo/cml-u/Kconfig M src/mainboard/clevo/cml-u/Makefile.inc A src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads 3 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 59205065..39b617f 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -13,6 +13,7 @@ select HAVE_SPD_IN_CBFS select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc index b69c257..213e62f 100644 --- a/src/mainboard/clevo/cml-u/Makefile.inc +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -6,5 +6,6 @@ ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads b/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/48751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id58bb2ce5fdaeaf158d02d8c812ab2c331db352d Gerrit-Change-Number: 48751 Gerrit-PatchSet: 41 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI
by Michael Niewöhner (Code Review) 03 Jan '21

03 Jan '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48750 ) Change subject: mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI ...................................................................... mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPI Add the panel settings dumped from vendor firmware and hook up drivers/intel/gma, which will be required for brightness control. Keyboard brightness control still requires ACPI code. This will be done in a separate change later. Test: Panel gets enabled when the payload starts on Clevo L141CU. Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/cml-u/dsdt.asl M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 2 files changed, 12 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl index 7555246..05e297b 100644 --- a/src/mainboard/clevo/cml-u/dsdt.asl +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -18,6 +18,7 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } #include <southbridge/intel/common/acpi/sleepstates.asl> diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 3329f63..d9a642a 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -65,7 +65,17 @@ device domain 0 on subsystemid 0x1558 0x1401 inherit device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_pwm_hz = 1000, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + }" + end device pci 04.0 on # SA Thermal device register "Device4Enable" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/48750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Gerrit-Change-Number: 48750 Gerrit-PatchSet: 40 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/gma: add macro for one internal panel in gfx struct
by Michael Niewöhner (Code Review) 03 Jan '21

03 Jan '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49054 ) Change subject: drivers/intel/gma: add macro for one internal panel in gfx struct ...................................................................... drivers/intel/gma: add macro for one internal panel in gfx struct Add a new macro `GMA_DEFAULT_PANEL(ssc)` as shortcut for specifying one internal panel at port A (0) in the devicetree. Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49054 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/gma/gma.h 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/gma/gma.h b/src/drivers/intel/gma/gma.h index ee7d730..a39198c 100644 --- a/src/drivers/intel/gma/gma.h +++ b/src/drivers/intel/gma/gma.h @@ -30,6 +30,12 @@ .ndid = 3, .did = { 0x0100, 0x0240, 0x0410, } \ } +/* Shortcut for one internal panel at port A */ +#define GMA_DEFAULT_PANEL(ssc) { \ + .use_spread_spectrum_clock = (ssc), \ + .ndid = 1, .did = { 0x0400 } \ +} + void drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *conf); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/49054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818 Gerrit-Change-Number: 49054 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Drop indirect <soc/nvs.h> include
by Kyösti Mälkki (Code Review) 03 Jan '21

03 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48803 ) Change subject: soc/intel: Drop indirect <soc/nvs.h> include ...................................................................... soc/intel: Drop indirect <soc/nvs.h> include Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/broadwell/include/soc/acpi.h M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/soc_acpi.c 12 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48803/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 1413dcb..e9e08c7 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -14,6 +14,7 @@ #include <cpu/intel/turbo.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index 8d9e93a..d629b24 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _BAYTRAIL_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> int acpi_sci_irq(void); unsigned long acpi_madt_irq_overrides(unsigned long current); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 63accb9..f754226 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -12,6 +12,7 @@ #include <device/pci.h> #include <drivers/intel/gma/opregion.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/gfx.h> #include <soc/iomap.h> #include <soc/irq.h> diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index 8ce8c2a..461913d 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _SOC_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> int acpi_sci_irq(void); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 39d6cb4..4999f8f 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _BROADWELL_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 05ee467..d634e70 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -12,6 +12,7 @@ #include <console/console.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/cpu.h> #include <soc/soc_util.h> #include <soc/pmc.h> diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 40d2098..5ee89f5 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _DENVERTON_NS_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long acpi_madt_irq_overrides(unsigned long current); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index b46c241..7b9e73d 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -19,6 +19,7 @@ #include <intelblocks/systemagent.h> #include <soc/intel/common/acpi.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 5f209a7..e12a748 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _SOC_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> /* P-state configuration */ #define PSS_MAX_ENTRIES 8 diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 4808344..4e374bd 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -10,6 +10,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 743251b..8c12cbf 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -4,7 +4,6 @@ #define _SOC_ACPI_H_ #include <acpi/acpi.h> -#include <soc/nvs.h> #define MEM_BLK_COUNT 0x140 typedef struct { diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 703ec21..ff3ea28 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -9,6 +9,7 @@ #include <device/mmio.h> #include <device/pci.h> #include <soc/acpi.h> +#include <soc/nvs.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <device/mmio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/48803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Gerrit-Change-Number: 48803 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Drop unnecessary <soc/nvs.h> include
by Kyösti Mälkki (Code Review) 03 Jan '21

03 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48830 ) Change subject: soc/intel: Drop unnecessary <soc/nvs.h> include ...................................................................... soc/intel: Drop unnecessary <soc/nvs.h> include Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/sd.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/sd.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48830/1 diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index e8253e0..8a2541c 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -7,7 +7,6 @@ #include <reg_script.h> #include <soc/iosf.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include "chip.h" diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 34a9031..b8473d8 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -7,7 +7,6 @@ #include <device/pci_ids.h> #include <soc/iosf.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include "chip.h" diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 954b5b4..4c8cbbf 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -7,7 +7,6 @@ #include <reg_script.h> #include <soc/iosf.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include "chip.h" diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 5d88016..9d18917 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -7,7 +7,6 @@ #include <device/pci_ids.h> #include <soc/iosf.h> -#include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/48830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6 Gerrit-Change-Number: 48830 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessor
by Kyösti Mälkki (Code Review) 03 Jan '21

03 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48783 ) Change subject: sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessor ...................................................................... sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessor Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/pch/me.c M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/lynxpoint/me_9.x.c 3 files changed, 8 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48783/1 diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 40a81d8..88d2172 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -28,10 +28,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif /* Path that the BIOS should take based on ME state */ static const char *me_bios_path_values[] = { @@ -772,10 +769,9 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index ae157d3..422c091 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -15,6 +15,8 @@ #include "me.h" #include "pch.h" +#include <vendorcode/google/chromeos/chromeos.h> + /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -362,10 +364,6 @@ return 0; } -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> -#endif - /* Read the Extend register hash of ME firmware */ int intel_me_extend_valid(struct device *dev) { @@ -405,10 +403,9 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 9910658..69192e6 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -25,10 +25,7 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] __unused = { @@ -755,10 +752,9 @@ } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687 Gerrit-Change-Number: 48783 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/google/chromeos: Move chromeos_set_me_hash() prototype
by Kyösti Mälkki (Code Review) 03 Jan '21

03 Jan '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48782 ) Change subject: vc/google/chromeos: Move chromeos_set_me_hash() prototype ...................................................................... vc/google/chromeos: Move chromeos_set_me_hash() prototype Change allows to remove some <chromeos/gnvs.h> exposure from coreboot proper. Change-Id: I7817914cc7b248331bb8fa79baa642ed548bbc11 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.h 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48782/1 diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 233eb42..315d693 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -45,6 +45,7 @@ #endif /* CONFIG_CHROMEOS_RAMOOPS */ void cbmem_add_vpd_calibration_data(void); +void chromeos_set_me_hash(u32*, int); /** * get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 74324a0..e44e292 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -45,7 +45,6 @@ } __packed chromeos_acpi_t; void chromeos_init_chromeos_acpi(chromeos_acpi_t *init); -void chromeos_set_me_hash(u32*, int); chromeos_acpi_t *chromeos_get_chromeos_acpi(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7817914cc7b248331bb8fa79baa642ed548bbc11 Gerrit-Change-Number: 48782 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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