coreboot-gerrit September 2020

coreboot-gerrit@coreboot.org

1 participants
2629 discussions

Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
by Subrata Banik (Code Review) 05 Jun '21

05 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44014 ) Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ...................................................................... src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE This patch ensures that the TSEG region is only mapped as cacheable so that one can perform SMRAM relocation faster. Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) and other ranges as reserve alone. TEST=Able to build and boot ICL, TGL RVP. Without this CL: PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL: PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e12e07c..b15ca01 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -173,8 +173,13 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TSEG */ base_k = top_of_ram; + size_k = sa_map_values[SA_TSEG_REG] - base_k; + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + + /* TSEG -> BGSM */ + base_k = sa_map_values[SA_TSEG_REG]; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/44014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Gerrit-Change-Number: 44014 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

8 46

Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review) 04 Jun '21

04 Jun '21

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231 Change subject: Add KASAN stubs to coreboot. ...................................................................... Add KASAN stubs to coreboot. Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN. Remove lint errors and warnings from kasan.c. Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> Changes to be committed: modified: src/Kconfig modified: src/lib/Makefile.inc new file: src/lib/kasan.c Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 --- M src/Kconfig M src/lib/Makefile.inc A src/lib/kasan.c 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..96e746e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -219,6 +219,15 @@ coverage information in CBMEM for extraction from user space. If unsure, say N. +config KASAN + bool "Kernel Address sanitizer support" + default y + help + Instrument the code with checks for UAF and OOB erros. If unsure, + say N because it adds a small performance penalty and may abort + on code that happens to work in spite of the UB. + + config UBSAN bool "Undefined behavior sanitizer support" default n diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..88afaaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,12 @@ CFLAGS_ramstage += -fsanitize=undefined endif +ifeq ($(CONFIG_KASAN),y) +ramstage-y += kasan.c +CFLAGS_ramstage += -fsanitize=kernel-address +endif + + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -83,7 +89,7 @@ romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -romstage-y += ramtest.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c romstage-y += region_file.c diff --git a/src/lib/kasan.c b/src/lib/kasan.c new file mode 100644 index 0000000..3f482e9 --- /dev/null +++ b/src/lib/kasan.c @@ -0,0 +1,29 @@ +#include <stddef.h> + +/* + *Empty stubs for required by gcc to add compiler code + */ +void __asan_handle_no_return(void); +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t x); +void __asan_storeN_noabort(unsigned long addr, size_t x); + + +void __asan_handle_no_return(void) { } +void __asan_load1_noabort(unsigned long addr) { } +void __asan_store1_noabort(unsigned long addr) { } +void __asan_load2_noabort(unsigned long addr) { } +void __asan_store2_noabort(unsigned long addr) { } +void __asan_load4_noabort(unsigned long addr) { } +void __asan_store4_noabort(unsigned long addr) { } +void __asan_store8_noabort(unsigned long addr) { } +void __asan_load8_noabort(unsigned long addr) { } +void __asan_loadN_noabort(unsigned long addr, size_t i) { } +void __asan_storeN_noabort(unsigned long addr, size_t i) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/32231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 Gerrit-Change-Number: 32231 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: [TEST]3rdparty/vboot: Vboot version update
by Wonkyu Kim (Code Review) 03 Jun '21

03 Jun '21

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39447 ) Change subject: [TEST]3rdparty/vboot: Vboot version update ...................................................................... [TEST]3rdparty/vboot: Vboot version update Update Vboot version to bb6c23472a0f to fix depthcharge build Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39447/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 5059062..bb6c234 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 5059062dd352e3864fb68f8a061e87bd7055d12a +Subproject commit bb6c23472a0fd0565b3991331b63a4ed319d7872 -- To view, visit https://review.coreboot.org/c/coreboot/+/39447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea Gerrit-Change-Number: 39447 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35645 ) Change subject: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE ...................................................................... vboot: Fix wrong algorithm in TCPA log for BOOT_MODE The hash algorithm for VBOOTs BOOT_MODE is fixed to sha1 but TCPA log uses sha256 as the name for the algorithm. This leads to an log entry with 20 bytes (sha1) while the algorithm is set to sha256 (which needs 32 bytes of hash). Fix it by using the matching algorithm name for BOOT_MODE. Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/tpm_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35645/1 diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 0a211c5..1db7189 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -46,7 +46,7 @@ switch (which_digest) { /* SHA1 of (devmode|recmode|keyblock) bits */ case BOOT_MODE_PCR: - return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, size, + return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size, TPM_PCR_BOOT_MODE); /* SHA256 of HWID */ case HWID_DIGEST_PCR: -- To view, visit https://review.coreboot.org/c/coreboot/+/35645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574 Gerrit-Change-Number: 35645 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: util/intelp2m/snr: Remove incorrent GPO macro
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44472 ) Change subject: util/intelp2m/snr: Remove incorrent GPO macro ...................................................................... util/intelp2m/snr: Remove incorrent GPO macro GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO and according to the changes in the project [1], this patch removes the code to generate PAD_CFG_GPO_GPIO_DRIVER macro. [1] Change-Id: I74c318897647836f4604a937543254f44b470433 Change-Id: Ibe7b787d455b638e70e54fb8b048c8aad8283037 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/platforms/snr/macro.go 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44472/1 diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 86cc7b7..3340ec0 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -213,11 +213,6 @@ dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) } macro.Set("PAD_CFG") - if macro.IsOwnershipDriver() { - // PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) - macro.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),") - return - } if term != 0 { // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), macro.Add("_TERM") -- To view, visit https://review.coreboot.org/c/coreboot/+/44472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe7b787d455b638e70e54fb8b048c8aad8283037 Gerrit-Change-Number: 44472 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/supermicro/x11-lga1151: undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44465 ) Change subject: mb/supermicro/x11-lga1151: undo set DRIVER for GPO ...................................................................... mb/supermicro/x11-lga1151: undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: I5aed5769600bb9c442ad13a2efbcf9d5fd8da537 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 1 file changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44465/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index f5e71ad..98e2d62 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -34,8 +34,8 @@ PAD_NC(GPP_A23, NONE), /* GPIO Group GPP_B */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B3, NONE), PAD_NC(GPP_B4, NONE), @@ -45,7 +45,7 @@ PAD_NC(GPP_B8, NONE), PAD_NC(GPP_B9, NONE), PAD_NC(GPP_B10, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), @@ -54,7 +54,7 @@ PAD_NC(GPP_B17, NONE), PAD_NC(GPP_B18, NONE), PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), PAD_NC(GPP_B21, NONE), PAD_NC(GPP_B22, NONE), PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), @@ -65,7 +65,7 @@ PAD_NC(GPP_C2, NONE), // PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_C5, 1, DEEP), // PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), @@ -87,10 +87,10 @@ /* GPIO Group GPP_D */ PAD_NC(GPP_D0, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), PAD_NC(GPP_D3, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), PAD_NC(GPP_D5, NONE), PAD_NC(GPP_D6, NONE), PAD_NC(GPP_D7, NONE), @@ -104,10 +104,10 @@ PAD_NC(GPP_D15, NONE), PAD_NC(GPP_D16, NONE), PAD_NC(GPP_D17, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), PAD_NC(GPP_D20, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), PAD_NC(GPP_D23, NONE), @@ -133,9 +133,9 @@ PAD_NC(GPP_F3, NONE), PAD_NC(GPP_F4, NONE), PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), @@ -150,7 +150,7 @@ PAD_NC(GPP_F20, NONE), PAD_NC(GPP_F21, NONE), PAD_NC(GPP_F22, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), /* GPIO Group GPP_G */ PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), @@ -179,16 +179,16 @@ PAD_NC(GPP_G23, NONE), /* GPIO Group GPP_H */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), PAD_NC(GPP_H12, NONE), @@ -198,11 +198,11 @@ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), PAD_NC(GPP_H18, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO Group GPP_I */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/44465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aed5769600bb9c442ad13a2efbcf9d5fd8da537 Gerrit-Change-Number: 44465 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/intel/glkrvp: Undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44466 ) Change subject: mb/intel/glkrvp: Undo set DRIVER for GPO ...................................................................... mb/intel/glkrvp: Undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: Iac7d674e79e0caee467fc087e6d36192e84a12d8 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44466/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 56df526..d70a064 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -35,7 +35,7 @@ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K), + PAD_CFG_TERM_GPO(GPIO_24, 1, DN_20K, DEEP), PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac7d674e79e0caee467fc087e6d36192e84a12d8 Gerrit-Change-Number: 44466 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44467 ) Change subject: mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO ...................................................................... mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register. Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/google/fizz/variants/endeavour/gpio.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44467/1 diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 432a180..716be3f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -28,9 +28,9 @@ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ -/* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP1 */ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* 7322_OE */ /* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ -/* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP3 */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* 7322_OE */ /* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), @@ -134,13 +134,11 @@ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, - NONE), /* TPU_RST_PIN40 */ +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* TPU_RST_PIN40 */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, - NONE), /* TPU_RST_PIN42 */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TPU_RST_PIN42 */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ /* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea Gerrit-Change-Number: 44467 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/intel/cedarisland/gpio: use macros for bidirectional pads
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43456 ) Change subject: mb/intel/cedarisland/gpio: use macros for bidirectional pads ...................................................................... mb/intel/cedarisland/gpio: use macros for bidirectional pads The configuration contains pads in which both buffers (Tx/Rx) [1] are enabled. Therefore, they are bidirectional. Use the new macros instead PAD_CFG_GPIO_BIDIRECT() [2] of common _PAD_CFG_STRUCT() to configure these pads. [1] Intel document #549921 [2] https://review.coreboot.org/c/coreboot/+/42914 Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/intel/cedarisland_crb/include/gpio.h 1 file changed, 10 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/43456/1 diff --git a/src/mainboard/intel/cedarisland_crb/include/gpio.h b/src/mainboard/intel/cedarisland_crb/include/gpio.h index cd15fed..2a5fb11 100644 --- a/src/mainboard/intel/cedarisland_crb/include/gpio.h +++ b/src/mainboard/intel/cedarisland_crb/include/gpio.h @@ -173,10 +173,7 @@ /* GPP_C9 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, RSMRST, OFF, DRIVER), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI), /* GPP_C11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, RSMRST, OFF, ACPI), /* GPP_C12 - GPIO */ @@ -318,10 +315,7 @@ /* GPP_I3 - LAN_TDI */ PAD_CFG_NF(GPP_I3, NONE, RSMRST, NF2), /* GPP_I4 - GPIO */ - _PAD_CFG_STRUCT(GPP_I4, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_I4, 0, NONE, RSMRST, OFF, ACPI), /* GPP_I5 - GPIO */ PAD_CFG_GPO(GPP_I5, 0, RSMRST), /* GPP_I6 - GPIO */ @@ -364,17 +358,11 @@ /* GPP_J12 - GPIO */ PAD_CFG_GPO(GPP_J12, 0, RSMRST), /* GPP_J13 - GPIO */ - _PAD_CFG_STRUCT(GPP_J13, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_J13, 0, NONE, RSMRST, OFF, ACPI), /* GPP_J14 - GPIO */ PAD_CFG_GPO(GPP_J14, 0, RSMRST), /* GPP_J15 - GPIO */ - _PAD_CFG_STRUCT(GPP_J15, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_J15, 0, NONE, RSMRST, OFF, ACPI), /* GPP_J16 - GPIO */ PAD_CFG_GPO(GPP_J16, 0, RSMRST), /* GPP_J17 - GPIO */ @@ -468,42 +456,24 @@ /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - _PAD_CFG_STRUCT(GPP_H0, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H0, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H1 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, RSMRST, OFF, ACPI), /* GPP_H2 - GPIO */ - _PAD_CFG_STRUCT(GPP_H2, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H2, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H3 - GPIO */ - _PAD_CFG_STRUCT(GPP_H3, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H3, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H4 - GPIO */ - _PAD_CFG_STRUCT(GPP_H4, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H4, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H5 - RESERVED */ /* GPP_H6 - SRCCLKREQ12# */ PAD_CFG_NF(GPP_H6, NONE, RSMRST, NF1), /* GPP_H7 - GPIO */ - _PAD_CFG_STRUCT(GPP_H7, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H7, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H8 - SRCCLKREQ14# */ PAD_CFG_NF(GPP_H8, NONE, RSMRST, NF1), /* GPP_H9 - GPIO */ - _PAD_CFG_STRUCT(GPP_H9, - PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(NO_DISABLE), - PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPIO_BIDIRECT(GPP_H9, 0, NONE, RSMRST, OFF, ACPI), /* GPP_H10 - RESERVED */ /* GPP_H11 - RESERVED */ /* GPP_H12 - GPIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32a10ead1d965811f6e644124ba84ceb2264ddc4 Gerrit-Change-Number: 43456 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU
by Maxim Polyakov (Code Review) 17 May '21

17 May '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39764 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39764/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c7fa3e7..8bea454 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -48,6 +48,39 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2efb520..5872e7a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,10 +264,23 @@ static void soc_gpu_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); if (dev && dev->enabled && CONFIG(ONBOARD_VGA_IS_PRIMARY) { m_cfg->PrimaryVideoAdaptor = PRIMARY_IGD; + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; } else { m_cfg->PrimaryVideoAdaptor = PRIMARY_PCI; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8013980259aadeb3a1fd504d31062ccb5ef7af Gerrit-Change-Number: 39764 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2020