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Change in coreboot[master]: [RFC] treewide: Configure PCI Bus Master based on config option
by Felix Singer (Code Review) 17 Jun '21

17 Jun '21

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42460 ) Change subject: [RFC] treewide: Configure PCI Bus Master based on config option ...................................................................... [RFC] treewide: Configure PCI Bus Master based on config option Change-Id: I25565315a5ddf8d53097ac4cb4884ecebcc9c0a9 Signed-off-by: Felix Singer <felix.singer(a)secunet.com> --- M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c M src/soc/amd/stoneyridge/psp.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/scs/early_mmc.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/xhci.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/i82801dx/usb.c M src/southbridge/intel/i82801dx/usb2.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_ehci.c 65 files changed, 101 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/42460/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 3d48ca2..af21802 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -157,7 +157,7 @@ mmio = res2mmio(gtt_res, 0, 0); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 68072ff..8320f59 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -468,7 +468,7 @@ gma_setup_panel(dev); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c6b5a12..64a843e 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,7 +59,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 929968e..f677d50 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -671,7 +671,7 @@ ; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; @@ -711,7 +711,7 @@ u8 val; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val); diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b6c5f0f..908ff8d 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -132,8 +132,8 @@ early_cpu_init(); pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); - pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Magic for S3 resume. Must be done early. */ if (s3_resume) { diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 8baccb2..9fabe74 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -138,7 +138,7 @@ intel_gma_init_igd_opregion(); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res || !gtt_res->base) diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e46bd7c..12a1b7c 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -221,7 +221,7 @@ intel_gma_init_igd_opregion(); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI init, will run VBIOS */ diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 83a0279..fbf25b3 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -591,7 +591,7 @@ gma_pm_init_pre_vbios(dev); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) /* PCI Init, will run VBIOS */ diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 68d382e..1e77b4b 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -25,7 +25,7 @@ intel_gma_init_igd_opregion(); if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* configure GMBUSFREQ */ pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c index c24b8be..f7bed62 100644 --- a/src/soc/amd/stoneyridge/psp.c +++ b/src/soc/amd/stoneyridge/psp.c @@ -26,8 +26,9 @@ /* Enable memory access and master */ cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND); - cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + cmd |= PCI_COMMAND_MEMORY; pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); + pci_configure_bus_master(dev); }; void *soc_get_mbox_address(void) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 2137e49..828d0b7 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -68,8 +68,8 @@ pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); pci_write_config16(pmc, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } void bootblock_soc_early_init(void) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 094e1c2..d66d543 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -267,7 +267,8 @@ /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SPECIAL); + pci_configure_bus_master(dev); /* Use IRQ9 for SCI Interrupt */ write32((void *)(ilb_base + ACTL), 0); diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index b8699a2..dcff272 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -23,7 +23,8 @@ u32 tmp32; /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 1640825..569dc26 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -93,7 +93,7 @@ printk(BIOS_DEBUG, "HDA: base = %p\n", base); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); hda_pch_init(dev, base); diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 41167b1..6a81f53 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -501,7 +501,7 @@ return; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 7449902..c903605 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -721,7 +721,8 @@ mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index b91d73d..725e9dc 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -61,7 +61,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 9eb14d9..9271fe1 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -580,7 +580,7 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 20a5d9a..cd33d55 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -163,7 +163,8 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index fecc71e..5c355a5 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -95,7 +95,8 @@ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); /* Enable Bus Master and MMIO Space */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); cse.sec_bar = tempbar; } diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 655d113..e741892 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -272,7 +272,8 @@ spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY); /* Enable Bus Master and MMIO Space */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init(); diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index f232ee5..8e3b1a3 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -55,7 +55,7 @@ return; if (!CONFIG(NO_GFX_INIT)) - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e..65bd287 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -172,8 +172,8 @@ static void gspi_set_base_addr(int devfn, struct device *dev, uintptr_t base) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } #endif diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index f7c241d..8931731 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -68,8 +68,9 @@ /* Prepare early base address for access before memory */ base = dw_i2c_get_soc_early_base(bus); pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + pci_configure_bus_master(dev); /* Take device out of reset */ lpss_reset_release(base); diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 4f4ab43..128be7a 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -22,8 +22,8 @@ pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } /* diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index f36366a..b06f86c 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -19,7 +19,7 @@ pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); diff --git a/src/soc/intel/common/block/scs/early_mmc.c b/src/soc/intel/common/block/scs/early_mmc.c index caee7d9..69d035d 100644 --- a/src/soc/intel/common/block/scs/early_mmc.c +++ b/src/soc/intel/common/block/scs/early_mmc.c @@ -31,8 +31,9 @@ { pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, PRERAM_MMC_BASE_ADDRESS); - pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + + pci_configure_bus_master(dev); } static void disable_mmc_controller_bar(void) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index cc5e485..9a8eb1d 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -14,7 +14,7 @@ #include <soc/iomap.h> #include <soc/nvs.h> -#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) +#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY) #define UART_CONSOLE_INVALID_INDEX 0xFF extern const struct uart_gpio_pad_config uart_gpio_pads[]; @@ -68,6 +68,7 @@ /* Enable memory access and bus master */ pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); + pci_configure_bus_master(dev); uart_lpss_init(device, baseaddr); } diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index 7514fee..e8b8c7a 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -42,7 +42,8 @@ #if (CONFIG(NON_LEGACY_UART_MODE)) PCI_COMMAND_MEMORY | #endif - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_IO); + pci_configure_bus_master(dev); #if (CONFIG(CONSOLE_SERIAL_230400)) /* Change the highest speed to 230400 */ diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 05c6484..8918c2d 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -452,8 +452,9 @@ /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_SPECIAL | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + PCI_COMMAND_SPECIAL | PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); + pci_configure_bus_master(dev); /* Serial IRQ initialization. */ pch_enable_serial_irqs(dev); diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 25a0e59..92dbf59 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -40,9 +40,9 @@ pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE; /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); + pci_configure_bus_master(dev); /* Setup power options. */ pch_power_options(dev); diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index d631117..0797cc3 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -23,9 +23,9 @@ /* SATA configuration is handled by the FSP */ /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | - PCI_COMMAND_IO); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + PCI_COMMAND_IO); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index abdeb60..a6874ff 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -16,8 +16,8 @@ printk(BIOS_NOTICE, "pch: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } static struct device_operations usb_xhci_ops = { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 43a88b7..4191a1a 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -97,8 +97,7 @@ write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN); } - dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); } diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 4f5d8ca..530a896 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -261,7 +261,7 @@ } /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 40b0cc2b..fd5f7d8 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -564,7 +564,8 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index e65b8e5..f03e91b 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -550,7 +550,8 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 895135b..2c90581 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -14,7 +14,7 @@ printk(BIOS_DEBUG, "PCI init.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index c381d33..663fc08 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -210,7 +210,7 @@ printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 8bc45f6..496892a 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -30,7 +30,7 @@ pci_write_config32(dev, 0xfc, 0x205b1708); #endif - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); //pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* For others, done in MRC. */ diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c index 2abfa8a..1c62372 100644 --- a/src/southbridge/intel/i82801dx/usb.c +++ b/src/southbridge/intel/i82801dx/usb.c @@ -11,7 +11,8 @@ { printk(BIOS_DEBUG, "USB: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + PCI_COMMAND_INVALIDATE); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c index e333bb6..508c1ee 100644 --- a/src/southbridge/intel/i82801dx/usb2.c +++ b/src/southbridge/intel/i82801dx/usb2.c @@ -12,7 +12,8 @@ { printk(BIOS_DEBUG, "USB: Setting up controller.. "); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); + PCI_COMMAND_INVALIDATE); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 205fb0d..af0b0f2 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -229,7 +229,7 @@ pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index 7fb489d..93d7177 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -29,7 +29,8 @@ enable_secondary = config->ide_enable_secondary; } - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + pci_configure_bus_master(dev); /* Native Capable, but not enabled. */ pci_write_config8(dev, 0x09, 0x8a); diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 7472438..363bfa6 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -13,9 +13,7 @@ u8 reg8; /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_configure_bus_master(dev); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index adf0e49..b3223b4 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -46,7 +46,7 @@ printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8ce57df..791ae1d 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -14,7 +14,7 @@ /* USB Specification says the device must be Bus Master */ printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); // Erratum pci_write_config8(dev, 0xca, 0x00); diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index f665ab7..fe581e1 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -17,7 +17,8 @@ u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); + pci_configure_bus_master(dev); reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 31) | (1 << 27); diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 6f82cb4..487507e 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -229,7 +229,7 @@ pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a8e7b11..6b07d8a 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -17,7 +17,7 @@ printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index cac0375..0621fdc 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -166,9 +166,9 @@ */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); + pci_configure_bus_master(dev); if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c index 64f23f6..6297f0e 100644 --- a/src/southbridge/intel/i82801ix/usb_ehci.c +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -11,7 +11,7 @@ static void usb_ehci_init(struct device *dev) { printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index 4ba7828..68c3023 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -229,7 +229,7 @@ pci_or_config32(dev, 0x120, (1 << 31) | (1 << 24) | (0x80 << 0)); /* VCi ID and map */ /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 5195522..23649a1 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -17,7 +17,7 @@ printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 73a7d82..2bf6809 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -160,9 +160,9 @@ */ pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | /* read-only in IDE modes */ PCI_COMMAND_IO); + pci_configure_bus_master(dev); if (sata_mode != 0) /* No AHCI: clear AHCI base */ pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 893bb29..51c71a7 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -11,7 +11,7 @@ static void usb_ehci_init(struct device *dev) { printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); printk(BIOS_DEBUG, "done.\n"); } diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4763703..f544c73 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -13,9 +13,9 @@ static void p64h2_ioapic_enable(struct device *dev) { /* We have to enable MEM and Bus Master for IOAPIC */ - uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - + uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, command); + pci_configure_bus_master(dev); } /** diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 59a384a..5a7a8cf 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -261,7 +261,7 @@ pci_write_config32(dev, 0xd0, reg32); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 2c9c87c..f413ec3 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -487,8 +487,9 @@ /* Ensure Memory and Bus Master bits are set */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 7ad9929..1be011e 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -29,7 +29,7 @@ pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x301b1728); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); access_cntl = pci_read_config8(dev, 0x80); diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index f415170..0410cf5 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -125,7 +125,7 @@ printk(BIOS_DEBUG, "Azalia: base = %p\n", base); /* Set Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); azalia_pch_init(dev, base); diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index aeab0c7..45f9c71 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -735,7 +735,8 @@ mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d957e8d..f7308a5 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -659,7 +659,7 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_configure_bus_master(dev); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index cdb1f35..03584c2 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -137,7 +137,8 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 52b3ed8..02ad4c0 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -72,7 +72,8 @@ /* Make sure memory space is enabled */ pci_write_config16(dev, PCI_COMMAND, pci_cmd | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + PCI_COMMAND_MEMORY); + pci_configure_bus_master(dev); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/42460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25565315a5ddf8d53097ac4cb4884ecebcc9c0a9 Gerrit-Change-Number: 42460 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: uti/cbfstool: Add option --pow2page
by Kyösti Mälkki (Code Review) 17 Jun '21

17 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41832 ) Change subject: uti/cbfstool: Add option --pow2page ...................................................................... uti/cbfstool: Add option --pow2page For add-stage command, --pow2page is equivalent of passing -P log2ceil(sizeof stage). The sizeof stage can be hard to determine in Makefile to be passed on the commandline. Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/cbfstool/cbfstool.c 1 file changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41832/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 4ec8c90..dd87a04 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -65,6 +65,7 @@ bool fill_partial_downward; bool show_immutable; bool stage_xip; + bool force_pow2_pagesize; bool autogen_attr; bool machine_parseable; bool unprocessed; @@ -169,6 +170,14 @@ DEBUG("File size is %zd (0x%zx)\n", data_size, data_size); + /* Use a page size that can fit the entire file. */ + if (param.force_pow2_pagesize) { + param.pagesize = 1; + while (param.pagesize < data_size) + param.pagesize <<= 1; + DEBUG("Page size is %d (0x%x)\n", param.pagesize, param.pagesize); + } + /* Include cbfs_file size along with space for with name. */ metadata_size += cbfs_calculate_file_header_size(param.name); /* Adjust metadata_size if additional attributes were added */ @@ -1259,7 +1268,7 @@ true, true}, {"add-payload", "H:r:f:n:c:b:C:I:p:vA:gh?", cbfs_add_payload, true, true}, - {"add-stage", "a:H:r:f:n:t:c:b:P:S:p:yvA:gh?", cbfs_add_stage, + {"add-stage", "a:H:r:f:n:t:c:b:P:Q:S:p:yvA:gh?", cbfs_add_stage, true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?j:", cbfs_add_master_header, true, true}, @@ -1311,6 +1320,7 @@ {"offset", required_argument, 0, 'o' }, {"padding", required_argument, 0, 'p' }, {"page-size", required_argument, 0, 'P' }, + {"pow2page", no_argument, 0, 'Q' }, {"ucode-region", required_argument, 0, 'q' }, {"size", required_argument, 0, 's' }, {"top-aligned", required_argument, 0, 'T' }, @@ -1405,7 +1415,7 @@ "Add a payload to the ROM\n" " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" - " [-a alignment] [-y|--xip] [-P page-size] [--ibb] " + " [-a alignment] [-y|--xip] [-P page-size] [-Q] [--ibb] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1664,6 +1674,9 @@ return 1; } break; + case 'Q': + param.force_pow2_pagesize = 1; + break; case 'o': param.cbfsoffset = strtoul(optarg, &suffix, 0); if (!*optarg || (suffix && *suffix)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6 Gerrit-Change-Number: 41832 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: mb/google/volteer: Add support for USB Type-C ports
by John Zhao (Code Review) 16 Jun '21

16 Jun '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40425 ) Change subject: mb/google/volteer: Add support for USB Type-C ports ...................................................................... mb/google/volteer: Add support for USB Type-C ports Two usb type-c ports under the actual Mux device. Each port has its own ACPI device entry (node). These nodes are the ones that the USB Type-C port/connnector devices will refer to in order to configure the mux. BUG=b:151646486 BRANCH=None TEST=Verify USB Type-C alternate mode (DP or TBT) along wth PMC control. Change-Id: I4b443a1ca1c5361652a69586b340b1c95e9c3f06 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- A src/mainboard/google/volteer/acpi/usbc.asl M src/mainboard/google/volteer/dsdt.asl 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40425/1 diff --git a/src/mainboard/google/volteer/acpi/usbc.asl b/src/mainboard/google/volteer/acpi/usbc.asl new file mode 100644 index 0000000..b185b2f --- /dev/null +++ b/src/mainboard/google/volteer/acpi/usbc.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +Scope (\_SB.PCI0.PMC.MUX) { + /* + * Mux driver looks for usb type-C devices underneath it through + * _DSD and _ADR, where _ADR specifies the device address on the + * parent bus. CON0 is representing the first type-C port and CON1 + * is representing the second. + */ + Device (CON0) + { + Name (_ADR, 0) + /* + * These properties should have the values that the driver needs + * to supply to the PMC via IPC when the muxes are being + * configured. + */ + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb2-port", 6 }, + Package () { "usb3-port", 3 }, + Package () { "sbu-orientation", "normal" }, + Package () { "hsl-orientation", "normal" }, + }, + }) + } + + Device (CON1) + { + Name (_ADR, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package () { "usb2-port", 5 }, + Package () { "usb3-port", 2 }, + Package () { "sbu-orientation", "normal" }, + Package () { "hsl-orientation", "normal" }, + }, + }) + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 640f7cd..1888267 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -50,4 +50,7 @@ /* Camera */ #include <soc/intel/tigerlake/acpi/ipu.asl> #include "acpi/mipi_camera.asl" + + /* usbc */ + #include "acpi/usbc.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/40425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b443a1ca1c5361652a69586b340b1c95e9c3f06 Gerrit-Change-Number: 40425 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: nb/intel/sandybridge: x86_64 support
by Patrick Rudolph (Code Review) 15 Jun '21

15 Jun '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44677 ) Change subject: nb/intel/sandybridge: x86_64 support ...................................................................... nb/intel/sandybridge: x86_64 support Add experimental x86_64 support. Tested on HP Z220: * Still boots on x86_32. * Boots to payload with CB:37395 applied on x86_64. Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smihandler.c 7 files changed, 51 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44677/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..97c8234 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_206AX +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select MMX select SSE2 select UDELAY_TSC diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..892b3e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1957,9 +1957,12 @@ { unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; + uintptr_t addr; - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + 4 * j; + write32((void *)addr, j & 2 ? b : a); + } sfence(); } @@ -1977,13 +1980,16 @@ unsigned int j; unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); + uintptr_t addr; - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); - - for (j = 0; j < 16; j++) - write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); - + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + j * 4; + write32((void *)addr, 0xffffffff); + } + for (j = 0; j < 16; j++) { + addr = 0x04000000 + channel_offset + channel_step + j * 4; + write32((void *)addr, 0); + } sfence(); } @@ -2925,14 +2931,14 @@ if (invert[patno - 1][i] & (1 << (j / 2))) val = ~val; - write32((void *)((1 << 26) + offset + i * step + j * 4), val); + write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); } } } else { for (i = 0; i < ARRAY_SIZE(pattern); i++) { for (j = 0; j < 16; j++) { const u32 val = pattern[i][j]; - write32((void *)((1 << 26) + offset + i * step + j * 4), val); + write32((void *)(uintptr_t)((1 << 26) + offset + i * step + j * 4), val); } } sfence(); diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 15be4ab..39d3b66 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -212,7 +212,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); if (RCBA32(CIR31) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2407d92..a108b42 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -265,18 +265,18 @@ { printk(BIOS_DEBUG, "CougarPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); - RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0)); - RCBA32_AND_OR(CIR5, ~0UL, (1 << 0)); - RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14)); - RCBA16_AND_OR(CIR2, ~0UL, (1 << 14)); + RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0)); + RCBA32_AND_OR(CIR5, ~0U, (1 << 0)); + RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14)); + RCBA16_AND_OR(CIR2, ~0U, (1 << 14)); RCBA32(DMC) = 0xc0388400; - RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18)); - RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1)); + RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18)); + RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1)); RCBA32_AND_OR(CIR7, ~0x1f, 0xf); RCBA32(PM_CFG) = 0x050f0000; RCBA32(CIR8) = 0x04000000; - RCBA32_AND_OR(CIR10, ~0UL, 0xfffff); - RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)); + RCBA32_AND_OR(CIR10, ~0U, 0xfffff); + RCBA32_AND_OR(CIR11, ~0U, (1 << 1)); RCBA32(CIR12) = 0x0001c000; RCBA32(CIR14) = 0x00061100; RCBA32(CIR15) = 0x7f8fdfff; @@ -378,10 +378,10 @@ reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); - pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); - pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); - pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); + pch_iobp_update(0xEB007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEB004000, ~0U, (1 << 7)); + pch_iobp_update(0xEC007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEC004000, ~0U, (1 << 7)); reg32 = RCBA32(CG); reg32 |= (1 << 31); @@ -672,7 +672,7 @@ /* Add it to DSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)(uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1c56e5e..7337eae 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -438,7 +438,7 @@ struct me_hfs hfs; u32 reg32; - mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 484f0f1..c350186 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -142,7 +142,7 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 7211da3..26b9074 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -96,23 +96,23 @@ case ACPI_S4: /* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */ reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); - reg16 &= ~0x03UL; + reg16 &= ~0x03U; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFU; /* FIXME: This looks broken (conditions are always false) */ if ((xhci_bar + 0x4C0) & 1) - pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000082, ~0U, (3 << 2)); if ((xhci_bar + 0x4D0) & 1) - pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000182, ~0U, (3 << 2)); if ((xhci_bar + 0x4E0) & 1) - pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000282, ~0U, (3 << 2)); if ((xhci_bar + 0x4F0) & 1) - pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); + pch_iobp_update(0xEC000382, ~0U, (3 << 2)); pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); @@ -192,7 +192,7 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; if (smm_region_overlaps_handler(&r)) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/44677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Gerrit-Change-Number: 44677 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: [WIP, HACK] broadwell: make uart support build again
by Angel Pons (Code Review) 14 Jun '21

14 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37553 ) Change subject: [WIP, HACK] broadwell: make uart support build again ...................................................................... [WIP, HACK] broadwell: make uart support build again @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @ @ @ DO NOT MERGE AS-IS! @ @ @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ I am fully aware this is an atrociously hideous kludge. Moreover, this change won't be properly build-tested by Mr. Jenkins, and it has not been tested on real hardware either. It only exists for backup purposes. Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/serialio.c 3 files changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37553/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 03aa3fb..61b62c8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += romstage/uart.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/systemagent.c @@ -16,6 +17,9 @@ bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/x86/early_reset.S +postcar-y += romstage/uart.c +ramstage-y += romstage/uart.c + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a1a29b6..43c62a9 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -14,13 +14,15 @@ */ #include <device/pci_def.h> +#include <console/uart.h> #include <reg_script.h> #include <stdint.h> -#include <uart8250.h> #include <soc/iobp.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> #include <soc/serialio.h> -const struct reg_script uart_init[] = { +const struct reg_script uart_init_script[] = { /* Set MMIO BAR */ REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), /* Enable Memory access and Bus Master */ @@ -41,6 +43,11 @@ REG_SCRIPT_END }; +uintptr_t uart_platform_base(int idx) +{ + return CONFIG_TTYS0_BASE; +} + void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ @@ -72,11 +79,11 @@ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); /* Initialize chipset uart interface */ - reg_script_run_on_dev(dev, uart_init); + reg_script_run_on_dev(dev, uart_init_script); /* * Perform standard UART initialization * Divisor 1 is 115200 BAUD */ - uart8250_mem_init(CONFIG_TTYS0_BASE, 1); + uart_init(0); } diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 161c875..50daa3f 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -282,7 +282,8 @@ if (serialio_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - uartmem_setbaseaddr(res->base); + printk(BIOS_ERR, "UART base address changed\n"); + //uartmem_setbaseaddr(res->base); } #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/37553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd Gerrit-Change-Number: 37553 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: [UNTESTED]cpu/x86/mp_init.c: Print out the SMM save state revision wh...
by Arthur Heymans (Code Review) 14 Jun '21

14 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45478 ) Change subject: [UNTESTED]cpu/x86/mp_init.c: Print out the SMM save state revision when relocating ...................................................................... [UNTESTED]cpu/x86/mp_init.c: Print out the SMM save state revision when relocating This can be used to determine the save state revision of a CPU. Change-Id: I751d226a9de60f5dd03fd2bcb8c473bdbd5923a0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mp_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45478/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4..3a48f1a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -721,6 +721,8 @@ return; } + printk(BIOS_DEBUG, "SMM save state revision: 0x%x\n", smm_revision()); + /* * The permanent handler runs with all cpus concurrently. Precalculate * the location of the new SMBASE. If using SMM modules then this -- To view, visit https://review.coreboot.org/c/coreboot/+/45478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I751d226a9de60f5dd03fd2bcb8c473bdbd5923a0 Gerrit-Change-Number: 45478 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/intel/common/smihandler.c: Add common gnvs update mechanism
by Arthur Heymans (Code Review) 14 Jun '21

14 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45476 ) Change subject: sb/intel/common/smihandler.c: Add common gnvs update mechanism ...................................................................... sb/intel/common/smihandler.c: Add common gnvs update mechanism With common save state handling there is no need for per southbridge handling. Change-Id: I9dc0258f1335c678f992e8ad83f96b73fc474ec8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 8 files changed, 12 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45476/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 8af1428..e24a53e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -184,18 +184,6 @@ xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 52b83dd..c71ff0b 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -130,7 +130,6 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index ff61c6f..cb42832 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -8,7 +8,7 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> +#include <cpu/x86/save_state.h> #include <elog.h> #include <halt.h> #include <option.h> @@ -268,7 +268,13 @@ "SMI#: SMM structures already initialized!\n"); return; } - southbridge_update_gnvs(reg8, &smm_initialized); + int node = get_apmc_node(reg8); + + if (node >= 0) { + if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs))) + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } break; case APM_CNT_FINALIZE: if (mainboard_finalized) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 562dae3..fa91c37 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,10 +21,6 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f..3ca507f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,10 +14,6 @@ struct global_nvs *gnvs; #endif -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 16ec025..f5e9b75 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -15,10 +15,6 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 2bc31cf..5bf18c9 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -145,18 +145,6 @@ #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index a033d68..007b383 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -221,7 +221,7 @@ static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; + int node; static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -269,10 +269,10 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { + node = get_apmc_node(reg8); + if (node >= 0) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc0258f1335c678f992e8ad83f96b73fc474ec8 Gerrit-Change-Number: 45476 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: mb/lenovo/x220/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 09 Jun '21

09 Jun '21

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37297 ) Change subject: mb/lenovo/x220/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/x220/devicetree: Use subsystemid inheritance Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x220/devicetree.cb 1 file changed, 15 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37297/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 26fa1a4..5ae1427 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -37,13 +37,11 @@ register "pci_mmio_size" = "1024" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21db - end # host bridge + subsystemid 0x17aa 0x21db inherit + + device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21db - end # vga controller + device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -80,49 +78,29 @@ device pci 19.0 on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21db - end # High Definition Audio - device pci 1c.0 on - subsystemid 0x17aa 0x21db - end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21db - end # PCIe Port #2 (wlan) - device pci 1c.2 on - subsystemid 0x17aa 0x21db - end # PCIe Port #3 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21db smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on - subsystemid 0x17aa 0x21db chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21fa - end + device pci 00.0 on end end end # PCIe Port #5 (SD) device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on - subsystemid 0x17aa 0x21db - end # PCIe Port #7 + device pci 1c.6 on end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21db - end # USB2 EHCI #1 + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge - subsystemid 0x17aa 0x21db chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -172,11 +150,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on - subsystemid 0x17aa 0x21db - end # SATA Controller 1 + device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - subsystemid 0x17aa 0x21db # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -190,9 +165,7 @@ end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21db - end # Thermal + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535 Gerrit-Change-Number: 37297 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Add missing ID for PCI bridge
by James (Code Review) 07 Jun '21

07 Jun '21

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41015 ) Change subject: sb/intel/bd82x6x: Add missing ID for PCI bridge ...................................................................... sb/intel/bd82x6x: Add missing ID for PCI bridge The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge" was missing. Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/41015/1 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 459ed46..757bdeb 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -58,8 +58,14 @@ .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x244e, /* Desktop */ + 0x2448, /* Mobile */ + 0 +}; + static const struct pci_driver pch_pci __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f Gerrit-Change-Number: 41015 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: [TEST] Enable link time optimization
by Jacob Garber (Code Review) 05 Jun '21

05 Jun '21

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40815 ) Change subject: [TEST] Enable link time optimization ...................................................................... [TEST] Enable link time optimization Enable LTO to shake out the bugs. Current problems: - GCC does not track symbol origins when using LTO, so it must be disabled for AGESA so it can be excluded from the illegal_globals check. - GCC segfaults when compiling ARMV7 - Most of the Google boards do not compile because of a missing reference to _watchdog_tombstone Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/Kconfig M src/vendorcode/amd/agesa/Makefile.inc 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40815/1 diff --git a/src/Kconfig b/src/Kconfig index e4821e8..375bca2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,7 +116,7 @@ config LTO bool "Use link time optimization (LTO)" - default n + default y depends on COMPILER_GCC help Compile with link time optimization. This can often decrease the diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..3e4a53c 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -14,6 +14,12 @@ AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing +# GCC currently does not track symbol origins when using LTO, so +# AGESA gets caught in the illegal_globals check. Disable for now. +ifeq ($(CONFIG_LTO),y) +AGESA_CFLAGS += -fno-lto +endif + CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/40815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37474d4adbf653729bb2e631a1ff812b4319c17a Gerrit-Change-Number: 40815 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2020