coreboot-gerrit September 2020

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Change in coreboot[master]: mb/google: Add ALIGNED flag to known sections that need alignment
by Hung-Te Lin (Code Review) 14 Jun '23

14 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37263 ) Change subject: mb/google: Add ALIGNED flag to known sections that need alignment ...................................................................... mb/google: Add ALIGNED flag to known sections that need alignment Update sections in chromeos.fmd that need 4k alignment: - RW_ELOG: By src/driver/elog/elog.c - RW_NVRAM: By src/security/vboot/vbnv_flash.c - {RO,RW}_DDR_TRAINING: By soc/qualcomm/common/qclib.c and mainboard/kukui/romstage.c Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/auron/chromeos.fmd M src/mainboard/google/beltino/chromeos.fmd M src/mainboard/google/butterfly/chromeos.fmd M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cyan/chromeos.fmd M src/mainboard/google/dragonegg/chromeos.fmd M src/mainboard/google/drallion/chromeos.fmd M src/mainboard/google/eve/chromeos.fmd M src/mainboard/google/fizz/chromeos.fmd M src/mainboard/google/foster/chromeos.fmd M src/mainboard/google/gale/chromeos.fmd M src/mainboard/google/glados/chromeos.fmd M src/mainboard/google/gru/chromeos.fmd M src/mainboard/google/hatch/chromeos-16MiB.fmd M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/jecht/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.fmd M src/mainboard/google/link/chromeos.fmd M src/mainboard/google/mistral/chromeos.fmd M src/mainboard/google/nyan/chromeos.fmd M src/mainboard/google/nyan_big/chromeos.fmd M src/mainboard/google/nyan_blaze/chromeos.fmd M src/mainboard/google/oak/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/parrot/chromeos.fmd M src/mainboard/google/poppy/chromeos.fmd M src/mainboard/google/rambi/chromeos.fmd M src/mainboard/google/reef/chromeos.fmd M src/mainboard/google/sarien/chromeos.fmd M src/mainboard/google/slippy/chromeos.fmd M src/mainboard/google/smaug/chromeos.fmd M src/mainboard/google/storm/chromeos.fmd M src/mainboard/google/stout/chromeos.fmd M src/mainboard/google/trogdor/chromeos.fmd M src/mainboard/google/veyron/chromeos.fmd M src/mainboard/google/veyron_mickey/chromeos.fmd M src/mainboard/google/veyron_rialto/chromeos.fmd 39 files changed, 70 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37263/1 diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/auron/chromeos.fmd +++ b/src/mainboard/google/auron/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/beltino/chromeos.fmd +++ b/src/mainboard/google/beltino/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/butterfly/chromeos.fmd +++ b/src/mainboard/google/butterfly/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index b0d2d99..109f61b 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd index 7bdeb17..a0bf5f2 100644 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 6e9170e..da90787 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -25,13 +25,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/fizz/chromeos.fmd +++ b/src/mainboard/google/fizz/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/foster/chromeos.fmd b/src/mainboard/google/foster/chromeos.fmd index f9a531c..5f47ba7 100644 --- a/src/mainboard/google/foster/chromeos.fmd +++ b/src/mainboard/google/foster/chromeos.fmd @@ -17,12 +17,12 @@ RW_SHARED@0x378000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x37c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x37c000 0x4000 RW_SECTION_B@0x380000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 RW_FWID_B@0x77f00 0x100 } RW_VPD(PRESERVE)@0x3f8000 0x4000 - RW_NVRAM(PRESERVE)@0x3fc000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3fc000 0x4000 } diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/gale/chromeos.fmd +++ b/src/mainboard/google/gale/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd index 9ba1bf7..0f516e2 100644 --- a/src/mainboard/google/glados/chromeos.fmd +++ b/src/mainboard/google/glados/chromeos.fmd @@ -15,13 +15,13 @@ RW_FWID_B@0x3effc0 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG(PRESERVE)@0x7f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x7f0000 0x4000 RW_SHARED@0x7f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x7f8000 0x2000 - RW_NVRAM(PRESERVE)@0x7fa000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x7fa000 0x6000 SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index 032f472..cada219 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,11 +20,11 @@ FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG(PRESERVE)@0x5d8000 0x1000 + RW_ELOG(PRESERVE,ALIGNED)@0x5d8000 0x1000 RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 } - RW_NVRAM(PRESERVE)@0x5f0000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0x5f0000 0x10000 RW_LEGACY(CBFS)@0x600000 0x200000 } diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 8880a4f..bbc666a 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } # RW_LEGACY needs to be minimum of 1MB RW_LEGACY(CBFS)@0x700000 0x100000 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 8368b0a..9e649d7 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -23,13 +23,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x30000 0x4000 RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3a000 0x6000 } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/jecht/chromeos.fmd +++ b/src/mainboard/google/jecht/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index d7d0a88..0888262 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -14,14 +14,14 @@ FW_MAIN_B(CBFS)@0x10000 0x20DFC0 RW_FWID_B@0x21DFC0 0x40 } - RW_ELOG(PRESERVE)@0x45D000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x45D000 0x4000 RW_SHARED@0x461000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x465000 0x2000 - RW_NVRAM(PRESERVE)@0x467000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x467000 0x5000 RW_UNUSED@0x46C000 0x14000 SMMSTORE(PRESERVE)@0x480000 0x20000 RW_LEGACY(CBFS)@0x4a0000 0x760000 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 098ce49..c75233e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select RTC + select FMD_GENPARSER select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 2635854..9456393 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -28,9 +28,9 @@ } RW_MISC 36K { RW_VPD(PRESERVE) 16K # At least 8K. - RW_NVRAM(PRESERVE) 8K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + RW_NVRAM(PRESERVE,ALIGNED) 8K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K # Only ELOG_SIZE needed. } RW_SECTION_B 1500K { VBLOCK_B 8K diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd index 3841445..cf7f76d 100644 --- a/src/mainboard/google/link/chromeos.fmd +++ b/src/mainboard/google/link/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 4d5f666..d2d92e6 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -23,13 +23,13 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 128K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/nyan/chromeos.fmd b/src/mainboard/google/nyan/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan/chromeos.fmd +++ b/src/mainboard/google/nyan/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_big/chromeos.fmd b/src/mainboard/google/nyan_big/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_big/chromeos.fmd +++ b/src/mainboard/google/nyan_big/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_blaze/chromeos.fmd b/src/mainboard/google/nyan_blaze/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.fmd +++ b/src/mainboard/google/nyan_blaze/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/oak/chromeos.fmd b/src/mainboard/google/oak/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/oak/chromeos.fmd +++ b/src/mainboard/google/oak/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..28c1a5f 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -19,13 +19,13 @@ RW_VAR_MRC_CACHE@0x20000 0x1000 } } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd index 6752888..625a30e 100644 --- a/src/mainboard/google/parrot/chromeos.fmd +++ b/src/mainboard/google/parrot/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/rambi/chromeos.fmd +++ b/src/mainboard/google/rambi/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 87eb4e7..72d8df1 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -17,13 +17,13 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 65a915a..b63149f4 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -26,13 +26,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x1800000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/slippy/chromeos.fmd +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/smaug/chromeos.fmd b/src/mainboard/google/smaug/chromeos.fmd index 4b1ba19..cb5ec8e 100644 --- a/src/mainboard/google/smaug/chromeos.fmd +++ b/src/mainboard/google/smaug/chromeos.fmd @@ -21,7 +21,7 @@ } RW_SHARED@0xf00000 0x4000 SHARED_DATA@0xf04000 0x4000 - RW_ELOG(PRESERVE)@0xf08000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0xf08000 0x4000 RW_VPD(PRESERVE)@0xf0c000 0x8000 - RW_NVRAM(PRESERVE)@0xf20000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0xf20000 0x10000 } diff --git a/src/mainboard/google/storm/chromeos.fmd b/src/mainboard/google/storm/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/storm/chromeos.fmd +++ b/src/mainboard/google/storm/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/stout/chromeos.fmd +++ b/src/mainboard/google/stout/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 9af3d51..27ff291 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -23,16 +23,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/veyron/chromeos.fmd b/src/mainboard/google/veyron/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/veyron/chromeos.fmd +++ b/src/mainboard/google/veyron/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_mickey/chromeos.fmd b/src/mainboard/google/veyron_mickey/chromeos.fmd index 76ab2c3..da8bbc5 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.fmd +++ b/src/mainboard/google/veyron_mickey/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_rialto/chromeos.fmd b/src/mainboard/google/veyron_rialto/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.fmd +++ b/src/mainboard/google/veyron_rialto/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/37263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Gerrit-Change-Number: 37263 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 32

Change in vboot[master]: [Debug] Disable Wimplicit-fallthrough
by Selma Bensaid (Code Review) 10 Jun '23

10 Jun '23

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/vboot/+/38910 to review the following change. Change subject: [Debug] Disable Wimplicit-fallthrough ...................................................................... [Debug] Disable Wimplicit-fallthrough Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.corp-partner.google.com> Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/10/38910/1 diff --git a/Makefile b/Makefile index 0539e8d..62c0307 100644 --- a/Makefile +++ b/Makefile @@ -142,7 +142,7 @@ -Wundef -Wmissing-prototypes -Wno-trigraphs -Wredundant-decls -Wshadow \ -Wwrite-strings -Wstrict-aliasing -Wdate-time -Wno-unknown-warning \ -Wno-address-of-packed-member -ffunction-sections -fdata-sections \ - -Wimplicit-fallthrough ${DEBUG_FLAGS} + ${DEBUG_FLAGS} # Note: FIRMWARE_ARCH is defined by the Chromium OS ebuild. ifeq (${FIRMWARE_ARCH},arm) -- To view, visit https://review.coreboot.org/c/vboot/+/38910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: Ib50af965b30509ba96b01c937474a9a064836e1f Gerrit-Change-Number: 38910 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in ...vboot[master]: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/32679 Change subject: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR ...................................................................... vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR vboot fails to compile with the error "error: comparison is always false due to limited range of data type [-Werror=type-limits]" since struct_version_minor is uint16_t and can never be less than VB2_SHARED_DATA_VERSION_MINOR (0) Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 --- M firmware/2lib/2misc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/79/32679/1 diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 95cbae3..195a0f9 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -128,7 +128,7 @@ return VB2_ERROR_SHARED_DATA_MAGIC; if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || - sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) + sd->struct_version_minor != VB2_SHARED_DATA_VERSION_MINOR) return VB2_ERROR_SHARED_DATA_VERSION; return VB2_SUCCESS; -- To view, visit https://review.coreboot.org/c/vboot/+/32679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 Gerrit-Change-Number: 32679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build
by Pablo Moyano (Code Review) 10 Jun '23

10 Jun '23

Pablo Moyano has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34105 ) Change subject: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build ...................................................................... payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build At some point between Grub 2.02 and 2.04, something was added and it refuses to build without it. Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Signed-off-by: Pablo <42.pablo.ms(a)gmail.com> --- M payloads/external/GRUB2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34105/1 diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 31c4066..b036aeb 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -28,7 +28,7 @@ echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./autogen.sh + cd grub2 && ./bootstrap && ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/34105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Gerrit-Change-Number: 34105 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41852 ) Change subject: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler ...................................................................... sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler The xHCI S3/S4 quirk is only needed on PPT Revision A0. Fix always false condition by adding the missing read32 function call. Untested. Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/smihandler.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/41852/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index cddb4cf..fbc7b81 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -100,6 +100,9 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: + if (!pch_silicon_supported(PCH_TYPE_PPT, PCH_STEP_A0)) + break; + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 &= ~0x03UL; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); @@ -112,14 +115,13 @@ PCI_BASE_ADDRESS_0) & ~0xFUL; if (!smm_validate_pointer((void *)(uintptr_t)xhci_bar)) { - /* FIXME: This looks broken */ - if ((xhci_bar + 0x4C0) & 1) + if (read32(xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4D0) & 1) + if (read32(xhci_bar + 0x4D0) & 1) pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4E0) & 1) + if (read32(xhci_bar + 0x4E0) & 1) pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4F0) & 1) + if (read32(xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); } reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); -- To view, visit https://review.coreboot.org/c/coreboot/+/41852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57 Gerrit-Change-Number: 41852 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: soc/amd/common: Use ACPIMMIO_BASE() in ASL
by Kyösti Mälkki (Code Review) 10 Jun '23

10 Jun '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42944 ) Change subject: soc/amd/common: Use ACPIMMIO_BASE() in ASL ...................................................................... soc/amd/common: Use ACPIMMIO_BASE() in ASL Change-Id: Iff6bdbe5a12f1a47c7ce348a628e0b67aac37c7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/stoneyridge/acpi/sb_fch.asl 5 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42944/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 837678a..f61f6a0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -22,7 +22,7 @@ Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Return (RBUF) diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index f73340c..b60fba91 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -6,7 +6,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) + Return (Add(Multiply(Arg0, 4), ACPIMMIO_BASE(GPIO0))) } /* Read pin control dword */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index e5caefc..e8f4625 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -94,12 +94,6 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#ifdef __ACPI__ -/* ASL MemoryFixed32() fails if these are additions. */ -#define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#endif - #define ACPIMMIO_SM_PCI_BANK 0x0000 #define ACPIMMIO_GPIO_100_BANK 0x0100 #define ACPIMMIO_SMI_BANK 0x0200 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 007df8d..d283402 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) }) } Else { Return (Local0) @@ -396,7 +396,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index c999b67..9adb82a 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -30,7 +30,7 @@ { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) { 7 } - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) }) Method (_STA, 0x0, NotSerialized) @@ -132,7 +132,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Method (_STA, 0x0, NotSerialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6bdbe5a12f1a47c7ce348a628e0b67aac37c7c Gerrit-Change-Number: 42944 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pciexp: retrain PCIe link at lower speed if no link
by Jonathan Kollasch (Code Review) 10 Jun '23

10 Jun '23

Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42683 ) Change subject: pciexp: retrain PCIe link at lower speed if no link ...................................................................... pciexp: retrain PCIe link at lower speed if no link Needed for PCIe x4 dual-port Marvell NIC (sky2) on Sandy/Ivy Bridge and 6-series PCH (if not other chipsets), where the link will not come up at 5GT/s (or 8GT/s?), but will if explicitly trained at 2.5GT/s. Change-Id: I7ba15f7c13463356c6417f41b44d045aacfde4cc --- M src/device/pciexp_device.c M src/include/device/pci_def.h 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/42683/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f04d865..aeb44f7 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -112,6 +112,38 @@ } } +static void pciexp_limit_speed(struct device *dev, unsigned int cap) +{ + u16 x, y; + + x = pci_read_config16(dev, cap + PCI_EXP_FLAGS); + + /* is this new enough to support LNKCTL2? */ + if ((x & PCI_EXP_FLAGS_VERS) <= 1) + return; + + y = pci_read_config16(dev, cap + PCI_EXP_LNKCTL2); + y &= PCI_EXP_LNKCTL2_TLS; + + do { + /* link up? */ + x = pci_read_config16(dev, cap + PCI_EXP_LNKSTA); + x = (x & PCI_EXP_LNKSTA_LW) >> 4; + if (x > 0) + return; + + printk(BIOS_INFO, "%s: link down; retraining at target link speed %u\n", + dev_path(dev), y); + + x = pci_read_config16(dev, cap + PCI_EXP_LNKCTL2); + x &= ~PCI_EXP_LNKCTL2_TLS; + x |= y & PCI_EXP_LNKCTL2_TLS; + pci_write_config16(dev, cap + PCI_EXP_LNKCTL2, x); + + pciexp_retrain_link(dev, cap); + } while (--y > 0); +} + static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap) { /* check if per port clk req is supported in device */ @@ -488,6 +520,12 @@ void pciexp_scan_bridge(struct device *dev) { + unsigned int cap; + + cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (cap) + pciexp_limit_speed(dev, cap); + do_pci_scan_bridge(dev, pciexp_scan_bus); pciexp_enable_ltr(dev); } diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 07ba4a2..b351e42 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -432,6 +432,7 @@ #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LW 0x3F0 /* Link Width */ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ @@ -446,6 +447,8 @@ #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTSTA 32 /* Root Status */ +#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +#define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) -- To view, visit https://review.coreboot.org/c/coreboot/+/42683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ba15f7c13463356c6417f41b44d045aacfde4cc Gerrit-Change-Number: 42683 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41024 ) Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support ...................................................................... soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support Refer to https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilico… Include TCSS TBT PCIE Root Port 0/1/2/3 inside \_SB.PCIx (where x depends on PCI multiple segment support). Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/tigerlake/acpi/tcss.asl 3 files changed, 29 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41024/1 diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index a87c743..5997ccc 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -31,8 +31,8 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> - #include <soc/intel/tigerlake/acpi/tcss.asl> } + #include <soc/intel/tigerlake/acpi/tcss.asl> /* Mainboard hooks */ #include "mainboard.asl" } diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index c66e972..2576596 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -27,8 +27,8 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> - #include <soc/intel/tigerlake/acpi/tcss.asl> } + #include <soc/intel/tigerlake/acpi/tcss.asl> } #if CONFIG(CHROMEOS) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9f03aa9..86536bc 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -19,6 +19,10 @@ #define TCSS_XDCI 5 #define TCSS_DMA0 6 #define TCSS_DMA1 7 +#define TCSS_TBT_PCIE1_RP0 8 +#define TCSS_TBT_PCIE1_RP1 9 +#define TCSS_TBT_PCIE1_RP2 10 +#define TCSS_TBT_PCIE1_RP3 11 /* * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE @@ -681,7 +685,13 @@ } #include "tcss_dma.asl" } - +} +#if CONFIG_PCI_SEGMENT_GROUPS > 1 +Scope (\_SB.PCI1) +#else +Scope (\_SB.PCI0) +#endif +{ /* * TCSS PCIE Root Port #00 */ @@ -692,8 +702,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP0) +#else Name (DCPM, TCSS_TBT_PCIE0_RP0) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -717,8 +730,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP1) +#else Name (DCPM, TCSS_TBT_PCIE0_RP1) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -742,8 +758,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP2) +#else Name (DCPM, TCSS_TBT_PCIE0_RP2) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -767,8 +786,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP3) +#else Name (DCPM, TCSS_TBT_PCIE0_RP3) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) -- To view, visit https://review.coreboot.org/c/coreboot/+/41024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Gerrit-Change-Number: 41024 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/dg41wv: Inherit the subsystemid
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30470 Change subject: mb/intel/dg41wv: Inherit the subsystemid ...................................................................... mb/intel/dg41wv: Inherit the subsystemid Don't reprogram the same subsystemid for each PCI device. Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg41wv/devicetree.cb 1 file changed, 23 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30470/1 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad95..da91ea2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -24,14 +24,10 @@ end end device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x8086 0x5756 - end + subsystemid 0x8086 0x5756 inherit + device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG - device pci 2.0 on # Integrated graphics controller - subsystemid 0x8086 0x5756 - end + device pci 2.0 on end # Integrated graphics controller chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" @@ -66,39 +62,24 @@ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" - device pci 1b.0 on # Audio - subsystemid 0x8086 0x5756 + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2: NIC + device pci 00.0 on end end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2: NIC - device pci 00.0 on - subsystemid 0x8086 0x5756 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.1 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.2 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.3 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.7 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio Controller - device pci 1e.3 off end # AC'97 Modem Controller - device pci 1f.0 on # ISA bridge - subsystemid 0x8086 0x5756 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio Controller + device pci 1e.3 off end # AC'97 Modem Controller + device pci 1f.0 on # ISA bridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy # global @@ -155,12 +136,9 @@ end end device pci 1f.1 off end # PATA/IDE - device pci 1f.2 on # SATA - subsystemid 0x8086 0x5756 - end - device pci 1f.3 on # SMbus - subsystemid 0x8086 0x5756 - chip drivers/i2c/ck505 + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -173,7 +151,6 @@ 0x06, 0x00, 0xea }" device i2c 69 on end end - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Gerrit-Change-Number: 30470 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: force --divide for iPXE default build
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35820 ) Change subject: force --divide for iPXE default build ...................................................................... force --divide for iPXE default build Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35820/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 0c071fa..7005016 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -72,7 +72,7 @@ $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom WORKAROUND_ASFLAGS="--divide" endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) -- To view, visit https://review.coreboot.org/c/coreboot/+/35820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Gerrit-Change-Number: 35820 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

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