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Change in coreboot[master]: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
by Julius Werner (Code Review) 12 Dec '20

12 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39306 to review the following change. Change subject: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() ...................................................................... cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f --- M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/cbfs.c M src/northbridge/intel/haswell/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/quark/romstage/romstage.c 6 files changed, 60 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39306/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 4789b15..1f9abb5 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -60,36 +60,28 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +static struct cmos_option_table *get_cmos_layout(struct region_device *rdev) { - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; + MAYBE_STATIC_BSS struct cmos_option_table ct = NULL; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the 'COREBOOT' region for now. + * Support only one CMOS layout in the RO CBFS for now. */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; + if (!ct) + ct = cbfs_ro_map("cmos_layout.bin", NULL); + if (!ct) + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return ct; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -97,16 +89,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -119,19 +104,15 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); +} + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); +} return CB_SUCCESS; } @@ -179,7 +160,6 @@ enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -188,16 +168,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -210,7 +183,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -219,18 +191,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index cc61b16..8cd5713 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -36,9 +36,12 @@ NOTE: Since this may return a direct pointer to memory-mapped hardware, compressed files are NOT transparently decompressed (unlike cbfs_load()). */ void *cbfs_map(const char *name, size_t *size); -/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap - mappings in strict LIFO order where possible, since mapping backends often - don't support more complicated cases. */ +/* Like cbfs_map(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +void *cbfs_ro_map(const char *name, size_t *size); +/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in + strict LIFO order where possible, since mapping backends often don't support + more complicated cases. */ int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -47,6 +50,9 @@ success or 0 on error. File will get decompressed as necessary. Same decompression requirements as cbfs_load_and_decompress(). */ size_t cbfs_load(const char *name, void *buf, size_t buf_size); +/* Like cbfs_load(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c3660aa..ba50c34 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,9 +79,9 @@ return 0; } -void *cbfs_map(const char *name, size_t *size) +static void *_cbfs_map(const char *name, size_t *size, bool force_ro) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); union cbfs_mdata mdata; size_t data_offset; @@ -96,6 +96,16 @@ return rdev_mmap(&cbd->rdev, data_offset, data_size); } +void *cbfs_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, false); +} + +void *cbfs_ro_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, true); +} + int cbfs_unmap(void *mapping) { /* This works because munmap() only works on the root rdev and never @@ -215,7 +225,8 @@ return prog_entry(&stage); } -size_t cbfs_load(const char *name, void *buf, size_t buf_size) +static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, + bool force_ro) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); union cbfs_mdata mdata; @@ -238,6 +249,16 @@ compression); } +size_t cbfs_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, false); +} + +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, true); +} + size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) { struct cbfs_stage stage; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..00211bd 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -118,8 +118,6 @@ void sdram_initialize(struct pei_data *pei_data) { unsigned long entry; - uint32_t type = CBFS_TYPE_MRC; - struct cbfsf f; printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); @@ -144,12 +142,11 @@ /* * Locate and call UEFI System Agent binary. The binary needs to be at * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * COREBOOT fmap region. We don't care about leaking the mapping. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + entry = (unsigned long)cbfs_ro_map("mrc.bin", NULL); + if (!entry) die("mrc.bin not found!"); - /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; asm volatile ( diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f..bcf7148 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -43,8 +43,6 @@ struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; - struct cbfsf f; - uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -76,15 +74,10 @@ pei_data->saved_data_size = 0; } - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) - die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } + entry = cbfs_ro_map("mrc.bin", NULL); + if (entry == NULL) + die("mrc.bin not found!"); printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ac580e..3e08663 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -63,29 +63,16 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; size_t fsize; void *rmu_data; - uint32_t type; /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) + rmu_data = cbfs_ro_map("rmu.bin", &fsize); + if (!rmu_data) return NULL; - /* Get the file size */ - fsize = region_device_sz(&fh.data); if (rmu_file_len != NULL) *rmu_file_len = fsize; - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); return rmu_data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Gerrit-Change-Number: 39306 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: sb/intel/bd82x6x: Make me_common.c a compilation unit
by Angel Pons (Code Review) 10 Dec '20

10 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42019 ) Change subject: sb/intel/bd82x6x: Make me_common.c a compilation unit ...................................................................... sb/intel/bd82x6x: Make me_common.c a compilation unit We need to make most things non-static so that the code builds. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 5 files changed, 47 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42019/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 9e34e96..cf9bf50 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c +ramstage-y += me_common.c ramstage-y += smbus.c ramstage-y += ../common/pciehp.c @@ -24,7 +25,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 515f984..d2a3480 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) { diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 5aaf661..a55a1f2 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -221,6 +221,34 @@ ME_FIRMWARE_UPDATE_BIOS_PATH, } me_bios_path; +/* Defined in me_common.c for both ramstage and smm */ +const char *const me_get_bios_path_string(int path); + +void mei_read_dword_ptr(void *ptr, int offset); +void mei_write_dword_ptr(void *ptr, int offset); + +#ifndef __SIMPLE_DEVICE__ +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); +#endif + +void read_host_csr(struct mei_csr *csr); +void write_host_csr(struct mei_csr *csr); + +void read_me_csr(struct mei_csr *csr); + +void write_cb(u32 dword); +u32 read_cb(void); + +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes); + +int mkhi_end_of_post(void); +void update_mei_base_address(void); +bool is_mei_base_address_valid(void); +int intel_mei_setup(struct device *dev); +int intel_me_extend_valid(struct device *dev); +void intel_me_hide(struct device *dev); + /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index fcf4dd3..1a331e9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 790b870..83e7fe6 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -25,7 +25,7 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static inline const char *const me_get_bios_path_string(int path) +const char *const me_get_bios_path_string(int path) { return me_bios_path_values[path]; } @@ -70,14 +70,14 @@ * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset / sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } -static inline void mei_write_dword_ptr(void *ptr, int offset) +void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); @@ -86,7 +86,7 @@ } #ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -94,28 +94,28 @@ } #endif -static inline void read_host_csr(struct mei_csr *csr) +void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); } -static inline void write_host_csr(struct mei_csr *csr) +void write_host_csr(struct mei_csr *csr) { mei_write_dword_ptr(csr, MEI_H_CSR); } -static inline void read_me_csr(struct mei_csr *csr) +void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); } -static inline void write_cb(u32 dword) +void write_cb(u32 dword) { write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } -static inline u32 read_cb(void) +u32 read_cb(void) { u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); @@ -310,8 +310,8 @@ return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -321,7 +321,7 @@ } /* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) +int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -351,12 +351,12 @@ #ifdef __SIMPLE_DEVICE__ -static inline void update_mei_base_address(void) +void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -static inline bool is_mei_base_address_valid(void) +bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } @@ -364,7 +364,7 @@ #else /* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) +int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -391,7 +391,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) +int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -438,7 +438,7 @@ } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) +void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/42019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Gerrit-Change-Number: 42019 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: cbfs: Simplify load/map API names, remove type arguments
by Julius Werner (Code Review) 08 Dec '20

08 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39304 to review the following change. Change subject: cbfs: Simplify load/map API names, remove type arguments ...................................................................... cbfs: Simplify load/map API names, remove type arguments This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e --- M src/arch/x86/acpi.c M src/arch/x86/bootblock_normal.c M src/cpu/amd/pi/00730F01/microcode_fam16h.c M src/cpu/intel/microcode/microcode.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/state_machine.c M src/drivers/intel/fsp1_1/logo.c M src/drivers/intel/fsp2_0/logo.c M src/drivers/intel/gma/opregion.c M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/bootsplash.c M src/lib/cbfs.c M src/lib/coreboot_table.c M src/lib/spd_bin.c M src/mainboard/apple/macbookair4_2/early_init.c M src/mainboard/google/auron/variants/auron_paine/spd/spd.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c M src/mainboard/google/auron/variants/buddy/variant.c M src/mainboard/google/auron/variants/gandof/spd/spd.c M src/mainboard/google/auron/variants/lulu/spd/spd.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/beltino/lan.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/dragonegg/romstage_fsp_params.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/lan.c M src/mainboard/google/kahlee/variants/baseboard/mainboard.c M src/mainboard/google/kahlee/variants/treeya/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/kukui/sdram_configs.c M src/mainboard/google/link/early_init.c M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/rambi/romstage.c M src/mainboard/google/rambi/variants/ninja/lan.c M src/mainboard/google/rambi/variants/sumo/lan.c M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c M src/mainboard/intel/harcuvar/spd/spd.c M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/lenovo/s230u/early_init.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/sifive/hifive-unleashed/fixup_fdt.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/security/intel/stm/StmPlatformSmm.c M src/security/vboot/ec_sync.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/common/mma.c M src/soc/intel/denverton_ns/chip.c M src/soc/mediatek/mt8183/spm.c M src/soc/mediatek/mt8183/sspm.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/sc7180/qclib.c M src/soc/qualcomm/sdm845/qclib.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c M src/vendorcode/google/chromeos/sar.c M src/vendorcode/siemens/hwilib/hwilib.c 70 files changed, 112 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39304/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index b9e896f..d96edb1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1308,9 +1308,7 @@ return fw; } - dsdt_file = cbfs_boot_map_with_leak( - CONFIG_CBFS_PREFIX "/dsdt.aml", - CBFS_TYPE_RAW, &dsdt_size); + dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size); if (!dsdt_file) { printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); return current; @@ -1323,8 +1321,7 @@ return current; } - slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic", - CBFS_TYPE_RAW, &slic_size); + slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size); if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index b6b31af..f92237e 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -30,7 +30,7 @@ const char *boot_candidate; size_t stages_len; - boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len); + boot_candidate = cbfs_map("coreboot-stages", &stages_len); if (!boot_candidate) boot_candidate = default_filenames; diff --git a/src/cpu/amd/pi/00730F01/microcode_fam16h.c b/src/cpu/amd/pi/00730F01/microcode_fam16h.c index 1f1dbd9..88546f5 100644 --- a/src/cpu/amd/pi/00730F01/microcode_fam16h.c +++ b/src/cpu/amd/pi/00730F01/microcode_fam16h.c @@ -120,9 +120,7 @@ "Skipping microcode patch!\n"); return; } - ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, - &ucode_len); + ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len); if (!ucode) { printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. " "Skipping updates.\n"); diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 90138be..ae17d71 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -137,9 +137,7 @@ unsigned int x86_model, x86_family; msr_t msr; - ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE, - &microcode_len); + ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len); if (ucode_updates == NULL) return NULL; diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index bce90d9..e9f1689 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -135,9 +135,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = cbfs_map("pci"CONFIG_VGA_BIOS_ID".rom", NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index 1678f84..7297ba4 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -42,8 +42,7 @@ const void *agesa, *image; size_t file_size; - agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME, - CBFS_TYPE_RAW, &file_size); + agesa = cbfs_map((const char *)CONFIG_AGESA_CBFS_NAME, &file_size); if (agesa == NULL) return; diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c index b00406d..5dd8202 100644 --- a/src/drivers/intel/fsp1_1/logo.c +++ b/src/drivers/intel/fsp1_1/logo.c @@ -24,8 +24,8 @@ if (logo_entry) { logo_buffer = cbmem_entry_start(logo_entry); if (logo_buffer) { - *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, - 1 * MiB, CBFS_TYPE_RAW); + *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, + 1 * MiB); if (*logo_size) *logo_ptr = (UINT32)logo_buffer; } diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c index 1a9152f..3c95fef 100644 --- a/src/drivers/intel/fsp2_0/logo.c +++ b/src/drivers/intel/fsp2_0/logo.c @@ -24,8 +24,8 @@ if (logo_entry) { logo_buffer = cbmem_entry_start(logo_entry); if (logo_buffer) { - *logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer, - 1 * MiB, CBFS_TYPE_RAW); + *logo_size = cbfs_load("logo.bmp", (void *)logo_buffer, + 1 * MiB); if (*logo_size) *logo_ptr = (UINT32)logo_buffer; } diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..8cb7fcd 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -46,8 +46,7 @@ const char *filename = mainboard_vbt_filename(); - size_t file_size = cbfs_boot_load_file(filename, - vbt_data, sizeof(vbt_data), CBFS_TYPE_RAW); + size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data)); if (file_size == 0) return NULL; diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index bb697df..4789b15 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -244,9 +244,7 @@ size_t length = 128; size_t i; - const unsigned char *cmos_default = - cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); + const unsigned char *cmos_default = cbfs_map("cmos.default", &length); if (!cmos_default) return; diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 82c92d7..cc61b16 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -31,19 +31,22 @@ void *cbfs_boot_load_stage_by_name(const char *name); /* Locate file by name and optional type. Return 0 on success. < 0 on error. */ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); -/* Map file into memory leaking the mapping. Only should be used when - * leaking mappings are a no-op. Returns NULL on error, else returns - * the mapping and sets the size of the file. */ -void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); +/* Map file into memory, returning a pointer to the mapping or NULL on error. + If |size| is not NULL, it will pass out the size of the mapped file. + NOTE: Since this may return a direct pointer to memory-mapped hardware, + compressed files are NOT transparently decompressed (unlike cbfs_load()). */ +void *cbfs_map(const char *name, size_t *size); +/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap + mappings in strict LIFO order where possible, since mapping backends often + don't support more complicated cases. */ +int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type); -/* Load an arbitrary type file from CBFS into a buffer. Returns amount of - * loaded bytes on success or 0 on error. File will get decompressed as - * necessary. Same decompression requirements as - * cbfs_load_and_decompress(). */ -size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, - uint32_t type); +/* Load a file from CBFS into a buffer. Returns amount of loaded bytes on + success or 0 on error. File will get decompressed as necessary. Same + decompression requirements as cbfs_load_and_decompress(). */ +size_t cbfs_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 8364afa..3f96907 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -29,8 +29,7 @@ printk(BIOS_INFO, "Setting up bootsplash in %dx%d@%d\n", x_resolution, y_resolution, fb_resolution); struct jpeg_decdata *decdata; - unsigned char *jpeg = - cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL); + unsigned char *jpeg = cbfs_map("bootsplash.jpg", NULL); if (!jpeg) { printk(BIOS_ERR, "Could not find bootsplash.jpg\n"); return; @@ -44,6 +43,7 @@ decdata = malloc(sizeof(*decdata)); int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution, decdata); + cbfs_unmap(jpeg); if (ret != 0) { printk(BIOS_ERR, "Bootsplash could not be decoded. jpeg_decode returned %d.\n", ret); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 39db97a..bece4d0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,12 +79,12 @@ return 0; } -void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) +void *cbfs_map(const char *name, size_t *size) { struct cbfsf fh; size_t fsize; - if (cbfs_boot_locate(&fh, name, &type)) + if (cbfs_boot_locate(&fh, name, NULL)) return NULL; fsize = region_device_sz(&fh.data); @@ -95,6 +95,13 @@ return rdev_mmap(&fh.data, 0, fsize); } +int cbfs_unmap(void *mapping) +{ + /* This works because munmap() only works on the root rdev and never + cares about which chained subregion something was mapped from. */ + return rdev_munmap(boot_device_ro(), mapping); +} + int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, const char *name, uint32_t *type) { @@ -187,16 +194,15 @@ tohex16(vendor, name + 3); tohex16(device, name + 8); - return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); + return cbfs_map(name, NULL); } void *cbfs_boot_load_stage_by_name(const char *name) { struct cbfsf fh; struct prog stage = PROG_INIT(PROG_UNKNOWN, name); - uint32_t type = CBFS_TYPE_STAGE; - if (cbfs_boot_locate(&fh, name, &type)) + if (cbfs_boot_locate(&fh, name, NULL)) return NULL; /* Chain data portion in the prog. */ @@ -208,14 +214,13 @@ return prog_entry(&stage); } -size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size, - uint32_t type) +size_t cbfs_load(const char *name, void *buf, size_t buf_size) { struct cbfsf fh; uint32_t compression_algo; size_t decompressed_size; - if (cbfs_boot_locate(&fh, name, &type) < 0) + if (cbfs_boot_locate(&fh, name, NULL) < 0) return 0; if (cbfsf_decompression_info(&fh, &compression_algo, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 91e0247..78ecb5a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -494,8 +494,7 @@ #if CONFIG(USE_OPTION_TABLE) { struct cmos_option_table *option_table = - cbfs_boot_map_with_leak("cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + cbfs_map("cmos_layout.bin", NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 9e625b5..41588d7 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -209,8 +209,7 @@ size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); if (spd_file_len < min_len) @@ -220,6 +219,7 @@ memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + cbfs_unmap(spd_file); u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index 29a2977..69e26f0 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -39,8 +39,7 @@ { void *spd_file; size_t spd_file_len = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (spd_file && spd_file_len >= 1024) { int i; for (i = 0; i < 4; i++) diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 2991d15..f08e0a4 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 2991d15..f08e0a4 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c index 4e05711..31f4cc1 100644 --- a/src/mainboard/google/auron/variants/buddy/variant.c +++ b/src/mainboard/google/auron/variants/buddy/variant.c @@ -140,9 +140,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 2991d15..f08e0a4 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index bd76947..94f9346 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -106,7 +106,7 @@ spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index ffb90f9..6ff6d77 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -101,7 +101,7 @@ spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c index 1c38e45..8e8b44d 100644 --- a/src/mainboard/google/beltino/lan.c +++ b/src/mainboard/google/beltino/lan.c @@ -123,9 +123,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index eb4d15b..9bbb700 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -195,8 +195,7 @@ } } } else { - vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, - &search_length); + vpd_file = cbfs_map("vpd.bin", &search_length); if (vpd_file) { search_address = (unsigned long)vpd_file; } else { diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 8dd4366..e08234a 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -49,8 +49,7 @@ int spd_index = 0; /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index f1f5143..e6573ad 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -32,8 +32,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map(spd_bin, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index fca670c..a03d077 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -96,8 +96,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 324d3be..68d840d 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -93,8 +93,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 5e9e15f..25719bc 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -66,8 +66,7 @@ if (ramcode >= ARRAY_SIZE(sdram_configs) || !snprintf(config_file, sizeof(config_file), "%s-%d", sdram_configs[ramcode], get_sdram_target_mhz()) || - (cbfs_boot_load_file(config_file, &params, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params))) + (cbfs_load(config_file, &params, sizeof(params)) != sizeof(params))) die("Cannot load SDRAM parameter file!"); return &params; diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index bd08b09..fde59a7 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -123,9 +123,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 69b9b40..2bada6e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -103,9 +103,7 @@ if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kahlee/variants/treeya/mainboard.c b/src/mainboard/google/kahlee/variants/treeya/mainboard.c index cd42b56..9639977 100644 --- a/src/mainboard/google/kahlee/variants/treeya/mainboard.c +++ b/src/mainboard/google/kahlee/variants/treeya/mainboard.c @@ -115,9 +115,7 @@ if (manuf) return manuf; - if (cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data) - 1, - CBFS_TYPE_RAW)) + if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) manuf = &oem_bin_data[0]; else manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 844496d..c64bc98 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -117,8 +117,7 @@ return NULL; snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); - if (cbfs_boot_load_file(cbfs_name, buffer.raw, sizeof(buffer), - CBFS_TYPE_STRUCT)) + if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) desc->s = &buffer.s; else printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); diff --git a/src/mainboard/google/kukui/sdram_configs.c b/src/mainboard/google/kukui/sdram_configs.c index b6277ea..8ce455d 100644 --- a/src/mainboard/google/kukui/sdram_configs.c +++ b/src/mainboard/google/kukui/sdram_configs.c @@ -36,8 +36,8 @@ uint32_t ramcode = ram_code(); if (ramcode >= ARRAY_SIZE(sdram_configs) || - cbfs_boot_load_file(sdram_configs[ramcode], &params, sizeof(params), - CBFS_TYPE_STRUCT) != sizeof(params)) + cbfs_load(sdram_configs[ramcode], &params, sizeof(params)) + != sizeof(params)) die("Cannot load SDRAM parameter file!"); return &params; diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 7d1c177..5fd56cf 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -81,8 +81,7 @@ int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 9de1602..08d21f6 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -125,8 +125,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map(spd_bin, &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 6d54e17..71cade7 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -167,9 +167,8 @@ if (oem_id == OEM_UNKNOWN) return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; - oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, - sizeof(oem_bin_data), - CBFS_TYPE_RAW); + oem_data_size = cbfs_load("oem.bin", oem_bin_data, + sizeof(oem_bin_data)); while ((curr < oem_data_size) && ((oem_data_size - curr) >= sizeof(*oem_entry))) { diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index f74d77d..542d996 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -62,8 +62,7 @@ void *spd_file; size_t spd_fsize; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_fsize); + spd_file = cbfs_map("spd.bin", &spd_fsize); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c index 5b220e0..bd22fe9 100644 --- a/src/mainboard/google/rambi/variants/ninja/lan.c +++ b/src/mainboard/google/rambi/variants/ninja/lan.c @@ -122,9 +122,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c index d6cd580..27e5c9f 100644 --- a/src/mainboard/google/rambi/variants/sumo/lan.c +++ b/src/mainboard/google/rambi/variants/sumo/lan.c @@ -122,9 +122,7 @@ search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_boot_map_with_leak("vpd.bin", - CBFS_TYPE_RAW, - &search_length); + search_address = cbfs_map("vpd.bin", &search_length); } if (search_address == NULL) diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index c193d20..11e1d59 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -77,8 +77,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 9e9cf73..5ea13f4 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -76,8 +76,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 8adf4b2..c67ffef 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -79,8 +79,7 @@ uint32_t board_version = PEPPY_BOARD_VERSION_PROTO; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 651d8b1..cdc8f90 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -77,8 +77,7 @@ size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c index 29be074..9ef3174 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/early_init.c @@ -55,8 +55,7 @@ { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index 61bf2e5..75a95c4 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -30,8 +30,7 @@ spd_index = 0; - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 2fe4596..bab5f53 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -82,8 +82,7 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index a0fc2ec..5222f99 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -84,8 +84,7 @@ spd_index, mainboard_spd_names[spd_index]); /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) die("SPD data not found."); diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 7da2c55..2db7fc6 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -44,8 +44,7 @@ { /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; - void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + void *spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file || spd_file_len < sizeof(spd_raw_data)) die("SPD data for C1S0 not found."); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 859148a..a56d024 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -50,8 +50,7 @@ size_t spd_file_len; printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_file = cbfs_map("spd.bin", &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 0249c3b..add76b5 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -119,8 +119,7 @@ break; } - spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); + spd_data = cbfs_map("spd.bin", &spd_file_len); if (!spd_data) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c index 3d43181..6ef7c1c 100644 --- a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c +++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c @@ -86,7 +86,7 @@ struct device_tree *tree; /* load flat dt from cbfs */ - fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL); + fdt_rom = cbfs_map("fallback/DTB", NULL); if (fdt_rom == NULL) { printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 8daa9aa..a0753aa 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -220,7 +220,7 @@ pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + entry = cbfs_map("mrc.bin", NULL); if (entry) { int rv; rv = entry (pei_data); diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 45db0e0..6eae9b0 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -49,8 +49,7 @@ memset((void *)mseg_base, 0, CONFIG_MSEG_SIZE); // clear the mseg - stm_image_size = cbfs_boot_load_file("stm.bin", mseg_base, - stm_buffer_size, CBFS_TYPE_RAW); + stm_image_size = cbfs_load("stm.bin", mseg_base, stm_buffer_size); printk(BIOS_DEBUG, "STM:loaded into mseg: 0x%p size: %u\n", mseg_base, stm_image_size); /* status is number of bytes loaded */ diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index e7b64b2..3d14e14 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -397,7 +397,7 @@ { size_t size; const char *filename = EC_HASH_FILENAME(select); - const uint8_t *file = cbfs_boot_map_with_leak(filename, CBFS_TYPE_RAW, &size); + const uint8_t *file = cbfs_map(filename, &size); if (file == NULL) return VB2_ERROR_UNKNOWN; diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index facd5f8..b671b55 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -150,9 +150,8 @@ GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo; pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( - "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM, NULL); + pVbiosImageInfo->ImagePtr = cbfs_map( + "pci"CONFIG_VGA_BIOS_ID".rom", NULL); printk(BIOS_DEBUG, "%s: IMGptr=%p\n", __func__, pVbiosImageInfo->ImagePtr); return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING; diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 8abb328..18a7b3f 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -347,8 +347,7 @@ size_t size = 0; - void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb", - CBFS_TYPE_RAW, &size); + void *ptr = cbfs_map("sff8104-linux.dtb", &size); if (ptr) memcpy(_sff8104, ptr, size); /* Point to devicetree in secure memory */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index c21a0c4..d6f26cd 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -142,7 +142,7 @@ } /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { + if (cbfs_map("mrc.bin", NULL) == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 2cd35ea..b5c8a78 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -126,7 +126,7 @@ printk(BIOS_DEBUG, "MMA: Entry %s\n", __func__); if (cbfs_locate_file_in_region(&metadata_fh, MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, &mma_type)) { + MMA_TEST_METADATA_FILENAME)) { printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", MMA_TEST_METADATA_FILENAME); return -1; @@ -167,7 +167,7 @@ test_filename, test_param_filename); if (cbfs_locate_file_in_region(&test_content_fh, MMA_CBFS_REGION, - test_filename, &efi_type)) { + test_filename)) { printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", test_filename); return -1; @@ -176,7 +176,7 @@ cbfs_file_data(&mma_cfg->test_content, &test_content_fh); if (cbfs_locate_file_in_region(&test_param_fh, MMA_CBFS_REGION, - test_param_filename, &mma_type)) { + test_param_filename)) { printk(BIOS_DEBUG, "MMA: Failed to locate %s\n", test_param_filename); return -1; diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index c21a2a7..2d9ec23 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -106,8 +106,7 @@ const struct microcode *microcode_file; size_t microcode_len; - microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &microcode_len); + microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len); if ((microcode_file != NULL) && (microcode_len != 0)) { /* Update CPU Microcode patch base address/size */ diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 020da93..b275422 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -245,8 +245,7 @@ stopwatch_init(&sw); - size_t file_size = cbfs_boot_load_file(file_name, spm_bin, - sizeof(spm_bin), CBFS_TYPE_RAW); + size_t file_size = cbfs_load(file_name, spm_bin, sizeof(spm_bin)); if (file_size == 0) { printk(BIOS_ERR, "SPM binary %s not found\n", file_name); diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index 857d3dc..2e1065b 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -26,10 +26,7 @@ void sspm_init(void) { const char *file_name = "sspm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - sspm_bin, - sizeof(sspm_bin), - CBFS_TYPE_RAW); + size_t fw_size = cbfs_load(file_name, sspm_bin, sizeof(sspm_bin)); if (fw_size == 0) die("SSPM file :sspm.bin not found."); diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 9d608fa..ceecdf2 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -36,8 +36,7 @@ void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = cbfs_map(file_name, &blob_size); if (!blob_mbn) return NULL; diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index 2da868b..0d783eb 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -32,8 +32,7 @@ void *blob_dest; size_t blob_size; - blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, - &blob_size); + blob_mbn = cbfs_map(file_name, &blob_size); if (!blob_mbn) return NULL; diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 9c05452..653a90f 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -25,15 +25,15 @@ ssize_t ssize; /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index ae7251a..eb0fa20 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -24,15 +24,15 @@ ssize_t ssize; /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index 4429c1f..70a6332 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -248,7 +248,7 @@ size_t size; printk(BIOS_DEBUG, "%s: Measure %s\n", __func__, name); - base = cbfs_boot_map_with_leak(name, type, &size); + base = cbfs_map(name, &size); if (base == NULL) { printk(BIOS_DEBUG, "%s: CBFS locate fail: %s\n", __func__, name); diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9d99e02..69d8ade 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -46,7 +46,7 @@ sd = vb2_get_sd(ctx); - buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); + buffer = cbfs_map(RSA_PUBLICKEY_FILE_NAME, &size); if (!buffer || !size) { printk(BIOS_ERR, "ERROR: Public key not found!\n"); goto fail; @@ -84,7 +84,7 @@ pre->flags = VB2_FIRMWARE_PREAMBLE_DISALLOW_HWCRYPTO; /* Fill body_signature (vb2_structure). RSA2048 key is used */ - cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); + cbfs_map("oemmanifest.bin", &size); if (size != ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) { printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); goto fail; @@ -195,7 +195,7 @@ void *start; size_t size; - start = cbfs_boot_map_with_leak(name, type & ~VERIFIED_BOOT_COPY_BLOCK, &size); + start = cbfs_map(name, &size); if (start && size) { /* Speed up processing by copying the file content to memory first */ if (!ENV_ROMSTAGE_OR_BEFORE && (type & VERIFIED_BOOT_COPY_BLOCK)) { diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 01de60c..d597d3e 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -29,8 +29,7 @@ const char *filename = get_wifi_sar_cbfs_filename(); if (filename == NULL) filename = WIFI_SAR_CBFS_FILENAME; - return cbfs_boot_load_file(filename, buf, - buffer_size, CBFS_TYPE_RAW); + return cbfs_load(filename, buf, buffer_size); } /* Retrieve the wifi SAR limits data from VPD and decode it diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index a4b8e54..e155404 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -482,7 +482,7 @@ return CB_SUCCESS; } - ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, &filesize); + ptr = cbfs_map(hwi_filename, &filesize); if (!ptr) { printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", hwi_filename); -- To view, visit https://review.coreboot.org/c/coreboot/+/39304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Gerrit-Change-Number: 39304 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

6 22

Change in ...coreboot[master]: Adding Asus A88XM-E FM2+ motherboard with documentation
by Balázs Vinarz (Code Review) 06 Dec '20

06 Dec '20

Balázs Vinarz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30987 Change subject: Adding Asus A88XM-E FM2+ motherboard with documentation ...................................................................... Adding Asus A88XM-E FM2+ motherboard with documentation Signed-off-by: Balazs Vinarz <vinibali1(a)gmail.com> Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 --- A Documentation/mainboard/asus/a88xm-e.md A src/mainboard/asus/a88xm-e/BiosCallOuts.c A src/mainboard/asus/a88xm-e/Kconfig A src/mainboard/asus/a88xm-e/Kconfig.name A src/mainboard/asus/a88xm-e/Makefile.inc A src/mainboard/asus/a88xm-e/OemCustomize.c A src/mainboard/asus/a88xm-e/OptionsIds.h A src/mainboard/asus/a88xm-e/acpi/cpstate.asl A src/mainboard/asus/a88xm-e/acpi/gpe.asl A src/mainboard/asus/a88xm-e/acpi/mainboard.asl A src/mainboard/asus/a88xm-e/acpi/routing.asl A src/mainboard/asus/a88xm-e/acpi/sata.asl A src/mainboard/asus/a88xm-e/acpi/si.asl A src/mainboard/asus/a88xm-e/acpi/sleep.asl A src/mainboard/asus/a88xm-e/acpi/superio.asl A src/mainboard/asus/a88xm-e/acpi/thermal.asl A src/mainboard/asus/a88xm-e/acpi/usb_oc.asl A src/mainboard/asus/a88xm-e/acpi_tables.c A src/mainboard/asus/a88xm-e/board_info.txt A src/mainboard/asus/a88xm-e/buildOpts.c A src/mainboard/asus/a88xm-e/cmos.layout A src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb A src/mainboard/asus/a88xm-e/dsdt.asl A src/mainboard/asus/a88xm-e/irq_tables.c A src/mainboard/asus/a88xm-e/mainboard.c A src/mainboard/asus/a88xm-e/mptable.c A src/mainboard/asus/a88xm-e/romstage.c 27 files changed, 2,371 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30987/1 diff --git a/Documentation/mainboard/asus/a88xm-e.md b/Documentation/mainboard/asus/a88xm-e.md new file mode 100644 index 0000000..5f50c5a --- /dev/null +++ b/Documentation/mainboard/asus/a88xm-e.md @@ -0,0 +1,131 @@ +# ASUS A88XM-E + +This page describes how to run coreboot on the [ASUS A88XM-E]. + +## Technology + +Both "Trinity" and "Richland" FM2 desktop processing units are working, +the CPU architecture in these CPUs/APUs are [Piledriver], +and their GPU is [TeraScale 3] (VLIW4-based). + +Kaveri is non-working at the moment (FM2+), +the CPU architecture in these CPUs/APUs are [Steamroller], +and their GPU is [Sea Islands] (GCN2-based). + +```eval_rst ++------------------+--------------------------------------------------+ +| A88XM-E | | ++------------------+--------------------------------------------------+ +| DDR voltage IC | Nuvoton 3101S | ++------------------+--------------------------------------------------+ +| Network | Realtek RTL8111G - Not working | ++------------------+--------------------------------------------------+ +| Northbridge | Integrated into CPU with IMC and GPU (APUs only) | ++------------------+--------------------------------------------------+ +| Southbridge | Bolton-D4 | ++------------------+--------------------------------------------------+ +| Sound IC | Realtek ALC887 | ++------------------+--------------------------------------------------+ +| Super I/O | ITE 8603E | ++------------------+--------------------------------------------------+ +| VRM controller | DIGI VRM ASP1206 | ++------------------+--------------------------------------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | yes | ++---------------------+------------+ +| Model | [GD25Q64] | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | DIP-8 | ++---------------------+------------+ +| Write protection | yes | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom], if the +AmdSpiRomProtect modules have been deleted in the factory image previously. + +## Integrated graphics + +### Retrieve the VGA optionrom from the vendor EFI binary by running: + + # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768 + +This version is usable for all the GPUs. +1002,9901 Trinity (Radeon HD 7660D) +1002,9904 Trinity (Radeon HD 7560D) +1002,990c Richland (Radeon HD 8670D) +1002,990e Richland (Radeon HD 8570D) +1002,9991 Trinity (Radeon HD 7540D) +1002,9993 Trinity (Radeon HD 7480D) +1002,9996 Richland (Radeon HD 8470D) +1002,9998 Richland (Radeon HD 8370D) +1002,999d Richland (Radeon HD 8550D) +1002,130f Kaveri (Radeon R7) + +## Known issues + +- AHCI hot-plug +- Integrated ethernet +- S3 resume +- XHCI + +### XHCI ports can broke after using any of the blobs, restarting the +board with factory image makes it work again as fallback. +Tested even with/without the Bolton and Hudson blobs. + +## Untested + +- audio over HDMI +- IOMMU +- PS/2 mouse + +## TODOs + +- one ATOMBIOS module for all the integrated GPUs +- manage to work with Kaveri/Godavary (missing PSP firmware?) + +## Working + +- ACPI +- CPU frequency scaling +- flashrom under coreboot +- Hardware monitoring +- Integrated graphics +- Keyboard +- KVM virtualization +- Onboard audio +- PCI +- PCIe +- PS/2 keyboard (during payload, bootloader) +- SATA +- Serial port +- SuperIO based fan control +- USB (disabling XHCI controller makes to work as fallback USB2.0 ports) + +## Extra resources + +- [Board manual] + +[ASUS A88XM-E]: https://www.asus.com/Motherboards/A88XME/ +[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/A88XM-E/E9125_A88XM-E.pdf +[flashrom]: https://flashrom.org/Flashrom +[GD25Q64]: http://www.elm-tech.com/ja/products/spi-flash-memory/gd25q64/gd25q64.pdf +[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines +[Sea Islands]: https://en.wikipedia.org/wiki/Graphics_Core_Next#GCN_2nd_generation +[Steamroller]: https://en.wikipedia.org/wiki/Steamroller_(microarchitecture) +[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c new file mode 100644 index 0000000..56c1753 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> + +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <stdlib.h> + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * ASUS A88XM-E board ALC887-VD Verb Table + * + * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running + * the vendor BIOS. + */ +#if !IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E) +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} + }; +#else +const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = { + {0x11, 0x90460130}, + {0x12, 0x40330000}, + {0x14, 0x01014010}, + {0x15, 0x411111f0}, + {0x16, 0x411111f0}, + {0x17, 0x411111f0}, + {0x18, 0x01a19040}, + {0x19, 0x02a19050}, + {0x1a, 0x0181304f}, + {0x1b, 0x02214020}, + {0x1c, 0x411111f0}, + {0x1d, 0x4044c601}, + {0x1e, 0x411111f0}, + {0x1f, 0x411111f0} +}; +#endif + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0887, (CODEC_ENTRY*)&a88xm_e_alc887_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + FchParams_env->Imc.ImcEnable = FALSE; + FchParams_env->Hwm.HwMonitorEnable = FALSE; + FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ +} diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig new file mode 100644 index 0000000..70be2f1 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig @@ -0,0 +1,117 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_A88XM_E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY15_TN + select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN + select SOUTHBRIDGE_AMD_AGESA_HUDSON + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +choice + prompt "DDR3 memory voltage" + default BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + +config BOARD_ASUS_A88XM_E_DDR3_VOLT_135 + bool "1.35V" + help + Set DRR3 memory voltage to 1.35V +config BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + bool "1.50V" + help + Set DRR3 memory voltage to 1.50V +config BOARD_ASUS_A88XM_E_DDR3_VOLT_165 + bool "1.65V" + help + Set DRR3 memory voltage to 1.65V +endchoice + +config BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL + hex + default 0x9e if BOARD_ASUS_A88XM_E_DDR3_VOLT_135 + default 0x0 if BOARD_ASUS_A88XM_E_DDR3_VOLT_150 + default 0x1e if BOARD_ASUS_A88XM_E_DDR3_VOLT_165 + +config MAINBOARD_DIR + string + default asus/a88xm-e + +config MAINBOARD_PART_NUMBER + string + default "A88XM-E" if BOARD_ASUS_A88XM_E + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HUDSON_XHCI_FWM + bool + default n + +config HUDSON_IMC_FWM + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,990e" + +config CONFIG_DRIVERS_PS2_KEYBOARD + bool + default y + +config CONFIG_HUDSON_XHCI_ENABLE + bool + default n + +config HUDSON_LEGACY_FREE + bool + default n + +config POST_IO + bool + default n + +config CONFIG_POST_DEVICE_PCI_PCIE + bool + default y + +config DEVICETREE + string + default "devicetree_a88xm-e.cb" + +endif # BOARD_ASUS_A88XM_E diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name new file mode 100644 index 0000000..492d610 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_A88XM_E + bool "A88XM-E" diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc new file mode 100644 index 0000000..f8895fa --- /dev/null +++ b/src/mainboard/asus/a88xm-e/Makefile.inc @@ -0,0 +1,22 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c new file mode 100644 index 0000000..4c4c5bf --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OemCustomize.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <PlatformMemoryConfiguration.h> + +/* + * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping) + * + * Lane Id + * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8 + * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8 + * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8 + * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8 + * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7 + * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7 + * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7 + * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7 + * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI + * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI + * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI + * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI + * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI + * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI + * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI + * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI + * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI + * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI + * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI + * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI + * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI + * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI + * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI + * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI + * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs) + * 25 DP0_TX[P,N]1 + * 26 DP0_TX[P,N]2 + * 27 DP0_TX[P,N]3 + * 28 DP1_TX[P,N]0 + * 29 DP1_TX[P,N]1 + * 30 DP1_TX[P,N]2 + * 31 DP1_TX[P,N]3 + * 32 DP2_TX[P,N]0 + * 33 DP2_TX[P,N]1 + * 34 DP2_TX[P,N]2 + * 35 DP2_TX[P,N]3 + * 36 DP2_TX[P,N]4 + * 37 DP2_TX[P,N]5 + * 38 DP2_TX[P,N]6 + */ + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) + }, + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) + }, +}; + +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI + * Untested: HDMI + */ +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + // DP0 to HDMI0/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) + }, + // DP1 to FCH + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // DP2 to HDMI1/DP + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList, +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PsppPolicy = 0; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ + +static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = { + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)) + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h new file mode 100644 index 0000000..b45f5a8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/OptionsIds.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl new file mode 100644 index 0000000..69de2d8 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl new file mode 100644 index 0000000..297db37 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl new file mode 100644 index 0000000..8398c88 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl new file mode 100644 index 0000000..0af6b42 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl @@ -0,0 +1,258 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl new file mode 100644 index 0000000..ff0c3cf --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/si.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl new file mode 100644 index 0000000..08b7de4 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl new file mode 100644 index 0000000..f5d6980 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c new file mode 100644 index 0000000..f94fde0 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/acpi_tables.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt new file mode 100644 index 0000000..bc090ff --- /dev/null +++ b/src/mainboard/asus/a88xm-e/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/A88XME/ +ROM package: DIP8 +ROM protocol: [http://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flas… SPI] +ROM socketed: y +Flashrom support: y (without AmdSpiRomProtect modules) +Release year: 2014 diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c new file mode 100644 index 0000000..c324532 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -0,0 +1,346 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file + * + * AMD User options selection for a Brazos platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + */ + +#include <stdlib.h> + +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> +/* the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> + + +/* Select the CPU family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT FALSE +#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE + +/* Select the CPU socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP2_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +#define INSTALL_FM2_SOCKET_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +//This element selects whether P-States should be forced to be independent, +// as reported by the ACPI _PSD object. For single-link processors, +// setting TRUE for OS to support this feature. + +//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +// Specify the default values for the VRM controlling the VDDNB plane. +// If not specified, the values used for the core VRM will be applied +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity + +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 + +#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 +#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 + +#if IS_ENABLED(CONFIG_GFXUMA) +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#endif + +#define BLDCFG_IOMMU_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID +//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +/* + * Customized OEM build configurations for FCH component + */ +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE + +CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL } +}; + +#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList + + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} + + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} + +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR2100_FREQUENCY 1050 ///< DDR 2100 +#define DDR2133_FREQUENCY 1066 ///< DDR 2133 +#define DDR2400_FREQUENCY 1200 ///< DDR 2400 +#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +/* The AGESA likes to enable 512 bytes region on this base for LPC bus */ +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define DFLT_FCH_GPP_PORT0_PRESENT TRUE +#define DFLT_FCH_GPP_PORT1_PRESENT TRUE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +//#define BLDCFG_IR_PIN_CONTROL 0x33 +//#define FCH_NO_XHCI_SUPPORT FALSE +GPIO_CONTROL a88xm_e_gpio[] = { +// {183, Function1, PullUpB}, + {-1} +}; +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&a88xm_e_gpio[0]) + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) + +/* Moving this include up will break AGESA. */ +#include <PlatformInstall.h> diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout new file mode 100644 index 0000000..e1dbd9a --- /dev/null +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -0,0 +1,66 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#392 3 r 0 unused +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb new file mode 100644 index 0000000..e2b0eea --- /dev/null +++ b/src/mainboard/asus/a88xm-e/devicetree_a88xm-e.cb @@ -0,0 +1,143 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family15tn/root_complex + + device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal Audio (iGPU) + device pci 2.0 on end # PCIE x4/x16 yellow (?) + device pci 3.0 on end # unused? + device pci 4.0 on end # PCIE x4/x16 yellow (?) + device pci 5.0 off end # unused + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" + + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end # + device pci 14.3 off end # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 off end # unused + device pci 15.2 on end # PCI bridge + device pci 15.3 off end # unused + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + end #domain +end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl new file mode 100644 index 0000000..45a2606 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> + + /* Describe the supported Sleep States for this Southbridge */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + + /** + * TODO: The devices listed here (SBR0 and SBR1) do not appear to + * be referenced anywhere and could possibly be removed. + */ + Device(SBR0) { /* PCIe 1x SB */ + Name(_ADR, 0x00150000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(ABR0) } /* APIC mode */ + Return (PBR0) /* PIC mode */ + } + } + + Device(SBR1) { /* Onboard network */ + Name(_ADR, 0x00150001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT, 0) { + If(PMOD){ Return(ABR1) } /* APIC mode */ + Return (PBR1) /* PIC mode */ + } + } + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c new file mode 100644 index 0000000..88d2160 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/irq_tables.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <stdint.h> +#include <string.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c new file mode 100644 index 0000000..2a0e618 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> +#include <device/device.h> + +/************************************************* + * enable the dedicated function in thatcher board. + *************************************************/ +static void mainboard_enable(struct device *dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(LS_CFG_MSR); + msr.lo &= ~(1 << 28); + wrmsr(LS_CFG_MSR, msr); + + msr = rdmsr(DC_CFG_MSR); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(DC_CFG_MSR, msr); + + msr = rdmsr(BU_CFG_MSR); + msr.lo &= ~(1 << 23); + wrmsr(BU_CFG_MSR, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c new file mode 100644 index 0000000..d97663d --- /dev/null +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c new file mode 100644 index 0000000..0a85c27 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/romstage.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +#include <northbridge/amd/agesa/state_machine.h> +#include <southbridge/amd/common/amd_defs.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smbus.h> +#include <stdint.h> +#include <string.h> + +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void superio_init_e(void) +{ + pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1); + pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO); + + ite_kill_watchdog(gpio); + ite_enable_serial(uart, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(gpio); +} + +void board_BeforeAgesa(struct sysinfo *cb) +{ + u8 byte; + pci_devfn_t dev; + + if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + hudson_lpc_port80(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + if (IS_ENABLED(CONFIG_BOARD_ASUS_A88XM_E)) + superio_init_e(); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + + /* set DDR3 voltage */ + byte = CONFIG_BOARD_ASUS_A88XM_E_DDR3_VOLT_VAL; + + /* default is byte = 0x0, so no need to set it in this case */ + if (byte) + do_smbus_write_byte(0xb20, 0x15, 0x3, byte); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Gerrit-Change-Number: 30987 Gerrit-PatchSet: 1 Gerrit-Owner: Balázs Vinarz <vinibali1(a)gmail.com> Gerrit-MessageType: newchange

9 252

Change in coreboot[master]: amd_blobs: Always set default paths
by Nico Huber (Code Review) 05 Dec '20

05 Dec '20

Hello Marshall Dawson, Richard Spiegel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38044 to review the following change. Change subject: amd_blobs: Always set default paths ...................................................................... amd_blobs: Always set default paths Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This way we get error messages about the missing files when the blobs repos aren't checked out. Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/amd/stoneyridge/Kconfig M src/vendorcode/amd/pi/Kconfig 2 files changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/38044/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index a03b8f3..cc7354f 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -155,7 +155,6 @@ config VGA_BIOS_FILE string - default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/CarrizoGenericVbios.bin" if AMD_APU_MERLINFALCON default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_PRAIRIEFALCON default "3rdparty/amd_blobs/stoneyridge/StoneyGenericVbios.bin" if AMD_APU_STONEYRIDGE @@ -197,7 +196,6 @@ config STONEYRIDGE_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/xhci.bin" depends on STONEYRIDGE_XHCI_FWM @@ -207,7 +205,6 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "" if !USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/PSP/CZ/AmdPubKeyCZ.bin" if AMD_APU_MERLINFALCON default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_PRAIRIEFALCON default "3rdparty/amd_blobs/stoneyridge/PSP/ST/AmdPubKeyST.bin" if AMD_APU_STONEYRIDGE diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 9dcdf34..ee2958a 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -43,9 +43,9 @@ string "AGESA PI binary file name" default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01 default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON && USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON && USE_AMD_BLOBS - default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE && USE_AMD_BLOBS + default "3rdparty/amd_blobs/stoneyridge/pi/CZ/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON + default "3rdparty/amd_blobs/stoneyridge/pi/ST/$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. @@ -70,7 +70,7 @@ config AGESA_PRE_MEMORY_BINARY_PI_FILE string "Pre memory Binary PI file name" depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE # FIXME: File doesn't exist help Specify the binary file to use for pre-memory AMD platform initialization. @@ -78,7 +78,7 @@ config AGESA_POST_MEMORY_BINARY_PI_FILE string "Post memory Binary PI file name" depends on AGESA_SPLIT_MEMORY_FILES - default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE && USE_AMD_BLOBS + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE # FIXME: File doesn't exist help Specify the binary file to use for post-memory AMD platform initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/38044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0 Gerrit-Change-Number: 38044 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/tigerlake: Define and use a Kconfig for no of USB ports.
by Meera Ravindranath (Code Review) 03 Dec '20

03 Dec '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38682 ) Change subject: src/soc/tigerlake: Define and use a Kconfig for no of USB ports. ...................................................................... src/soc/tigerlake: Define and use a Kconfig for no of USB ports. BUG=None BRANCH=None TEST=Compilation for jasper lake board is working Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params_jsl.c M src/soc/intel/tigerlake/fsp_params_tgl.c 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index cef1fd0..f50e40e 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -156,6 +156,16 @@ default 3 if SOC_INTEL_JASPERLAKE default 4 if SOC_INTEL_TIGERLAKE +config SOC_INTEL_USB2_DEV_MAX + int + default 8 if SOC_INTEL_JASPERLAKE + default 10 if SOC_INTEL_TIGERLAKE + +config SOC_INTEL_USB3_DEV_MAX + int + default 6 if SOC_INTEL_JASPERLAKE + default 4 if SOC_INTEL_TIGERLAKE + config SOC_INTEL_I2C_DEV_MAX int default 6 diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 8046b2e..d5d623b 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -106,7 +106,7 @@ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); /* USB configuration */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -116,7 +116,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..f027ee0 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -89,7 +89,7 @@ params->IomTypeCPortPadCfg[i] = 0x09000000; /* USB */ - for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB2_DEV_MAX; i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; @@ -98,7 +98,7 @@ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } - for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + for (i = 0; i < CONFIG_SOC_INTEL_USB3_DEV_MAX; i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/38682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb Gerrit-Change-Number: 38682 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: cbfstool: Hide hash printing behind -v and add to parseable output
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41119 to review the following change. Change subject: cbfstool: Hide hash printing behind -v and add to parseable output ...................................................................... cbfstool: Hide hash printing behind -v and add to parseable output With the upcoming introduction of CBFS verification, a lot more CBFS files will have hashes. The current cbfstool default of always printing hash attributes when they exist will make cbfstool print very messy. Therefore, hide hash attribute output unless the user passed -v. It would also be useful to be able to get file attributes like hashes in machine parseable output. Unfortunately, our machine parseable format (-k) doesn't really seem designed to be extensible. To avoid breaking older parsers, this patch adds new attribute output behind -v (which hopefully no current users pass since it doesn't change anything for -k at the moment). With this patch cbfstool print -k -v may print an arbitrary amount of extra tokens behind the predefined ones on a file line. Tokens always begin with an identifying string (e.g. 'hash'), followed by extra fields that should be separated by colons. Multiple tokens are separated by the normal separator character (tab). cbfstool print -k -v may also print additional information that applies to the whole CBFS on separate lines. These lines will always begin with a '[' (which hopefully nobody would use as a CBFS filename character although we technically have no restrictions at the moment). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9e16cda393fa0bc1d8734d4b699e30e2ae99a36d --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 3 files changed, 41 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/41119/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 7942b27..3a83694 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1503,6 +1503,9 @@ decompressed_size ); + if (!verbose) + return 0; + struct cbfs_file_attr_hash *attr = NULL; while ((attr = cbfs_file_get_next_hash(entry, attr)) != NULL) { size_t hash_len = vb2_digest_size(attr->hash.algo); @@ -1522,9 +1525,6 @@ free(hash_str); } - if (!verbose) - return 0; - DEBUG(" cbfs_file=0x%x, offset=0x%x, content_address=0x%x+0x%x\n", cbfs_get_entry_addr(image, entry), ntohl(entry->offset), cbfs_get_entry_addr(image, entry) + ntohl(entry->offset), @@ -1587,21 +1587,45 @@ fprintf(fp, "%s%s", type, sep); fprintf(fp, "0x%zx%s", metadata_size, sep); fprintf(fp, "0x%zx%s", data_size, sep); - fprintf(fp, "0x%zx\n", metadata_size + data_size); + fprintf(fp, "0x%zx", metadata_size + data_size); + + if (verbose) { + unsigned int decompressed_size = 0; + unsigned int compression = cbfs_file_get_compression_info(entry, + &decompressed_size); + if (compression != CBFS_COMPRESS_NONE) + fprintf(fp, "%scomp:%s:0x%x", sep, lookup_name_by_type( + types_cbfs_compression, compression, "????"), + decompressed_size); + + struct cbfs_file_attr_hash *attr = NULL; + while ((attr = cbfs_file_get_next_hash(entry, attr)) != NULL) { + size_t hash_len = vb2_digest_size(attr->hash.algo); + if (!hash_len) + continue; + char *hash_str = bintohex(attr->hash.raw, hash_len); + int valid = vb2_hash_verify(CBFS_SUBHEADER(entry), + ntohl(entry->len), &attr->hash) == VB2_SUCCESS; + fprintf(fp, "%shash:%s:%s:%s", sep, + vb2_get_hash_algorithm_name(attr->hash.algo), + hash_str, valid ? "valid" : "invalid"); + free(hash_str); + } + } + fprintf(fp, "\n"); return 0; } -int cbfs_print_directory(struct cbfs_image *image) +void cbfs_print_directory(struct cbfs_image *image) { if (cbfs_is_legacy_cbfs(image)) cbfs_print_header_info(image); printf("%-30s %-10s %-12s Size Comp\n", "Name", "Offset", "Type"); cbfs_legacy_walk(image, cbfs_print_entry_info, NULL); - return 0; } -int cbfs_print_parseable_directory(struct cbfs_image *image) +void cbfs_print_parseable_directory(struct cbfs_image *image) { size_t i; const char *header[] = { @@ -1618,7 +1642,6 @@ fprintf(stdout, "%s%s", header[i], sep); fprintf(stdout, "%s\n", header[i]); cbfs_legacy_walk(image, cbfs_print_parseable_entry_info, stdout); - return 0; } int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index a3a6fb9..d633fee 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -174,8 +174,8 @@ int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry); /* Print CBFS component information. */ -int cbfs_print_directory(struct cbfs_image *image); -int cbfs_print_parseable_directory(struct cbfs_image *image); +void cbfs_print_directory(struct cbfs_image *image); +void cbfs_print_parseable_directory(struct cbfs_image *image); int cbfs_print_header_info(struct cbfs_image *image); int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, void *arg); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f97745e..6015603 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1087,12 +1087,16 @@ if (cbfs_image_from_buffer(&image, param.image_region, param.headeroffset)) return 1; - if (param.machine_parseable) - return cbfs_print_parseable_directory(&image); - else { + if (param.machine_parseable) { + if (verbose) + printf("[FMAP REGION]\t%s\n", param.region_name); + cbfs_print_parseable_directory(&image); + } else { printf("FMAP REGION: %s\n", param.region_name); - return cbfs_print_directory(&image); + cbfs_print_directory(&image); } + + return 0; } static int cbfs_extract(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/41119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e16cda393fa0bc1d8734d4b699e30e2ae99a36d Gerrit-Change-Number: 41119 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfstool: Rename cbfs_walk() to cbfs_legacy_walk()
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41118 to review the following change. Change subject: cbfstool: Rename cbfs_walk() to cbfs_legacy_walk() ...................................................................... cbfstool: Rename cbfs_walk() to cbfs_legacy_walk() This function name clashes with cbfs_walk() in the new commonlib CBFS stack, so rename it to cbfs_legacy_walk(). While we could replace it with the new commonlib implementation, it still has support for certain features in the deprecated pre-FMAP CBFSes (such as non-standard header alignment), which are needed to handle old files but probably not something we'd want to burden the commonlib implementation with. So until we decide to deprecate support for those files from cbfstool as well, it seems easier to just keep the existing implementation here. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I37c7e7aa9a206372817d8d0b8f66d72bafb4f346 --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h 2 files changed, 13 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/41118/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 035b196..7942b27 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -469,7 +469,7 @@ cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, last_entry_size, ""); /* If the last entry was an empty file, merge them. */ - cbfs_walk(&image, cbfs_merge_empty_entry, NULL); + cbfs_legacy_walk(&image, cbfs_merge_empty_entry, NULL); } return 0; @@ -621,7 +621,7 @@ prev_size, ""); /* Merge any potential empty entries together. */ - cbfs_walk(image, cbfs_merge_empty_entry, NULL); + cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL); /* * Since current switched to an empty file keep track of it. @@ -760,7 +760,7 @@ // Merge empty entries. DEBUG("(trying to merge empty entries...)\n"); - cbfs_walk(image, cbfs_merge_empty_entry, NULL); + cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL); for (entry = cbfs_find_first_entry(image); entry && cbfs_is_valid_entry(image, entry); @@ -1380,7 +1380,7 @@ DEBUG("cbfs_remove_entry: Removed %s @ 0x%x\n", entry->filename, cbfs_get_entry_addr(image, entry)); entry->type = htonl(CBFS_TYPE_DELETED); - cbfs_walk(image, cbfs_merge_empty_entry, NULL); + cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL); return 0; } @@ -1597,7 +1597,7 @@ if (cbfs_is_legacy_cbfs(image)) cbfs_print_header_info(image); printf("%-30s %-10s %-12s Size Comp\n", "Name", "Offset", "Type"); - cbfs_walk(image, cbfs_print_entry_info, NULL); + cbfs_legacy_walk(image, cbfs_print_entry_info, NULL); return 0; } @@ -1617,7 +1617,7 @@ for (i = 0; i < ARRAY_SIZE(header) - 1; i++) fprintf(stdout, "%s%s", header[i], sep); fprintf(stdout, "%s\n", header[i]); - cbfs_walk(image, cbfs_print_parseable_entry_info, stdout); + cbfs_legacy_walk(image, cbfs_print_parseable_entry_info, stdout); return 0; } @@ -1660,7 +1660,7 @@ return 0; } -int cbfs_walk(struct cbfs_image *image, cbfs_entry_callback callback, +int cbfs_legacy_walk(struct cbfs_image *image, cbfs_entry_callback callback, void *arg) { int count = 0; @@ -1970,7 +1970,7 @@ need_len = metadata_size + size; // Merge empty entries to build get max available space. - cbfs_walk(image, cbfs_merge_empty_entry, NULL); + cbfs_legacy_walk(image, cbfs_merge_empty_entry, NULL); /* Three cases of content location on memory page: * case 1. diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 6ff0746..a3a6fb9 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -129,16 +129,18 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, size_t page_size, size_t align, size_t metadata_size); -/* Callback function used by cbfs_walk. +/* Callback function used by cbfs_legacy_walk. * Returns 0 on success, or non-zero to stop further iteration. */ typedef int (*cbfs_entry_callback)(struct cbfs_image *image, struct cbfs_file *file, void *arg); /* Iterates through all entries in CBFS image, and invoke with callback. - * Stops if callback returns non-zero values. + * Stops if callback returns non-zero values. Unlike the commonlib cbfs_walk(), + * this can deal with different alignments in legacy CBFS (with master header). * Returns number of entries invoked. */ -int cbfs_walk(struct cbfs_image *image, cbfs_entry_callback callback, void *arg); +int cbfs_legacy_walk(struct cbfs_image *image, cbfs_entry_callback callback, + void *arg); /* Primitive CBFS utilities */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c7e7aa9a206372817d8d0b8f66d72bafb4f346 Gerrit-Change-Number: 41118 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: cbfstool: Use cbfs_serialized.h and standard vboot helpers
by Julius Werner (Code Review) 03 Dec '20

03 Dec '20

Hello Patrick Georgi, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41117 to review the following change. Change subject: cbfstool: Use cbfs_serialized.h and standard vboot helpers ...................................................................... cbfstool: Use cbfs_serialized.h and standard vboot helpers This patch reduces some code duplication in cbfstool by switching it to use the CBFS data structure definitions in commonlib rather than its own private copy. In addition, replace a few custom helpers related to hash algorithms with the official vboot APIs of the same purpose. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 --- M src/commonlib/bsd/cbfs_mcache.c M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M src/commonlib/cbfs.c M src/mainboard/facebook/fbg1701/board_mboot.h M util/cbfstool/Makefile.inc M util/cbfstool/cbfs-mkpayload.c M util/cbfstool/cbfs-mkstage.c M util/cbfstool/cbfs-payload-linux.c M util/cbfstool/cbfs.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfscomptool.c M util/cbfstool/cbfstool.c M util/cbfstool/common.h M util/cbfstool/compress.c 17 files changed, 201 insertions(+), 409 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/41117/1 diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c index 5a967dd..45255c5 100644 --- a/src/commonlib/bsd/cbfs_mcache.c +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -108,8 +108,8 @@ const uint32_t data_offset = be32toh(entry->file.h.offset); const uint32_t data_length = be32toh(entry->file.h.len); - if (namesize <= data_offset - offsetof(union cbfs_mdata, filename) && - memcmp(name, entry->file.filename, namesize) == 0) { + if (namesize <= data_offset - offsetof(union cbfs_mdata, h.filename) && + memcmp(name, entry->file.h.filename, namesize) == 0) { LOG("Found '%s' @%#x size %#x in mcache @%p\n", name, entry->offset, data_length, current); *data_offset_out = entry->offset + data_offset; diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 0b6b888..e575cd3 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -46,7 +46,7 @@ const uint32_t data_offset = be32toh(mdata.h.offset); const uint32_t data_length = be32toh(mdata.h.len); const uint32_t type = be32toh(mdata.h.type); - const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2); + const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_NULL); DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n", offset, be32toh(mdata.h.type), attr_offset, data_offset, data_length); @@ -74,7 +74,7 @@ if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h), offset + sizeof(mdata.h), todo) != todo) return CB_CBFS_IO; - DEBUG("File name: '%s'\n", mdata.filename); + DEBUG("File name: '%s'\n", mdata.h.filename); if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset)) return CB_ERR; @@ -132,8 +132,8 @@ size_t already_read, void *arg) { struct cbfs_lookup_args *args = arg; - if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) || - memcmp(args->name, mdata->filename, args->namesize) != 0) + if (args->namesize > already_read - offsetof(union cbfs_mdata, h.filename) || + memcmp(args->name, mdata->h.filename, args->namesize) != 0) return CB_CBFS_NOT_FOUND; LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len)); diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index ac7b1b1..39e4e10 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -31,12 +31,8 @@ #include <cbfs_glue.h> /* Helper structure to allocate space for a blob of metadata on the stack. */ -#define CBFS_METADATA_MAX_SIZE 256 union cbfs_mdata { - struct { - struct cbfs_file h; - char filename[]; - }; + struct cbfs_file h; uint8_t raw[CBFS_METADATA_MAX_SIZE]; }; diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index 556c8e4..334c9f6 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -6,44 +6,40 @@ #include <stdint.h> #include <vb2_sha.h> -/** These are standard values for the known compression - algorithms that coreboot knows about for stages and - payloads. Of course, other CBFS users can use whatever - values they want, as long as they understand them. */ +enum cbfs_compression { + CBFS_COMPRESS_NONE = 0, + CBFS_COMPRESS_LZMA = 1, + CBFS_COMPRESS_LZ4 = 2, +}; -#define CBFS_COMPRESS_NONE 0 -#define CBFS_COMPRESS_LZMA 1 -#define CBFS_COMPRESS_LZ4 2 +enum cbfs_type { + CBFS_TYPE_DELETED = 0x00000000, + CBFS_TYPE_NULL = 0xffffffff, + CBFS_TYPE_BOOTBLOCK = 0x01, + CBFS_TYPE_CBFSHEADER = 0x02, + CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_SELF = 0x20, + CBFS_TYPE_FIT = 0x21, + CBFS_TYPE_OPTIONROM = 0x30, + CBFS_TYPE_BOOTSPLASH = 0x40, + CBFS_TYPE_RAW = 0x50, + CBFS_TYPE_VSA = 0x51, + CBFS_TYPE_MBI = 0x52, + CBFS_TYPE_MICROCODE = 0x53, + CBFS_TYPE_FSP = 0x60, + CBFS_TYPE_MRC = 0x61, + CBFS_TYPE_MMA = 0x62, + CBFS_TYPE_EFI = 0x63, + CBFS_TYPE_STRUCT = 0x70, + CBFS_TYPE_CMOS_DEFAULT = 0xaa, + CBFS_TYPE_SPD = 0xab, + CBFS_TYPE_MRC_CACHE = 0xac, + CBFS_TYPE_CMOS_LAYOUT = 0x01aa, +}; -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define CBFS_TYPE_DELETED 0x00000000 -#define CBFS_TYPE_DELETED2 0xffffffff -#define CBFS_TYPE_STAGE 0x10 -#define CBFS_TYPE_SELF 0x20 -#define CBFS_TYPE_FIT 0x21 -#define CBFS_TYPE_OPTIONROM 0x30 -#define CBFS_TYPE_BOOTSPLASH 0x40 -#define CBFS_TYPE_RAW 0x50 -#define CBFS_TYPE_VSA 0x51 -#define CBFS_TYPE_MBI 0x52 -#define CBFS_TYPE_MICROCODE 0x53 -#define CBFS_TYPE_FSP 0x60 -#define CBFS_TYPE_MRC 0x61 -#define CBFS_TYPE_MMA 0x62 -#define CBFS_TYPE_EFI 0x63 -#define CBFS_TYPE_STRUCT 0x70 -#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa -#define CBFS_TYPE_SPD 0xab -#define CBFS_TYPE_MRC_CACHE 0xac -#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa - -#define CBFS_HEADER_MAGIC 0x4F524243 -#define CBFS_HEADER_VERSION1 0x31313131 -#define CBFS_HEADER_VERSION2 0x31313132 +#define CBFS_HEADER_MAGIC 0x4F524243 /* BE: 'ORBC' */ +#define CBFS_HEADER_VERSION1 0x31313131 /* BE: '1111' */ +#define CBFS_HEADER_VERSION2 0x31313132 /* BE: '1112' */ #define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2 /* this is the master cbfs header - it must be located somewhere available @@ -67,9 +63,15 @@ /* "Unknown" refers to CBFS headers version 1, * before the architecture was defined (i.e., x86 only). */ -#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARM 0x00000010 +enum cbfs_architecture { + CBFS_ARCHITECTURE_UNKNOWN = 0xFFFFFFFF, + CBFS_ARCHITECTURE_X86 = 0x00000001, + CBFS_ARCHITECTURE_ARM = 0x00000010, + CBFS_ARCHITECTURE_AARCH64 = 0x0000aa64, + CBFS_ARCHITECTURE_MIPS = 0x00000100, /* deprecated */ + CBFS_ARCHITECTURE_RISCV = 0xc001d0de, + CBFS_ARCHITECTURE_PPC64 = 0x407570ff, +}; /** This is a component header - every entry in the CBFS will have this header. @@ -87,6 +89,7 @@ */ #define CBFS_FILE_MAGIC "LARCHIVE" +#define CBFS_METADATA_MAX_SIZE 256 struct cbfs_file { char magic[8]; @@ -94,8 +97,13 @@ uint32_t type; uint32_t attributes_offset; uint32_t offset; + char filename[0]; } __packed; +#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406 +_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); +#endif + /* The common fields of extended cbfs file attributes. Attributes are expected to start with tag/len, then append their specific fields. */ @@ -108,13 +116,16 @@ /* Depending on how the header was initialized, it may be backed with 0x00 or * 0xff. Support both. */ -#define CBFS_FILE_ATTR_TAG_UNUSED 0 -#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff -#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c -#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 -#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ -#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ -#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ +enum cbfs_file_attr_tag { + CBFS_FILE_ATTR_TAG_UNUSED = 0, + CBFS_FILE_ATTR_TAG_UNUSED2 = 0xffffffff, + CBFS_FILE_ATTR_TAG_COMPRESSION = 0x42435a4c, /* BE: 'BCZL' */ + CBFS_FILE_ATTR_TAG_HASH = 0x68736148, /* BE: 'hsaH' */ + CBFS_FILE_ATTR_TAG_POSITION = 0x42435350, /* BE: 'BCSP' */ + CBFS_FILE_ATTR_TAG_ALIGNMENT = 0x42434c41, /* BE: 'BCLA' */ + CBFS_FILE_ATTR_TAG_IBB = 0x32494242, /* BE: '2IBB' */ + CBFS_FILE_ATTR_TAG_PADDING = 0x47444150, /* BE: 'GNDP' */ +}; struct cbfs_file_attr_compression { uint32_t tag; @@ -176,11 +187,13 @@ struct cbfs_payload_segment segments; }; -#define PAYLOAD_SEGMENT_CODE 0x434F4445 -#define PAYLOAD_SEGMENT_DATA 0x44415441 -#define PAYLOAD_SEGMENT_BSS 0x42535320 -#define PAYLOAD_SEGMENT_PARAMS 0x50415241 -#define PAYLOAD_SEGMENT_ENTRY 0x454E5452 +enum cbfs_payload_segment_type { + PAYLOAD_SEGMENT_CODE = 0x434F4445, /* BE: 'CODE' */ + PAYLOAD_SEGMENT_DATA = 0x44415441, /* BE: 'DATA' */ + PAYLOAD_SEGMENT_BSS = 0x42535320, /* BE: 'BSS ' */ + PAYLOAD_SEGMENT_PARAMS = 0x50415241, /* BE: 'PARA' */ + PAYLOAD_SEGMENT_ENTRY = 0x454E5452, /* BE: 'ENTR' */ +}; struct cbfs_optionrom { uint32_t compression; diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index caa81ea..a4cdc60 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -351,7 +351,7 @@ if (cbfsf_file_type(fh, &ftype)) return VB2_ERROR_UNKNOWN; - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2) + if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL) continue; rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); diff --git a/src/mainboard/facebook/fbg1701/board_mboot.h b/src/mainboard/facebook/fbg1701/board_mboot.h index 5864d4b..1b93162 100644 --- a/src/mainboard/facebook/fbg1701/board_mboot.h +++ b/src/mainboard/facebook/fbg1701/board_mboot.h @@ -7,7 +7,7 @@ const mboot_measure_item_t mb_log_list[] = { { "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, { "revision", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, - { "cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, + { "cmos_layout.bin", CBFS_TYPE_CMOS_LAYOUT, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL }, #if CONFIG(VENDORCODE_ELTAN_VBOOT) { "oemmanifest.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_7, EV_NO_ACTION, diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index f38c825..000ceb2 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -108,6 +108,7 @@ TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include +TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/host/include # UEFI header file support. It's not pretty, but that's what we currently # have right now. TOOLCPPFLAGS += -I$(top)/src diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index 830fe16..da8fdee 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -66,7 +66,7 @@ } int parse_elf_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo) + enum cbfs_compression algo) { Elf64_Phdr *phdr; Elf64_Ehdr ehdr; @@ -247,7 +247,7 @@ struct buffer *output, uint32_t loadaddress, uint32_t entrypoint, - enum comp_algo algo) + enum cbfs_compression algo) { comp_func_ptr compress; struct cbfs_payload_segment segs[2] = { {0} }; @@ -292,7 +292,7 @@ } int parse_fv_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo) + enum cbfs_compression algo) { comp_func_ptr compress; struct cbfs_payload_segment segs[2] = { {0} }; @@ -420,7 +420,7 @@ } int parse_fit_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo) + enum cbfs_compression algo) { struct fdt_header *fdt_h; diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index be920b4..cfa820b 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -89,7 +89,7 @@ return NULL; } -static void fill_cbfs_stage(struct buffer *outheader, enum comp_algo algo, +static void fill_cbfs_stage(struct buffer *outheader, enum cbfs_compression algo, uint64_t entry, uint64_t loadaddr, uint32_t filesize, uint32_t memsize) { @@ -109,7 +109,7 @@ * works for all elf files, not just the restricted set. */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - enum comp_algo algo, uint32_t *location, + enum cbfs_compression algo, uint32_t *location, const char *ignore_section) { struct parsed_elf pelf; diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index 6b4bf27..b9e56ea 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -47,14 +47,14 @@ struct buffer cmdline; struct buffer initrd; /* Output variables. */ - enum comp_algo algo; + enum cbfs_compression algo; comp_func_ptr compress; struct buffer output; size_t offset; struct cbfs_payload_segment *out_seg; }; -static int bzp_init(struct bzpayload *bzp, enum comp_algo algo) +static int bzp_init(struct bzpayload *bzp, enum cbfs_compression algo) { memset(bzp, 0, sizeof(*bzp)); @@ -199,7 +199,7 @@ */ int parse_bzImage_to_payload(const struct buffer *input, struct buffer *output, const char *initrd_name, - char *cmdline, enum comp_algo algo) + char *cmdline, enum cbfs_compression algo) { struct bzpayload bzp; unsigned int initrd_base = 64*1024*1024; diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index f0c215d..10b478c 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -17,234 +17,57 @@ #define __CBFS_H #include "common.h" -#include <stdint.h> - -#include <vb2_api.h> - -/* cbfstool will fail when trying to build a cbfs_file header that's larger - * than MAX_CBFS_FILE_HEADER_BUFFER. 1K should give plenty of room. */ -#define MAX_CBFS_FILE_HEADER_BUFFER 1024 - -/* create a magic number in host-byte order. - * b3 is the high order byte. - * in the coreboot tools, we go with the 32-bit - * magic number convention. - * This was an inline func but that breaks anything - * that uses it in a case statement. - */ - -#define makemagic(b3, b2, b1, b0)\ - (((b3)<<24) | ((b2) << 16) | ((b1) << 8) | (b0)) +#include <commonlib/bsd/cbfs_serialized.h> /* To make CBFS more friendly to ROM, fill -1 (0xFF) instead of zero. */ #define CBFS_CONTENT_DEFAULT_VALUE (-1) -// Alignment (in bytes) to be used when no master header is present -#define CBFS_ENTRY_ALIGNMENT 64 - -#define CBFS_HEADER_MAGIC 0x4F524243 #define CBFS_HEADPTR_ADDR_X86 0xFFFFFFFC -#define CBFS_HEADER_VERSION1 0x31313131 -#define CBFS_HEADER_VERSION2 0x31313132 -#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2 -#define CBFS_ALIGNMENT 64 - -struct cbfs_header { - uint32_t magic; - uint32_t version; - uint32_t romsize; - uint32_t bootblocksize; - uint32_t align; /* hard coded to 64 byte */ - uint32_t offset; - uint32_t architecture; /* Version 2 */ - uint32_t pad[1]; -} __packed; - -#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARM 0x00000010 -#define CBFS_ARCHITECTURE_AARCH64 0x0000aa64 -#define CBFS_ARCHITECTURE_MIPS 0x00000100 /* deprecated */ -#define CBFS_ARCHITECTURE_RISCV 0xc001d0de -#define CBFS_ARCHITECTURE_PPC64 0x407570ff - -#define CBFS_FILE_MAGIC "LARCHIVE" - -struct cbfs_file { - uint8_t magic[8]; - /* length of file data */ - uint32_t len; +struct typedesc_t { uint32_t type; - /* offset to struct cbfs_file_attribute or 0 */ - uint32_t attributes_offset; - /* length of header incl. variable data */ - uint32_t offset; - char filename[]; -} __packed; + const char *name; +}; -#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406 -_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); -#endif - -/* The common fields of extended cbfs file attributes. - Attributes are expected to start with tag/len, then append their - specific fields. */ -struct cbfs_file_attribute { - uint32_t tag; - /* len covers the whole structure, incl. tag and len */ - uint32_t len; - uint8_t data[0]; -} __packed; - -/* Depending on how the header was initialized, it may be backed with 0x00 or - * 0xff. Support both. */ -#define CBFS_FILE_ATTR_TAG_UNUSED 0 -#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff -#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c -#define CBFS_FILE_ATTR_TAG_HASH 0x68736148 -#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ -#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ -#define CBFS_FILE_ATTR_TAG_PADDING 0x47444150 /* PDNG */ -#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ - -struct cbfs_file_attr_compression { - uint32_t tag; - uint32_t len; - /* whole file compression format. 0 if no compression. */ - uint32_t compression; - uint32_t decompressed_size; -} __packed; - -struct cbfs_file_attr_hash { - uint32_t tag; - uint32_t len; - uint32_t hash_type; - /* hash_data is len - sizeof(struct) bytes */ - uint8_t hash_data[]; -} __packed; - -struct cbfs_file_attr_position { - uint32_t tag; - uint32_t len; - uint32_t position; -} __packed; - -struct cbfs_file_attr_align { - uint32_t tag; - uint32_t len; - uint32_t alignment; -} __packed; - -struct cbfs_stage { - uint32_t compression; - uint64_t entry; - uint64_t load; - uint32_t len; - uint32_t memlen; -} __packed; - -#define PAYLOAD_SEGMENT_CODE makemagic('C', 'O', 'D', 'E') -#define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') -#define PAYLOAD_SEGMENT_BSS makemagic('B', 'S', 'S', ' ') -#define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A') -#define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R') - -struct cbfs_payload_segment { - uint32_t type; - uint32_t compression; - uint32_t offset; - uint64_t load_addr; - uint32_t len; - uint32_t mem_len; -} __packed; - -struct cbfs_payload { - struct cbfs_payload_segment segments; -} __packed; - -/** These are standard component types for well known - components (i.e - those that coreboot needs to consume. - Users are welcome to use any other value for their - components */ - -#define CBFS_COMPONENT_BOOTBLOCK 0x01 -#define CBFS_COMPONENT_CBFSHEADER 0x02 -#define CBFS_COMPONENT_STAGE 0x10 -#define CBFS_COMPONENT_SELF 0x20 -#define CBFS_COMPONENT_FIT 0x21 -#define CBFS_COMPONENT_OPTIONROM 0x30 -#define CBFS_COMPONENT_BOOTSPLASH 0x40 -#define CBFS_COMPONENT_RAW 0x50 -#define CBFS_COMPONENT_VSA 0x51 -#define CBFS_COMPONENT_MBI 0x52 -#define CBFS_COMPONENT_MICROCODE 0x53 -#define CBFS_COMPONENT_FSP 0x60 -#define CBFS_COMPONENT_MRC 0x61 -#define CBFS_COMPONENT_MMA 0x62 -#define CBFS_COMPONENT_EFI 0x63 -#define CBFS_COMPONENT_STRUCT 0x70 -#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa -#define CBFS_COMPONENT_SPD 0xab -#define CBFS_COMPONENT_MRC_CACHE 0xac -#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa - -/* The deleted type is chosen to be a value - * that can be written in a FLASH from all other - * values. - */ -#define CBFS_COMPONENT_DELETED 0 - -/* for all known FLASH, this value can be changed - * to all other values. This allows NULL files to be - * changed without a block erase - */ -#define CBFS_COMPONENT_NULL 0xFFFFFFFF +static const struct typedesc_t types_cbfs_compression[] = { + {CBFS_COMPRESS_NONE, "none"}, + {CBFS_COMPRESS_LZMA, "LZMA"}, + {CBFS_COMPRESS_LZ4, "LZ4"}, + {0, NULL}, +}; static struct typedesc_t filetypes[] unused = { - {CBFS_COMPONENT_BOOTBLOCK, "bootblock"}, - {CBFS_COMPONENT_CBFSHEADER, "cbfs header"}, - {CBFS_COMPONENT_STAGE, "stage"}, - {CBFS_COMPONENT_SELF, "simple elf"}, - {CBFS_COMPONENT_FIT, "fit"}, - {CBFS_COMPONENT_OPTIONROM, "optionrom"}, - {CBFS_COMPONENT_BOOTSPLASH, "bootsplash"}, - {CBFS_COMPONENT_RAW, "raw"}, - {CBFS_COMPONENT_VSA, "vsa"}, - {CBFS_COMPONENT_MBI, "mbi"}, - {CBFS_COMPONENT_MICROCODE, "microcode"}, - {CBFS_COMPONENT_FSP, "fsp"}, - {CBFS_COMPONENT_MRC, "mrc"}, - {CBFS_COMPONENT_CMOS_DEFAULT, "cmos_default"}, - {CBFS_COMPONENT_CMOS_LAYOUT, "cmos_layout"}, - {CBFS_COMPONENT_SPD, "spd"}, - {CBFS_COMPONENT_MRC_CACHE, "mrc_cache"}, - {CBFS_COMPONENT_MMA, "mma"}, - {CBFS_COMPONENT_EFI, "efi"}, - {CBFS_COMPONENT_STRUCT, "struct"}, - {CBFS_COMPONENT_DELETED, "deleted"}, - {CBFS_COMPONENT_NULL, "null"} + {CBFS_TYPE_BOOTBLOCK, "bootblock"}, + {CBFS_TYPE_CBFSHEADER, "cbfs header"}, + {CBFS_TYPE_STAGE, "stage"}, + {CBFS_TYPE_SELF, "simple elf"}, + {CBFS_TYPE_FIT, "fit"}, + {CBFS_TYPE_OPTIONROM, "optionrom"}, + {CBFS_TYPE_BOOTSPLASH, "bootsplash"}, + {CBFS_TYPE_RAW, "raw"}, + {CBFS_TYPE_VSA, "vsa"}, + {CBFS_TYPE_MBI, "mbi"}, + {CBFS_TYPE_MICROCODE, "microcode"}, + {CBFS_TYPE_FSP, "fsp"}, + {CBFS_TYPE_MRC, "mrc"}, + {CBFS_TYPE_CMOS_DEFAULT, "cmos_default"}, + {CBFS_TYPE_CMOS_LAYOUT, "cmos_layout"}, + {CBFS_TYPE_SPD, "spd"}, + {CBFS_TYPE_MRC_CACHE, "mrc_cache"}, + {CBFS_TYPE_MMA, "mma"}, + {CBFS_TYPE_EFI, "efi"}, + {CBFS_TYPE_STRUCT, "struct"}, + {CBFS_TYPE_DELETED, "deleted"}, + {CBFS_TYPE_NULL, "null"} }; -static const struct typedesc_t types_cbfs_hash[] unused = { - {VB2_HASH_INVALID, "none"}, - {VB2_HASH_SHA1, "sha1"}, - {VB2_HASH_SHA256, "sha256"}, - {VB2_HASH_SHA512, "sha512"}, - {0, NULL} -}; - -static size_t widths_cbfs_hash[] unused = { - [VB2_HASH_INVALID] = 0, - [VB2_HASH_SHA1] = 20, - [VB2_HASH_SHA256] = 32, - [VB2_HASH_SHA512] = 64, -}; - -#define CBFS_NUM_SUPPORTED_HASHES ARRAY_SIZE(widths_cbfs_hash) - #define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) +static inline size_t cbfs_file_attr_hash_size(enum vb2_hash_algorithm algo) { + return offsetof(struct cbfs_file_attr_hash, hash.raw) + + vb2_digest_size(algo); +} + /* cbfs_image.c */ uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value); uint32_t get_cbfs_compression(const char *name, uint32_t unknown); diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 9bf3688..035b196 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -80,16 +80,6 @@ return lookup_type_by_name(types_cbfs_compression, name); } -static const char *get_hash_attr_name(uint16_t hash_type) -{ - return lookup_name_by_type(types_cbfs_hash, hash_type, "(invalid)"); -} - -int cbfs_parse_hash_algo(const char *name) -{ - return lookup_type_by_name(types_cbfs_hash, name); -} - /* CBFS image */ size_t cbfs_calculate_file_header_size(const char *name) @@ -227,7 +217,7 @@ size_t empty_header_len = cbfs_calculate_file_header_size(""); uint32_t entries_offset = 0; - uint32_t align = CBFS_ENTRY_ALIGNMENT; + uint32_t align = CBFS_ALIGNMENT; if (image->has_header) { entries_offset = image->header.offset; @@ -266,7 +256,7 @@ size_t capacity = entries_size - empty_header_len; LOG("Created CBFS (capacity = %zu bytes)\n", capacity); - return cbfs_create_empty_entry(entry_header, CBFS_COMPONENT_NULL, + return cbfs_create_empty_entry(entry_header, CBFS_TYPE_NULL, capacity, ""); } @@ -402,7 +392,7 @@ size_t copy_end = buffer_size(dst); - align = CBFS_ENTRY_ALIGNMENT; + align = CBFS_ALIGNMENT; dst_entry = (struct cbfs_file *)buffer_get(dst); @@ -412,9 +402,9 @@ src_entry = cbfs_find_next_entry(image, src_entry)) { size_t entry_size; - if ((src_entry->type == htonl(CBFS_COMPONENT_NULL)) || - (src_entry->type == htonl(CBFS_COMPONENT_CBFSHEADER)) || - (src_entry->type == htonl(CBFS_COMPONENT_DELETED))) + if ((src_entry->type == htonl(CBFS_TYPE_NULL)) || + (src_entry->type == htonl(CBFS_TYPE_CBFSHEADER)) || + (src_entry->type == htonl(CBFS_TYPE_DELETED))) continue; entry_size = htonl(src_entry->len) + htonl(src_entry->offset); @@ -440,7 +430,7 @@ if (last_entry_size < 0) WARN("No room to create the last entry!\n") else - cbfs_create_empty_entry(dst_entry, CBFS_COMPONENT_NULL, + cbfs_create_empty_entry(dst_entry, CBFS_TYPE_NULL, last_entry_size, ""); return 0; @@ -476,7 +466,7 @@ cbfs_calculate_file_header_size("") - sizeof(int32_t); if (last_entry_size > 0) { - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, last_entry_size, ""); /* If the last entry was an empty file, merge them. */ cbfs_walk(&image, cbfs_merge_empty_entry, NULL); @@ -510,8 +500,8 @@ * maximum size. */ if ((strlen(trailer->filename) != 0) && - (trailer->type != htonl(CBFS_COMPONENT_NULL)) && - (trailer->type != htonl(CBFS_COMPONENT_DELETED))) { + (trailer->type != htonl(CBFS_TYPE_NULL)) && + (trailer->type != htonl(CBFS_TYPE_DELETED))) { /* nothing to truncate. Return de-facto CBFS size in case it * was already truncated. */ *size = (uint8_t *)entry - (uint8_t *)buffer_get(region); @@ -565,8 +555,8 @@ uint32_t type = htonl(cur->type); /* Current entry is empty. Kepp track of it. */ - if ((type == htonl(CBFS_COMPONENT_NULL)) || - (type == htonl(CBFS_COMPONENT_DELETED))) { + if ((type == htonl(CBFS_TYPE_NULL)) || + (type == htonl(CBFS_TYPE_DELETED))) { prev = cur; continue; } @@ -627,7 +617,7 @@ prev_size -= spill_size + empty_metadata_size; /* Create new empty file. */ - cbfs_create_empty_entry(cur, CBFS_COMPONENT_NULL, + cbfs_create_empty_entry(cur, CBFS_TYPE_NULL, prev_size, ""); /* Merge any potential empty entries together. */ @@ -667,7 +657,7 @@ uint32_t min_entry_size = cbfs_calculate_file_header_size(""); uint32_t len, header_offset; uint32_t align = image->has_header ? image->header.align : - CBFS_ENTRY_ALIGNMENT; + CBFS_ALIGNMENT; uint32_t header_size = ntohl(header->offset); header_offset = content_offset - header_size; @@ -682,7 +672,7 @@ if (header_offset - addr > min_entry_size) { DEBUG("|min|...|header|content|... <create new entry>\n"); len = header_offset - addr - min_entry_size; - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, len, ""); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); entry = cbfs_find_next_entry(image, entry); addr = cbfs_get_entry_addr(image, entry); @@ -741,7 +731,7 @@ buffer_size(&image->buffer) - sizeof(int32_t)) { len -= sizeof(int32_t); } - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, len, ""); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); return 0; } @@ -777,7 +767,7 @@ entry = cbfs_find_next_entry(image, entry)) { entry_type = ntohl(entry->type); - if (entry_type != CBFS_COMPONENT_NULL) + if (entry_type != CBFS_TYPE_NULL) continue; addr = cbfs_get_entry_addr(image, entry); @@ -1352,10 +1342,10 @@ if (do_processing) { int (*make_elf)(struct buffer *, uint32_t) = NULL; switch (ntohl(entry->type)) { - case CBFS_COMPONENT_STAGE: + case CBFS_TYPE_STAGE: make_elf = cbfs_stage_make_elf; break; - case CBFS_COMPONENT_SELF: + case CBFS_TYPE_SELF: make_elf = cbfs_payload_make_elf; break; } @@ -1389,7 +1379,7 @@ } DEBUG("cbfs_remove_entry: Removed %s @ 0x%x\n", entry->filename, cbfs_get_entry_addr(image, entry)); - entry->type = htonl(CBFS_COMPONENT_DELETED); + entry->type = htonl(CBFS_TYPE_DELETED); cbfs_walk(image, cbfs_merge_empty_entry, NULL); return 0; } @@ -1513,28 +1503,21 @@ decompressed_size ); - struct cbfs_file_attr_hash *hash = NULL; - while ((hash = cbfs_file_get_next_hash(entry, hash)) != NULL) { - unsigned int hash_type = ntohl(hash->hash_type); - if (hash_type >= CBFS_NUM_SUPPORTED_HASHES) { - fprintf(fp, "invalid hash type %d\n", hash_type); + struct cbfs_file_attr_hash *attr = NULL; + while ((attr = cbfs_file_get_next_hash(entry, attr)) != NULL) { + size_t hash_len = vb2_digest_size(attr->hash.algo); + if (!hash_len) { + fprintf(fp, "invalid/unsupported hash algorithm: %d\n", + attr->hash.algo); break; } - size_t hash_len = widths_cbfs_hash[hash_type]; - char *hash_str = bintohex(hash->hash_data, hash_len); - uint8_t local_hash[hash_len]; - if (vb2_digest_buffer(CBFS_SUBHEADER(entry), - ntohl(entry->len), hash_type, local_hash, - hash_len) != VB2_SUCCESS) { - fprintf(fp, "failed to hash '%s'\n", name); - free(hash_str); - break; - } - int valid = memcmp(local_hash, hash->hash_data, hash_len) == 0; + char *hash_str = bintohex(attr->hash.raw, hash_len); + int valid = vb2_hash_verify(CBFS_SUBHEADER(entry), + ntohl(entry->len), &attr->hash) == VB2_SUCCESS; const char *valid_str = valid ? "valid" : "invalid"; fprintf(fp, " hash %s:%s %s\n", - get_hash_attr_name(hash_type), + vb2_get_hash_algorithm_name(attr->hash.algo), hash_str, valid_str); free(hash_str); } @@ -1549,12 +1532,12 @@ /* note the components of the subheader may be in host order ... */ switch (ntohl(entry->type)) { - case CBFS_COMPONENT_STAGE: + case CBFS_TYPE_STAGE: cbfs_print_stage_info((struct cbfs_stage *) CBFS_SUBHEADER(entry), fp); break; - case CBFS_COMPONENT_SELF: + case CBFS_TYPE_SELF: payload = (struct cbfs_payload_segment *) CBFS_SUBHEADER(entry); while (payload) { @@ -1650,8 +1633,8 @@ /* Loop until non-empty entry is found, starting from the current entry. After the loop, next_addr points to the next non-empty entry. */ next = entry; - while (ntohl(next->type) == CBFS_COMPONENT_DELETED || - ntohl(next->type) == CBFS_COMPONENT_NULL) { + while (ntohl(next->type) == CBFS_TYPE_DELETED || + ntohl(next->type) == CBFS_TYPE_NULL) { next = cbfs_find_next_entry(image, next); if (!next) break; @@ -1672,7 +1655,7 @@ uint32_t addr = cbfs_get_entry_addr(image, entry); size_t len = next_addr - addr - cbfs_calculate_file_header_size(""); DEBUG("join_empty_entry: [0x%x, 0x%x) len=%zu\n", addr, next_addr, len); - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); + cbfs_create_empty_entry(entry, CBFS_TYPE_NULL, len, ""); return 0; } @@ -1766,8 +1749,7 @@ struct cbfs_file *entry) { uint32_t addr = cbfs_get_entry_addr(image, entry); - int align = image->has_header ? image->header.align : - CBFS_ENTRY_ALIGNMENT; + int align = image->has_header ? image->header.align : CBFS_ALIGNMENT; assert(entry && cbfs_is_valid_entry(image, entry)); addr += ntohl(entry->offset) + ntohl(entry->len); addr = align_up(addr, align); @@ -1808,8 +1790,8 @@ struct cbfs_file *cbfs_create_file_header(int type, size_t len, const char *name) { - struct cbfs_file *entry = malloc(MAX_CBFS_FILE_HEADER_BUFFER); - memset(entry, CBFS_CONTENT_DEFAULT_VALUE, MAX_CBFS_FILE_HEADER_BUFFER); + struct cbfs_file *entry = malloc(CBFS_METADATA_MAX_SIZE); + memset(entry, CBFS_CONTENT_DEFAULT_VALUE, CBFS_METADATA_MAX_SIZE); memcpy(entry->magic, CBFS_FILE_MAGIC, sizeof(entry->magic)); entry->type = htonl(type); entry->len = htonl(len); @@ -1882,7 +1864,7 @@ next = cbfs_file_next_attr(header, attr); } while (next != NULL); uint32_t header_size = ntohl(header->offset) + size; - if (header_size > MAX_CBFS_FILE_HEADER_BUFFER) { + if (header_size > CBFS_METADATA_MAX_SIZE) { DEBUG("exceeding allocated space for cbfs_file headers"); return NULL; } @@ -1904,35 +1886,31 @@ ntohl(attr->len)); } header->offset = htonl(header_size); - memset(attr, CBFS_CONTENT_DEFAULT_VALUE, size); + /* Attributes are expected to be small (much smaller than a flash page) + and not really meant to be overwritten in-place. To avoid surprising + values in reserved fields of attribute structures, initialize them to + 0, not 0xff. */ + memset(attr, 0, size); attr->tag = htonl(tag); attr->len = htonl(size); return attr; } int cbfs_add_file_hash(struct cbfs_file *header, struct buffer *buffer, - enum vb2_hash_algorithm hash_type) + enum vb2_hash_algorithm alg) { - uint32_t hash_index = hash_type; - - if (hash_index >= CBFS_NUM_SUPPORTED_HASHES) + if (!vb2_digest_size(alg)) return -1; - unsigned hash_size = widths_cbfs_hash[hash_type]; - if (hash_size == 0) - return -1; - - struct cbfs_file_attr_hash *attrs = + struct cbfs_file_attr_hash *attr = (struct cbfs_file_attr_hash *)cbfs_add_file_attr(header, - CBFS_FILE_ATTR_TAG_HASH, - sizeof(struct cbfs_file_attr_hash) + hash_size); + CBFS_FILE_ATTR_TAG_HASH, cbfs_file_attr_hash_size(alg)); - if (attrs == NULL) + if (attr == NULL) return -1; - attrs->hash_type = htonl(hash_type); - if (vb2_digest_buffer(buffer_get(buffer), buffer_size(buffer), - hash_type, attrs->hash_data, hash_size) != VB2_SUCCESS) + if (vb2_hash_calculate(buffer_get(buffer), buffer_size(buffer), + alg, &attr->hash) != VB2_SUCCESS) return -1; return 0; @@ -1984,7 +1962,7 @@ size, page_size); size_t image_align = image->has_header ? image->header.align : - CBFS_ENTRY_ALIGNMENT; + CBFS_ALIGNMENT; if (page_size % image_align) WARN("%s: Page size (%#zx) not aligned with CBFS image (%#zx).\n", __func__, page_size, image_align); @@ -2020,7 +1998,7 @@ entry = cbfs_find_next_entry(image, entry)) { uint32_t type = ntohl(entry->type); - if (type != CBFS_COMPONENT_NULL) + if (type != CBFS_TYPE_NULL) continue; addr = cbfs_get_entry_addr(image, entry); diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 1bb3c68..6ff0746 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -54,7 +54,7 @@ /* Creates an empty CBFS image by given size, and description to its content * (bootblock, align, header location, starting offset of CBFS entries). * The output image will contain a valid cbfs_header, with one cbfs_file - * entry with type CBFS_COMPONENT_NULL, with max available size. + * entry with type CBFS_TYPE_NULL, with max available size. * Only call this if you want a legacy CBFS with a master header. * Returns 0 on success, otherwise nonzero. */ int cbfs_legacy_image_create(struct cbfs_image *image, diff --git a/util/cbfstool/cbfscomptool.c b/util/cbfstool/cbfscomptool.c index 028893c..a1245b5 100644 --- a/util/cbfstool/cbfscomptool.c +++ b/util/cbfstool/cbfscomptool.c @@ -19,6 +19,7 @@ #include <strings.h> #include <time.h> +#include "cbfs.h" #include "common.h" const char *usage_text = "cbfs-compression-tool benchmark\n" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f15c65b..f97745e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -34,6 +34,7 @@ #include <commonlib/fsp.h> #include <commonlib/endian.h> #include <commonlib/helpers.h> +#include <vboot_host.h> #define SECTION_WITH_FIT_TABLE "BOOTBLOCK" @@ -86,7 +87,7 @@ bool machine_parseable; bool unprocessed; bool ibb; - enum comp_algo compression; + enum cbfs_compression compression; int precompression; enum vb2_hash_algorithm hash; /* For linux payloads */ @@ -198,7 +199,7 @@ /* Take care of the hash attribute if it is used */ if (param.hash != VB2_HASH_INVALID) - metadata_size += sizeof(struct cbfs_file_attr_hash); + metadata_size += cbfs_file_attr_hash_size(param.hash); int32_t address = cbfs_locate_entry(&image, data_size, param.pagesize, param.alignment, metadata_size); @@ -250,7 +251,7 @@ offset = convert_to_from_top_aligned(param.image_region, -offset); - header = cbfs_create_file_header(CBFS_COMPONENT_RAW, + header = cbfs_create_file_header(CBFS_TYPE_RAW, buffer.size, name); if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", @@ -351,7 +352,7 @@ * image is at 4GB == 0. */ h->bootblocksize = htonl(4); - h->align = htonl(CBFS_ENTRY_ALIGNMENT); + h->align = htonl(CBFS_ALIGNMENT); /* The offset and romsize fields within the master header are absolute * values within the boot media. As such, romsize needs to relfect * the end 'offset' for a CBFS. To achieve that the current buffer @@ -365,7 +366,7 @@ h->offset = htonl(offset); h->architecture = htonl(CBFS_ARCHITECTURE_UNKNOWN); - header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER, + header = cbfs_create_file_header(CBFS_TYPE_CBFSHEADER, buffer_size(&buffer), name); if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) { ERROR("Failed to add cbfs master header into ROM image.\n"); @@ -487,7 +488,7 @@ * Check if Intel CPU topswap is specified this will require a * second bootblock to be added. */ - if (type == CBFS_COMPONENT_BOOTBLOCK && param.topswap_size) + if (type == CBFS_TYPE_BOOTBLOCK && param.topswap_size) if (add_topswap_bootblock(&buffer, &offset)) return 1; @@ -522,10 +523,10 @@ /* care about the additional metadata that is added */ /* to the cbfs file and therefore set the position */ /* the real beginning of the data. */ - if (type == CBFS_COMPONENT_STAGE) + if (type == CBFS_TYPE_STAGE) attrs->position = htonl(offset + sizeof(struct cbfs_stage)); - else if (type == CBFS_COMPONENT_SELF) + else if (type == CBFS_TYPE_SELF) attrs->position = htonl(offset + sizeof(struct cbfs_payload)); else @@ -759,7 +760,7 @@ if (ret != 0) { ret = parse_fit_to_payload(buffer, &output, param.compression); if (ret == 0) - header->type = htonl(CBFS_COMPONENT_FIT); + header->type = htonl(CBFS_TYPE_FIT); } /* If it's not an FIT, see if it's a UEFI FV */ @@ -817,7 +818,7 @@ /* Set the alignment to 4KiB minimum for FSP blobs when no base address * is provided so that relocation can occur. */ - if (param.type == CBFS_COMPONENT_FSP) { + if (param.type == CBFS_TYPE_FSP) { if (!param.baseaddress_assigned) param.alignment = 4*1024; convert = cbfstool_convert_fsp; @@ -858,7 +859,7 @@ return cbfs_add_component(param.filename, param.name, - CBFS_COMPONENT_STAGE, + CBFS_TYPE_STAGE, param.baseaddress, param.headeroffset, cbfstool_convert_mkstage); @@ -868,7 +869,7 @@ { return cbfs_add_component(param.filename, param.name, - CBFS_COMPONENT_SELF, + CBFS_TYPE_SELF, param.baseaddress, param.headeroffset, cbfstool_convert_mkpayload); @@ -888,7 +889,7 @@ } return cbfs_add_component(param.filename, param.name, - CBFS_COMPONENT_SELF, + CBFS_TYPE_SELF, param.baseaddress, param.headeroffset, cbfstool_convert_mkflatpayload); @@ -1577,10 +1578,7 @@ break; } case 'A': { - int algo = cbfs_parse_hash_algo(optarg); - if (algo >= 0) - param.hash = algo; - else { + if (!vb2_lookup_hash_alg(optarg, &param.hash)) { ERROR("Unknown hash algorithm '%s'.\n", optarg); return 1; diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index f152104..8aac371 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -22,10 +22,10 @@ #include <string.h> #include <assert.h> +#include <commonlib/bsd/cbfs_serialized.h> #include <commonlib/helpers.h> #include <console/console.h> -/* Endianness */ #include "swab.h" #define IS_TOP_ALIGNED_ADDRESS(x) ((uint32_t)(x) > 0x80000000) @@ -160,47 +160,29 @@ typedef int (*decomp_func_ptr) (char *in, int in_len, char *out, int out_len, size_t *actual_size); -enum comp_algo { - CBFS_COMPRESS_NONE = 0, - CBFS_COMPRESS_LZMA = 1, - CBFS_COMPRESS_LZ4 = 2, -}; - -struct typedesc_t { - uint32_t type; - const char *name; -}; - -static const struct typedesc_t types_cbfs_compression[] = { - {CBFS_COMPRESS_NONE, "none"}, - {CBFS_COMPRESS_LZMA, "LZMA"}, - {CBFS_COMPRESS_LZ4, "LZ4"}, - {0, NULL}, -}; - -comp_func_ptr compression_function(enum comp_algo algo); -decomp_func_ptr decompression_function(enum comp_algo algo); +comp_func_ptr compression_function(enum cbfs_compression algo); +decomp_func_ptr decompression_function(enum cbfs_compression algo); uint64_t intfiletype(const char *name); /* cbfs-mkpayload.c */ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo); + enum cbfs_compression algo); int parse_fv_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo); + enum cbfs_compression algo); int parse_fit_to_payload(const struct buffer *input, struct buffer *output, - enum comp_algo algo); + enum cbfs_compression algo); int parse_bzImage_to_payload(const struct buffer *input, struct buffer *output, const char *initrd, - char *cmdline, enum comp_algo algo); + char *cmdline, enum cbfs_compression algo); int parse_flat_binary_to_payload(const struct buffer *input, struct buffer *output, uint32_t loadaddress, uint32_t entrypoint, - enum comp_algo algo); + enum cbfs_compression algo); /* cbfs-mkstage.c */ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, - enum comp_algo algo, uint32_t *location, + enum cbfs_compression algo, uint32_t *location, const char *ignore_section); /* location is TOP aligned. */ int parse_elf_to_xip_stage(const struct buffer *input, struct buffer *output, diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c index 9938094..52ae6df 100644 --- a/util/cbfstool/compress.c +++ b/util/cbfstool/compress.c @@ -83,7 +83,7 @@ return 0; } -comp_func_ptr compression_function(enum comp_algo algo) +comp_func_ptr compression_function(enum cbfs_compression algo) { comp_func_ptr compress; switch (algo) { @@ -103,7 +103,7 @@ return compress; } -decomp_func_ptr decompression_function(enum comp_algo algo) +decomp_func_ptr decompression_function(enum cbfs_compression algo) { decomp_func_ptr decompress; switch (algo) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 Gerrit-Change-Number: 41117 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: cbfs: Port cbfs_load() and cbfs_map() to new API
by Julius Werner (Code Review) 02 Dec '20

02 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39305 to review the following change. Change subject: cbfs: Port cbfs_load() and cbfs_map() to new API ...................................................................... cbfs: Port cbfs_load() and cbfs_map() to new API This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API directly, rather than through cbfs_boot_locate(). For cbfs_load() this means that attribute metadata does not need to be read twice. Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/lib/cbfs.c 3 files changed, 43 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39305/1 diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 85a75ab..7e309ec 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -155,3 +155,21 @@ }; return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); } + +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag) +{ + uint32_t offset = be32toh(mdata->h.attributes_offset); + uint32_t end = be32toh(mdata->h.offset); + + if (!offset) + return NULL; + + while (offset < end) { + struct cbfs_file_attribute *attr = (void *)mdata + offset; + if (be32toh(attr->tag) == attr_tag) + return attr; + offset += be32toh(attr->len); + } + + return NULL; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index df97009..4962cef 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -112,4 +112,7 @@ /* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); +/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian). */ +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index bece4d0..c3660aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -81,18 +81,19 @@ void *cbfs_map(const char *name, size_t *size) { - struct cbfsf fh; - size_t fsize; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL)) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return NULL; - fsize = region_device_sz(&fh.data); + size_t data_size = be32toh(mdata.h.len); if (size != NULL) - *size = fsize; + *size = data_size; - return rdev_mmap(&fh.data, 0, fsize); + return rdev_mmap(&cbd->rdev, data_offset, data_size); } int cbfs_unmap(void *mapping) @@ -216,21 +217,25 @@ size_t cbfs_load(const char *name, void *buf, size_t buf_size) { - struct cbfsf fh; - uint32_t compression_algo; - size_t decompressed_size; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL) < 0) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) - return 0; + uint32_t compression = CBFS_COMPRESS_NONE; + struct cbfs_file_attr_compression *attr = + cbfs_find_attr(&mdata, CBFS_FILE_ATTR_TAG_COMPRESSION); + if (attr) { + compression = be32toh(attr->compression); + if (buf_size < be32toh(attr->decompressed_size)) + return 0; + } - return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), - buf, buf_size, compression_algo); + return cbfs_load_and_decompress(&cbd->rdev, data_offset, + be32toh(mdata.h.len), buf, buf_size, + compression); } size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) -- To view, visit https://review.coreboot.org/c/coreboot/+/39305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Gerrit-Change-Number: 39305 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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