coreboot-gerrit June 2020

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Change in coreboot[master]: cbfs: Move more stuff into cbfs_boot_lookup()
by Julius Werner (Code Review) 02 Dec '20

02 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39327 to review the following change. Change subject: cbfs: Move more stuff into cbfs_boot_lookup() ...................................................................... cbfs: Move more stuff into cbfs_boot_lookup() cbfs_boot_locate() is supposed to be deprecated eventually, after slowly migrating all APIs to bypass it. That means common features (like RO-fallback or measurement) need to be moved to the new cbfs_boot_lookup(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a --- M src/lib/cbfs.c M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 3 files changed, 34 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39327/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 39db97a..ef29299 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -31,40 +31,47 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> -static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, - const char *name, union cbfs_mdata *mdata, size_t *data_offset) +static cb_err_t cbfs_boot_lookup(struct region_device *rdev, const char *name, + union cbfs_mdata *mdata, size_t *data_offset, bool force_ro) { + cb_err_t err; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); + if (!cbd || rdev_chain_full(rdev, &cbd->rdev)) + return CB_ERR; + if (CONFIG(NO_CBFS_MCACHE)) - return cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + err = cbfs_lookup(rdev, name, mdata, data_offset, NULL); else - return cbfs_mcache_lookup(&cbd->rdev, - cbd->mcache, cbd->mcache_size, - name, mdata, data_offset, NULL); + err = cbfs_mcache_lookup(rdev, cbd->mcache, cbd->mcache_size, + name, mdata, data_offset, NULL); + + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && + err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + return cbfs_boot_lookup(rdev, name, mdata, data_offset, true); + } + if (err) + return err; + + if (vboot_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) + return CB_ERR; + + return CB_SUCCESS; } int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); - if (!cbd) - return -1; - + struct region_device rdev; union cbfs_mdata mdata; size_t data_offset; - cb_err_t err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { - printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", - name); - if (!(cbd = cbfs_get_boot_device(true))) - return -1; - err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - } - if (err) + if (cbfs_boot_lookup(&rdev, name, &mdata, &data_offset, false)) return -1; size_t msize = be32toh(mdata.h.offset); - if (rdev_chain(&fh->metadata, &cbd->rdev, data_offset - msize, msize) || - rdev_chain(&fh->data, &cbd->rdev, data_offset, be32toh(mdata.h.len))) + if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) return -1; if (type) { if (!*type) @@ -73,9 +80,6 @@ return -1; } - if (vboot_measure_cbfs_hook(fh, name)) - return -1; - return 0; } diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index f68ab0a4..75c5662 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -157,19 +157,16 @@ return false; } -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name) +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type) { uint32_t pcr_index; - uint32_t cbfs_type; struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; if (!vboot_logic_executed()) return 0; - cbfsf_file_type(fh, &cbfs_type); - cbfs_file_data(&rdev, fh); - switch (cbfs_type) { case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..8e6c076 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -49,13 +49,14 @@ #if CONFIG(VBOOT_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) - * fh is the cbfs file handle to measure + * rdev covers the file data (not metadata) * return 0 if successful, else an error */ -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type); #else -#define vboot_measure_cbfs_hook(fh, name) 0 +#define vboot_measure_cbfs_hook(rdev, name, cbfs_type) 0 #endif #endif /* __VBOOT_VBOOT_CRTM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a Gerrit-Change-Number: 39327 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet p...
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40495 ) Change subject: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches ...................................................................... AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches These scripts will help you to securely and conveniently apply five changes CB:40484, CB:40485, CB:40490, CB:40488, CB:40489 to add the DDR3 XMP support. Save to ./coreboot/ then run ./get_xmp_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d --- A apply_xmp_patches.sh A check_xmp_patches.sh A get_xmp_patches.sh A sha256sums_xmp_correct.txt 4 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40495/1 diff --git a/apply_xmp_patches.sh b/apply_xmp_patches.sh new file mode 100755 index 0000000..4320ee2 --- /dev/null +++ b/apply_xmp_patches.sh @@ -0,0 +1,27 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +patch -p1 < "./413db53.diff" +### diff --git a/check_xmp_patches.sh b/check_xmp_patches.sh new file mode 100755 index 0000000..88a0375 --- /dev/null +++ b/check_xmp_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +rm -f "./sha256sums_xmp_my.txt" +sha256sum "./b8b7fb7.diff" > "./sha256sums_xmp_my.txt" +sha256sum "./a81f3eb.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./bf4bd85.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./3b9288e.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./413db53.diff" >> "./sha256sums_xmp_my.txt" +if cmp -s "./sha256sums_xmp_my.txt" "./sha256sums_xmp_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_xmp_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_xmp_my.txt and ./sha256sums_xmp_correct.txt" + exit 1 +fi +# diff --git a/get_xmp_patches.sh b/get_xmp_patches.sh new file mode 100755 index 0000000..34eba96 --- /dev/null +++ b/get_xmp_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +rm -f "./b8b7fb7.diff" +wget "https://review.coreboot.org/changes/40484/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +rm -f "./a81f3eb.diff" +wget "https://review.coreboot.org/changes/40485/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +rm -f "./bf4bd85.diff" +wget "https://review.coreboot.org/changes/40490/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +rm -f "./3b9288e.diff" +wget "https://review.coreboot.org/changes/40488/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +rm -f "./413db53.diff" +wget "https://review.coreboot.org/changes/40489/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./413db53.diff" +### diff --git a/sha256sums_xmp_correct.txt b/sha256sums_xmp_correct.txt new file mode 100644 index 0000000..e3ccb04 --- /dev/null +++ b/sha256sums_xmp_correct.txt @@ -0,0 +1,5 @@ +0b19e790c27cc4344f5427e2af62b3d8f5c729c49a528709689e4c1536e55daf ./b8b7fb7.diff +0f5816d40a56e5fe3201e539c2f6cae51a03ae606085731f3c70eb7f2a007bd5 ./a81f3eb.diff +6749bbe5a8a33b0a32d214e32ffba4b6d7df740c73fd674c344653041e5103aa ./bf4bd85.diff +4579e9a7f3454e4909789b56d2fd6422129e31185a363cf6cd13485907b82b1d ./3b9288e.diff +d5161276160d1cf4d77a5252cb7f9855d2ff5de00dedea28790627d9a144b556 ./413db53.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/40495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d Gerrit-Change-Number: 40495 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40489 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Took Crucial BLT8G3D1869DT1TX0 XMP 1 (1866MHz 9-9-9-27) as an example. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 --- M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 10 files changed, 337 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/40489/1 diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 817c4b3..461b04d 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -38,6 +38,119 @@ help XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! +config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + bool "CUSTOM" + help + Custom memory profile. Use the XMP SPD values as the base, if available. + +if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + +config CUSTOM_SPD_DIVIDENT + int "[10]: Medium Timebase (MTB) Dividend" + default 1 + range 1 255 + +config CUSTOM_SPD_DIVISOR + int "[11]: Medium Timebase (MTB) Divisor" + default 14 + range 1 255 + +config CUSTOM_SPD_TCK + int "[12]: SDRAM Minimum Cycle Time, tCK" + default 15 + range 1 255 + +config CUSTOM_SPD_CASLO + int "[14]: CAS Latencies Supported, Lower Byte" + default 124 + range 0 255 + +config CUSTOM_SPD_CASHI + int "[15]: CAS Latencies Supported, Higher Byte" + default 0 + range 0 255 + +config CUSTOM_SPD_TAA + int "[16]: Min CAS Latency Time, tAA" + default 132 + range 1 255 + +config CUSTOM_SPD_TWR + int "[17]: Min Write Recovery Time, tWR" + default 210 + range 1 255 + +config CUSTOM_SPD_TRCD + int "[18]: Min RAS# to CAS# Delay Time, tRCD" + default 132 + range 1 255 + +config CUSTOM_SPD_TRRD + int "[19]: Min Row Active to Row Active Delay Time, tRRD" + default 84 + range 1 255 + +config CUSTOM_SPD_TRP + int "[20]: Min Row Precharge Delay Time, tRP" + default 132 + range 1 255 + +config CUSTOM_SPD_UPPER_TRC + int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC" + default 2 + range 0 16 + +config CUSTOM_SPD_UPPER_TRAS + int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS" + default 1 + range 0 16 + +config CUSTOM_SPD_TRAS + int "[22]: Min Active to Precharge Delay Time, LOWER tRAS" + default 138 + range 1 255 + +config CUSTOM_SPD_TRC + int "[23]: Min Active to Active/Refresh Delay, LOWER tRC" + default 181 + range 1 255 + +if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + +config CUSTOM_SPD_TWTR + int "[26]: Min Internal Write to Read Command Delay, tWTR" + default 105 + range 1 255 + +config CUSTOM_SPD_TRTP + int "[27]: Min Internal Read to Precharge Command Delay, tRTP" + default 105 + range 1 255 + +config CUSTOM_SPD_UPPER_TFAW + int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW" + default 1 + range 0 16 + +config CUSTOM_SPD_TFAW + int "[29]: Min Four Activate Window Delay Time, tFAW" + default 164 + range 1 255 + +endif + endchoice endif diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 86fe800..e38e675 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -798,6 +798,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c index 392b7fc..cf3942b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c @@ -64,6 +64,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -101,6 +102,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -293,6 +304,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -369,6 +434,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index c7f490d..2797f80 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 70c2135..82ebab7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2027,6 +2027,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c index f2e5848..1030d7a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -302,6 +313,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -378,6 +443,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index bbe5c12..ede7067 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,7 +94,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 90c4e3f..4349e4e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -996,6 +996,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c index d497aec..dfc1e35 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -314,6 +325,62 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TRFC_LO] = CONFIG_CUSTOM_SPD_TRFC_LO; + Buffer[SPD_TRFC_HI] = CONFIG_CUSTOM_SPD_TRFC_HI; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -390,6 +457,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bc608a5..472add0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 -- To view, visit https://review.coreboot.org/c/coreboot/+/40489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Gerrit-Change-Number: 40489 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40488 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles XMP memory profiles support which has been tested on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/40488/1 diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..7f85852 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -42,6 +42,10 @@ endchoice +if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" endif diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..817c4b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,43 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..c7f490d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..bbe5c12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -102,18 +104,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..bc608a5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,82 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +188,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38 -#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *----------------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/40488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Gerrit-Change-Number: 40488 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: [WIP] soc/amd/picasso: add FSP binary location
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42472 ) Change subject: [WIP] soc/amd/picasso: add FSP binary location ...................................................................... [WIP] soc/amd/picasso: add FSP binary location Since the blobs haven't landed yet, it is expected that this breaks the Jenkins build. Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Kconfig 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42472/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..bf809f8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -60,6 +60,20 @@ string default "src/soc/amd/picasso/memlayout.ld" +config FSP_M_FILE + string "FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" + help + The path and filename of the FSP-M binary for this platform. + +config FSP_S_FILE + string "FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" + help + The path and filename of the FSP-S binary for this platform. + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/42472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Gerrit-Change-Number: 42472 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: arch/x86/car.ld: Check for out of bound on no-XIP stages
by Arthur Heymans (Code Review) 02 Dec '20

02 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36623 ) Change subject: arch/x86/car.ld: Check for out of bound on no-XIP stages ...................................................................... arch/x86/car.ld: Check for out of bound on no-XIP stages Check that stages running in CAR have their start and end in CAR. Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36623/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c..e68beb3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -119,4 +119,9 @@ #endif #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE) +_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); +_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); +#endif + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Gerrit-Change-Number: 36623 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/dedede: Add ACPI support for camera in waddledee
by Varshit B Pandya (Code Review) 01 Dec '20

01 Dec '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42205 ) Change subject: mb/google/dedede: Add ACPI support for camera in waddledee ...................................................................... mb/google/dedede: Add ACPI support for camera in waddledee 1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI9734 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledee board and able to capture image using world facing camera and user facing camera. Change-Id: I3f6b490832d2c34c86512384eb7470f13a212a66 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl 6 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/42205/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 25ad61f..b6e1d64 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -18,6 +18,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_WHEELIE bool "Wheelie" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl new file mode 100644 index 0000000..90c7d58 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam0.asl @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA0, Zero) + + /* Method to turn off Power Rails */ + Method (POFF, 0) + { + /* Disable PP1200 lane */ + CTXS(GPP_D14) + /* Disable PP2800 lane */ + CTXS(GPP_D13) + } + + Method (PON, 0) + { + /* Enable PP2800 lane */ + STXS(GPP_D13) + /* Enable PP1200 lane */ + STXS(GPP_D14) + } + + PowerResource (FCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(1, 1) /* Clock 1, 19.2MHz */ + IF(!STA1) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D12) + Sleep(5) /* 5 us */ + /* Deassert Reset */ + STXS(GPP_D12) + Sleep(5) /* 5 us */ + STA0 = 1 + } + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(1) /* Clock 1 */ + /* Assert Reset */ + CTXS(GPP_D12) + IF(!STA1) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA0 = 0 + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA0) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hadware ID */ + + Name (_UID, 0x03) /* _UID: Unique ID */ + + Name (_DDN, "DW9714 VCM") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Setting */ + { + I2cSerialBusV2 (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , Exclusive, + ) + }) + + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3Hot */ + { + FCPR + }) + + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), /* Device Properties for _DSD */ + Package(0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl new file mode 100644 index 0000000..3e76197 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/cam1.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.I2C3) +{ + Name (STA1, Zero) + + PowerResource (RCPR, 0x00, 0x0000) + { + Method (_ON, 0, Serialized) /* _ON_: Power On */ + { + MCON(0, 1) /* Clock 0, 19.2MHz */ + /* Check if another sensor is ON */ + IF(!STA0) + { + /* Other sensor is OFF, so turn on power signals. */ + PON() + } + /* Assert Reset */ + CTXS(GPP_D15) + Sleep(5) /* 5 us */ + /* DeAssert Reset */ + STXS(GPP_D15) + Sleep(5) /* 5 us */ + STA1 = 1 + } + + Method (_OFF, 0, Serialized) /* _OFF_: Power Off */ + { + MCOF(0) /* Clock 0 */ + /* Assert Reset */ + CTXS(GPP_D15) + IF(!STA0) + { + /* Other sensor is OFF, so turn off power signals. */ + POFF() + } + STA1 = 0 + } + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA1) + } + } + + Device(CAM1) + { + Name (_HID, "OVTI9734") /* _HID: Hardware ID */ + + Name (_UID, Zero) /* _UID: Unique ID */ + + Name (_DDN, "Ov 9734 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x0ABA9500 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl new file mode 100644 index 0000000..51b4ebc --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/camera.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..89ccb48 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM0, + Zero, + Zero + } + } + } + }) + + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x01) + { + One, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C3.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..8d37674 --- /dev/null +++ b/src/mainboard/google/dedede/variants/waddledee/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) /* _ADR: Address */ + + Name (_DDN, "Camera and Imaging Subsystem") /* _DDN: DOS Device Name */ + } +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f6b490832d2c34c86512384eb7470f13a212a66 Gerrit-Change-Number: 42205 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

8 25

Change in coreboot[master]: arch/x86: Link NO_XIP_EARLY_STAGES like other stages
by Arthur Heymans (Code Review) 30 Nov '20

30 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36612 ) Change subject: arch/x86: Link NO_XIP_EARLY_STAGES like other stages ...................................................................... arch/x86: Link NO_XIP_EARLY_STAGES like other stages If stages are not run XIP they can be linked like other stages, which includes a (*.data) section. Change-Id: Ib165058abfb07e385461cdcca4aef31928ec7572 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/rules.h M src/lib/program.ld 4 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36612/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index c36dc1c..a838b6d 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -32,7 +32,8 @@ /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp - /* clear .bss section as it is not shared */ + /* clear .bss section as it is not shared if stages are run XIP*/ +#if !ENV_STAGE_HAS_DATA_SECTION cld xor %eax, %eax movl $(_ebss), %ecx @@ -40,6 +41,7 @@ sub %edi, %ecx shrl $2, %ecx rep stosl +#endif #if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c..a68b635 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -69,6 +69,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ +#if !ENV_STAGE_HAS_DATA_SECTION . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; #if ENV_STAGE_HAS_BSS_SECTION @@ -84,6 +85,7 @@ #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; +#endif _car_unallocated_start = .; #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) diff --git a/src/include/rules.h b/src/include/rules.h index 0436198..fe162f8 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -274,7 +274,7 @@ /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) /* No .data sections with execute-in-place from ROM. */ -#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +#define ENV_STAGE_HAS_DATA_SECTION (!ENV_CACHE_AS_RAM || CONFIG(NO_XIP_EARLY_STAGES)) /* No .bss sections for stage with CAR teardown. */ #define ENV_STAGE_HAS_BSS_SECTION !(ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION)) #else diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48..d323ac1 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -125,7 +125,7 @@ } #endif -#if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM +#if ENV_STAGE_HAS_BSS_SECTION && ENV_STAGE_HAS_DATA_SECTION .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/36612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib165058abfb07e385461cdcca4aef31928ec7572 Gerrit-Change-Number: 36612 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD
by Idwer Vollering (Code Review) 26 Nov '20

26 Nov '20

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37767 ) Change subject: util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD ...................................................................... util/inteltool: fix Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1 on FreeBSD Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/inteltool/Makefile M util/inteltool/inteltool.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37767/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index cd02fa8..918b6ec 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -23,6 +23,7 @@ INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes +CFLAGS += -Wno-unused-function LDFLAGS += -lpci -lz CPPFLAGS += -I$(top)/src/commonlib/include diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..81ebc72 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -370,7 +370,7 @@ #define rdmsr freebsd_rdmsr #define wrmsr freebsd_wrmsr typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); +static msr_t freebsd_rdmsr(int addr); int freebsd_wrmsr(int addr, msr_t msr); #endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/37767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Gerrit-Change-Number: 37767 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/northbridge/amd/agesa: fix the device resource assignment
by Mike Banon (Code Review) 24 Nov '20

24 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41431 ) Change subject: src/northbridge/amd/agesa: fix the device resource assignment ...................................................................... src/northbridge/amd/agesa: fix the device resource assignment The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). This successfully fixes the boot problems of fam15tn A88XM-E but fails to fix a fam16kb AM1I-A. After fam16kb will be fixed, this change should be updated with a fix for fam14 as well. Inspired by CB:41369. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5df6d0150e777cd21f6f9a2fc776f3548da8201d --- M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 2 files changed, 12 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41431/1 diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9d41e7a..0194ea8 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -666,6 +666,8 @@ u32 reset_memhole = 1; #endif + domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -749,17 +751,18 @@ } add_uma_resource_below_tolm(dev, 7); - +/* for (link = dev->link_list; link; link = link->next) { if (link->children) { assign_resources(link); } } +*/ } static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, + .read_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cedc7da..0467b27 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -683,6 +683,8 @@ u32 reset_memhole = 1; #endif + domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -768,11 +770,13 @@ add_uma_resource_below_tolm(dev, 7); +/* for (link = dev->link_list; link; link = link->next) { if (link->children) { assign_resources(link); } } +*/ } static const char *domain_acpi_name(const struct device *dev) @@ -784,8 +788,8 @@ } static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, + .read_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df6d0150e777cd21f6f9a2fc776f3548da8201d Gerrit-Change-Number: 41431 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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