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Change in coreboot[master]: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2
by Philipp Hug (Code Review) 07 Aug '23

07 Aug '23

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36487 ) Change subject: WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 ...................................................................... WIP: mb/riscv-qemu: Switch to -pflash option in Qemu > 4.2 Instead of loading coreboot in the RAM, newer Qemu version support providing it as flash using the -pflash option. Currently qemu limits the flash size to 2*16MiB. This will hopefully be changed to 2*32MiB before release of 4.2. Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 --- M Documentation/mainboard/emulation/qemu-riscv.md M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/qemu-riscv/rom_media.c 5 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/36487/1 diff --git a/Documentation/mainboard/emulation/qemu-riscv.md b/Documentation/mainboard/emulation/qemu-riscv.md index 3aad816..faae1e5 100644 --- a/Documentation/mainboard/emulation/qemu-riscv.md +++ b/Documentation/mainboard/emulation/qemu-riscv.md @@ -2,7 +2,11 @@ ## Building coreboot and running it in Qemu +### Qemu >= 4.2 - Configure coreboot and run `make` as usual +- Run `qemu-system-riscv64 -M virt -m 1024M -nographic -pflash build/coreboot.rom` + +### Qemu < 4.2 - Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to convert coreboot to an ELF that Qemu can load - Run `qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf` diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index fa6dccc..7d6fe48 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -12,11 +12,6 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -# To execute, do: -# util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf -# qemu-system-riscv64 -M virt -m 1024M -nographic -kernel build/coreboot.elf - - if BOARD_EMULATION_QEMU_RISCV_RV64 config BOARD_EMULATION_QEMU_RISCV @@ -65,19 +60,6 @@ # ugly, but CBFS is placed in DRAM... config OPENSBI_TEXT_START hex - default 0x80010000 if COREBOOT_ROMSIZE_KB_64 - default 0x80020000 if COREBOOT_ROMSIZE_KB_128 - default 0x80040000 if COREBOOT_ROMSIZE_KB_256 - default 0x80080000 if COREBOOT_ROMSIZE_KB_512 - default 0x80100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x80200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x80400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x80600000 if COREBOOT_ROMSIZE_KB_6144 - default 0x80800000 if COREBOOT_ROMSIZE_KB_8192 - default 0x80a00000 if COREBOOT_ROMSIZE_KB_10240 - default 0x80c00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x81000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x82000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x84000000 if COREBOOT_ROMSIZE_KB_65536 + default 0x80000000 endif # BOARD_EMULATION_QEMU_RISCV diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h index fd8c136..4bb5e98 100644 --- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h +++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h @@ -17,4 +17,5 @@ #define QEMU_VIRT_PLIC 0x0c000000 #define QEMU_VIRT_UART0 0x10000000 #define QEMU_VIRT_VIRTIO 0x10001000 +#define QEMU_VIRT_FLASH 0x20000000 #define QEMU_VIRT_DRAM 0x80000000 diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index b29bc14..46f360f 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -17,26 +17,24 @@ #include <arch/header.ld> #include <mainboard/addressmap.h> -// Stages start after CBFS in DRAM -#define STAGES_START (QEMU_VIRT_DRAM + CONFIG_ROM_SIZE) +#define FLASH_START(addr) SYMBOL(flash, addr) +#define FLASH_END(addr) SYMBOL(eflash, addr) SECTIONS { - // the virt target doesn't emulate flash and just puts the CBFS into DRAM. - // fake SRAM where CBFS resides. It's only done for better integration. - SRAM_START(QEMU_VIRT_DRAM) - BOOTBLOCK(QEMU_VIRT_DRAM, 64K) - // CBFS goes here - SRAM_END(STAGES_START) - DRAM_START(STAGES_START) + FLASH_START(QEMU_VIRT_FLASH) + BOOTBLOCK(QEMU_VIRT_FLASH, 64K) + FLASH_END(QEMU_VIRT_FLASH + 64K) -#if ENV_ROMSTAGE - ROMSTAGE(STAGES_START, 128K) -#endif + DRAM_START(QEMU_VIRT_DRAM) #if ENV_RAMSTAGE - REGION(opensbi, STAGES_START, 128K, 4K) + REGION(opensbi, QEMU_VIRT_DRAM, 128K, 4K) #endif - PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) - RAMSTAGE(STAGES_START + 200K, 16M) - STACK(STAGES_START + 200K + 16M, 4K) +#if ENV_ROMSTAGE + ROMSTAGE(QEMU_VIRT_DRAM + 128K, 128K) +#endif + // TODO, drop the 15M hack + RAMSTAGE(QEMU_VIRT_DRAM + 256K, 15M) + PRERAM_CBMEM_CONSOLE(QEMU_VIRT_DRAM + 256K + 15M, 8K) + STACK(QEMU_VIRT_DRAM + 256K + 15M + 8K, 4K) } diff --git a/src/mainboard/emulation/qemu-riscv/rom_media.c b/src/mainboard/emulation/qemu-riscv/rom_media.c index 79e5ca8..7349ecb 100644 --- a/src/mainboard/emulation/qemu-riscv/rom_media.c +++ b/src/mainboard/emulation/qemu-riscv/rom_media.c @@ -15,11 +15,10 @@ */ #include <boot_device.h> #include <symbols.h> +#include <mainboard/addressmap.h> -/* This assumes that the CBFS resides at start of dram, which is true for the - * default configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(QEMU_VIRT_FLASH, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dd47d55bbaf26bddfc8378e48fa247c2f4c1988 Gerrit-Change-Number: 36487 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8
by Gaggery Tsai (Code Review) 07 Aug '23

07 Aug '23

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36685 ) Change subject: src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8 ...................................................................... src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8 This patches adds an initial commit for Intel CML-S RVP board support and rename the original CML-U RVP to RVPU to avoid confusing. It adds an additional GBE region in fmd file as well. TEST=build an image and boot to UEFI payload Change-Id: Idf723ada53dc441cb9fabc8efb1dcd3da8e0991c Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c A src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h 6 files changed, 398 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36685/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 13e55b3..13cba46 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,9 +1,9 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 config BOARD_SPECIFIC_OPTIONS def_bool y - select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU - select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU + select BOARD_ROMSIZE_KB_16384 if !(BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8) + select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -11,11 +11,11 @@ select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC - select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU select MAINBOARD_USES_IFD_EC_REGION - select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 config MAINBOARD_DIR string @@ -27,12 +27,13 @@ default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 - default "cml_u" if BOARD_INTEL_COMETLAKE_RVP + default "cml_u" if BOARD_INTEL_COMETLAKE_RVPU + default "cml_s" if BOARD_INTEL_COMETLAKE_RVP8 config MAINBOARD_PART_NUMBER string default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 default "cflrvp" config MAINBOARD_VENDOR @@ -42,7 +43,7 @@ config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP - default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP + default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8 default "Intel_cflrvp" config CHROMEOS @@ -53,7 +54,7 @@ config MAX_CPUS int - default 12 if BOARD_INTEL_COFFEELAKE_RVP11 + default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COMETLAKE_RVP8 default 16 if BOARD_INTEL_COFFEELAKE_RVP8 default 8 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 35c0f0f..3e5bf19 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -12,6 +12,10 @@ config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" select SOC_INTEL_COFFEELAKE -config BOARD_INTEL_COMETLAKE_RVP +config BOARD_INTEL_COMETLAKE_RVPU bool "-> Cometlake U DDR4 RVP" select SOC_INTEL_COMETLAKE +config BOARD_INTEL_COMETLAKE_RVP8 + bool "-> Cometlake S U-DIMM DDR4 RVP8" + select SOC_INTEL_COMETLAKE +~ diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index 62e0f5d..521716a 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -1,8 +1,9 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1081000 { + SI_ALL@0x0 0x1083000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x1000000 + SI_GBE@0x81000 0x2000 + SI_ME@0x83000 0x1000000 } SI_BIOS@0x1400000 0xC00000 { RW_SECTION_A@0x0 0x2d0000 { diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..0295d93 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2018 Intel Corporation. + * Copyright 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -264,7 +264,7 @@ /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVP) +#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVPU) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), @@ -466,8 +466,11 @@ /* F17 : USB2_OC_6 */ /* F18 : USB2_OC_7 */ /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), /* F22 : DDPF_C_TRLCLK */ /* F23 : DDPF_C_TRLDATA */ @@ -512,16 +515,27 @@ PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE), /* I0 : DDPB_HPD_0 */ + PAD_CFG_NF(GPP_I0, UP_20K, PLTRST, NF1), /* I1 : DDPC_HPD_1 */ + PAD_CFG_NF(GPP_I1, UP_20K, PLTRST, NF1), /* I2 : DPPD_HPD_2 */ + PAD_CFG_NF(GPP_I2, UP_20K, PLTRST, NF1), /* I3 : DPPE_HPD_3 */ + PAD_CFG_NF(GPP_I3, UP_20K, PLTRST, NF1), /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, UP_20K, PLTRST, NF1), /* I5 : DDPB_C_TRLCLK */ + PAD_CFG_NF(GPP_I5, UP_20K, PLTRST, NF1), /* I6 : DDPB_C_TRLDATA */ + PAD_CFG_NF(GPP_I6, UP_20K, PLTRST, NF1), /* I7 : DDPC_C_TRLCLK */ + PAD_CFG_NF(GPP_I7, UP_20K, PLTRST, NF1), /* I8 : DDPC_C_TRLDATA */ + PAD_CFG_NF(GPP_I8, UP_20K, PLTRST, NF1), /* I9 : DDPD_C_TRLCLK */ + PAD_CFG_NF(GPP_I9, UP_20K, PLTRST, NF1), /* I10 : DDPD_C_TRLDATA */ + PAD_CFG_NF(GPP_I10, UP_20K, PLTRST, NF1), /* I11 : M2_SKT2_C_FG0 */ /* I12 : M2_SKT2_CFG1 */ /* I13 : M2_SKT2_C_FG2 */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb new file mode 100644 index 0000000..7a93af0 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb @@ -0,0 +1,163 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "RMT" = "1" + register "ScsEmmcHs400Enabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC6)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC7)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "0" + register "PcieRpEnable[1]" = "0" + + # PCIe root port 3 for GBe LAN + register "PcieRpEnable[2]" = "1" + # RP 3 uses CLK SRC 8 + register "PcieClkSrcUsage[8]" = "2" + # ClkReq-to-ClkSrc mapping for CLK SRC 8 + register "PcieClkSrcClkReq[8]" = "8" + + # PCIe root port 4 for M.2 Wi-Fi + register "PcieRpEnable[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + # RP 4 uses CLK SRC 0 + register "PcieClkSrcUsage[0]" = "3" + # ClkReq-to-ClkSrc mapping for CLK SRC 0 + register "PcieClkSrcClkReq[0]" = "0" + + # PCIe root port 9 for X4 slot + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + # RP 9 uses CLK SRC 4 + register "PcieClkSrcUsage[4]" = "8" + + # PCIe root port 13 for GBe LAN + register "PcieRpEnable[12]" = "1" + # RP 13 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "12" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe root port 17 for X4 M.2 SSD + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[17]" = "1" + register "PcieRpEnable[18]" = "1" + register "PcieRpEnable[19]" = "1" + # RP 17 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "16" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe root port 21 for X4 slot + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" + # RP 21 uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "20" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + chip drivers/intel/wifi + register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + end + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C 0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on end # PCI Express Port 17 M.2 SSD + device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h new file mode 100644 index 0000000..f921f3f --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Damien Zammit <damien(a)zamaudio.com> + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + /* + * VerbTable: CFL Display Audio Codec + * Revision ID = 0xFF + * Codec Vendor: 0x8086280B + */ + + 0x8086280B, + 0xFFFFFFFF, + 0x00000005, + + /* + * Display Audio Verb Table + * For GEN9, the Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode + * PORT C - BIT[7:6] = 01b + */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + + /* ALC700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000015, + + /* + * HDA Codec Subsystem ID Verb-table + * HDA Codec Subsystem ID : 0x10EC112C + */ + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + /* + * Pin Widget Verb-table + * Widget node 0x01 + */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + /* Pin widget 0x12 - DMIC */ + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + /* Pin widget 0x13 - DMIC */ + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + /* Pin widget 0x14 - FRONT (Port-D) */ + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + /* Pin widget 0x15 - I2S-OUT */ + 0x01571C10, + 0x01571D01, + 0x01571E17, + 0x01571F90, + /* Pin widget 0x16 - LINE3 (Port-B) */ + 0x01671C20, + 0x01671D10, + 0x01671E01, + 0x01671F01, + /* Pin widget 0x17 - I2S-OUT */ + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + /* Pin widget 0x18 - I2S-IN */ + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971C30, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01B71C40, + 0x01B71D90, + 0x01B71EA1, + 0x01B71F01, + /* Pin widget 0x1D - PC-BEEP */ + 0x01D71C69, + 0x01D71D84, + 0x01D71E45, + 0x01D71F40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + /* Pin widget 0x21 - P-OUT (Port-I) */ + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F02, + /* Pin widget 0x29 - I2S-IN */ + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + /* + * Widget node 0x20 : MIC2-Vrefo-R and MIC2-vrefo-L + * to independent control + */ + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + /* + * Widget node 0x20 - 2 : Line2-JD gating MIC2-Vrefo-R, + * P-JD gating MIC2-vrefo-L + */ + 0x0205006B, + 0x02044260, + 0x05B50010, + 0x05B45C1D, + + /* Widget node 0X20 for ALC1305 */ + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf723ada53dc441cb9fabc8efb1dcd3da8e0991c Gerrit-Change-Number: 36685 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

9 44

Change in coreboot[master]: cpu/x86/smm: Remove usused Kconfig symbol
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36977 ) Change subject: cpu/x86/smm: Remove usused Kconfig symbol ...................................................................... cpu/x86/smm: Remove usused Kconfig symbol These platforms now use parallel mp. Change-Id: I73527a7feb6151d765295d6449262a2852b30177 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/smmhandler.S 2 files changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36977/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 85ebd83..5004cfd 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -137,13 +137,6 @@ endif -config SMM_LAPIC_REMAP_MITIGATION - bool - default y if NORTHBRIDGE_INTEL_I945 - default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM - default n - config SERIALIZED_SMM_INITIALIZATION bool default n diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index a2be7f2..6e8941e 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -75,36 +75,6 @@ #endif .global smm_handler_start smm_handler_start: -#if CONFIG(SMM_LAPIC_REMAP_MITIGATION) - /* Check if the LAPIC register block overlaps with SMM. - * This block needs to work without data accesses because they - * may be routed into the LAPIC register block. - * Code accesses, on the other hand, are never routed to LAPIC, - * which is what makes this work in the first place. - */ - mov $LAPIC_BASE_MSR, %ecx - rdmsr - and $(~0xfff), %eax - sub $(SMM_START), %eax - cmp $(SMM_END - SMM_START), %eax - ja untampered_lapic -1: - /* emit "Crash" on serial */ - mov $(CONFIG_TTYS0_BASE), %dx - mov $'C', %al - out %al, (%dx) - mov $'r', %al - out %al, (%dx) - mov $'a', %al - out %al, (%dx) - mov $'s', %al - out %al, (%dx) - mov $'h', %al - out %al, (%dx) - /* now crash for real */ - ud2 -untampered_lapic: -#endif movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx lgdtl %cs:(%bx) -- To view, visit https://review.coreboot.org/c/coreboot/+/36977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73527a7feb6151d765295d6449262a2852b30177 Gerrit-Change-Number: 36977 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: mainboard/google: Fix Hatch baseboard/gpio.c default mux
by Edward O'Callaghan (Code Review) 07 Aug '23

07 Aug '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36988 ) Change subject: mainboard/google: Fix Hatch baseboard/gpio.c default mux ...................................................................... mainboard/google: Fix Hatch baseboard/gpio.c default mux The schematics seem to suggest F20,F21,F11,F22 are all NC. BUG=b:144809606 Change-Id: Ide74ab6361f48f0e9c967b9e4318537f605bee2d Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36988/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 598600b..d8625b9 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -301,12 +301,12 @@ PAD_NC(GPP_F18, NONE), /* F19 : GPP_F19 ==> NC */ PAD_NC(GPP_F19, NONE), - /* F20 : PCH_MEM_STRAP0 */ - PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ - PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ - PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* F20 : GPP_F20 ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : GPP_F21 ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : GPP_F22 ==> NC */ + PAD_NC(GPP_F22, NONE), /* F23 : GPP_F23 ==> NC */ PAD_NC(GPP_F23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/36988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide74ab6361f48f0e9c967b9e4318537f605bee2d Gerrit-Change-Number: 36988 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: arch/riscv: Add error detection for supports_extension
by Xiang Wang (Code Review) 07 Aug '23

07 Aug '23

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37130 ) Change subject: arch/riscv: Add error detection for supports_extension ...................................................................... arch/riscv: Add error detection for supports_extension Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/arch/riscv/include/arch/cpu.h 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37130/1 diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 72a8a69..dd70af7 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -49,7 +49,7 @@ * */ int soc_supports_extension(char ext); -static inline int supports_extension(char ext) +static inline int supports_extension_imp(char ext) { uintptr_t isa = read_csr(misa); if (isa) @@ -58,6 +58,13 @@ return soc_supports_extension(ext); } +#define supports_extension(c)\ +({\ + _Static_assert(((c >= 'A') && (c <= 'Z')),\ + "The parameter of supports_extension must be [A-Z]");\ + supports_extension_imp(c);\ +}) + /* If the SOC does not implement misa, the read misa will be zero. * Such SOC requires a non-standard mechanism to detect machine XLEN. * If the soc does not implement misa, implement this function. -- To view, visit https://review.coreboot.org/c/coreboot/+/37130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d Gerrit-Change-Number: 37130 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: sb/intel/bd82x6x: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37138 ) Change subject: sb/intel/bd82x6x: Use common AHCI ...................................................................... sb/intel/bd82x6x: Use common AHCI Untested. Change-Id: I180c7f11bccfcd50340ba27cd926107765713e04 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/sata.c 2 files changed, 4 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/37138/1 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1c7e9b7..0c6b348 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -24,6 +24,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 3ec065f..06c0f3f 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -23,6 +23,7 @@ #include <pc80/mc146818rtc.h> #include <acpi/sata.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "pch.h" @@ -67,8 +68,6 @@ /* AHCI */ if (sata_mode == 0) { - u8 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -101,32 +100,8 @@ ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ - if (config->sata_interface_speed_support) - { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x24); - reg32 &= ~0x00000002; - write32(abar + 0x24, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); + sb_ahci_init(dev, config->sata_port_map, false, false, + config->sata_interface_speed_support, false, 5); } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I180c7f11bccfcd50340ba27cd926107765713e04 Gerrit-Change-Number: 37138 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/lynxpoint: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37139 ) Change subject: sb/intel/lynxpoint: Use common AHCI ...................................................................... sb/intel/lynxpoint: Use common AHCI Untested. Change-Id: I9c46e85084996b430b077f4bc683a96df42bf41a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 5 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/37139/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ef071f2..03b9bbb 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -21,6 +21,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 75bfbde..911575b 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -21,6 +21,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/ahci.h> + #include "chip.h" #include "pch.h" @@ -94,8 +96,6 @@ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if (config->sata_ahci) { - u32 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -154,31 +154,8 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void) read32(abar + 0x03); /* Read back 1 */ - (void) read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ - if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - } else { - reg32 &= ~0x00000002; - } - write32(abar + 0x09, reg32); + sb_ahci_init(dev, config->sata_port_map, pch_is_lp(), false, 0, + pch_is_lp() && !config->sata_devslp_disable, 0); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c46e85084996b430b077f4bc683a96df42bf41a Gerrit-Change-Number: 37139 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/ibexpeak: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37140 ) Change subject: sb/intel/ibexpeak: Use common AHCI ...................................................................... sb/intel/ibexpeak: Use common AHCI Untested. Change-Id: I772e69fe4400d921bea12806a0ab159b7cf5fbe1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/sata.c 2 files changed, 4 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/37140/1 diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f9723fb..c923714 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -26,6 +26,7 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..aa39a54 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -24,6 +24,7 @@ #include <pc80/mc146818rtc.h> #include <acpi/sata.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "pch.h" @@ -68,8 +69,6 @@ if (sata_mode == 0) { /* AHCI */ - u32 *abar; - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set Interrupt Line */ @@ -104,31 +103,8 @@ pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - /* Set ISS, if available */ - if (config->sata_interface_speed_support) { - reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) - << 20; - } - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended) */ - reg32 = read32(abar + 0x09); - reg32 &= ~0x00000002; - write32(abar + 0x09, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0x28); - reg32 &= ~0x00000005; - write32(abar + 0x28, reg32); + sb_ahci_init(dev, config->sata_port_map, false, false, + config->sata_interface_speed_support, false, 5); } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/37140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I772e69fe4400d921bea12806a0ab159b7cf5fbe1 Gerrit-Change-Number: 37140 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801ix: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37141 ) Change subject: sb/intel/i82801ix: Use common AHCI ...................................................................... sb/intel/i82801ix: Use common AHCI Untested. Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/sata.c 2 files changed, 12 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37141/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8363978..9ef680b 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index fa6c1df..7143fa2 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -24,60 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - struct resource *res; - - /* Initialize AHCI memory-mapped space */ - res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (!res) - return; - - u8 *abar = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -228,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Gerrit-Change-Number: 37141 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37142 ) Change subject: sb/intel/i82801gx: Use common AHCI ...................................................................... sb/intel/i82801gx: Use common AHCI Untested. Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/sata.c 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37142/1 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d95fc2..b8f8731 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,6 +20,7 @@ select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 47c35ba..f902013 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -20,6 +20,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> +#include <southbridge/intel/common/ahci.h> + #include "chip.h" #include "i82801gx.h" #include "sata.h" @@ -154,11 +156,7 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (ahci_res != NULL) - /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + sb_ahci_init(dev, config->sata_ports_implemented, false, false, 0, false, 0); break; default: case SATA_MODE_IDE_PLAIN: -- To view, visit https://review.coreboot.org/c/coreboot/+/37142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Gerrit-Change-Number: 37142 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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