coreboot-gerrit April 2020

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Change in coreboot[master]: ec/google/chromeec: Replace uses of ec_current_image with ec_image
by Furquan Shaikh (Code Review) 09 Apr '20

09 Apr '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40267 ) Change subject: ec/google/chromeec: Replace uses of ec_current_image with ec_image ...................................................................... ec/google/chromeec: Replace uses of ec_current_image with ec_image This change replaces all uses of ec_current_image with ec_image since Chromium OS EC has deprecated the use of enum ec_current_image and instead changed it to enum ec_image. BUG=b:149987779 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864 --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/40267/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 8bb3661..8d9c2ac 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1337,9 +1337,9 @@ } /* Cache and retrieve the EC image type (ro or rw) */ -enum ec_current_image google_chromeec_get_current_image(void) +enum ec_image google_chromeec_get_current_image(void) { - MAYBE_STATIC_BSS enum ec_current_image ec_image_type = EC_IMAGE_UNKNOWN; + MAYBE_STATIC_BSS enum ec_image ec_image_type = EC_IMAGE_UNKNOWN; if (ec_image_type != EC_IMAGE_UNKNOWN) return ec_image_type; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c40172a..f1caeb0 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -25,7 +25,7 @@ /* Check if EC supports feature EC_FEATURE_UNIFIED_WAKE_MASKS */ bool google_chromeec_is_uhepi_supported(void); int google_ec_running_ro(void); -enum ec_current_image google_chromeec_get_current_image(void); +enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); int google_chromeec_wait_for_displayport(long timeout); -- To view, visit https://review.coreboot.org/c/coreboot/+/40267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864 Gerrit-Change-Number: 40267 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Update ec_commands.h
by Furquan Shaikh (Code Review) 09 Apr '20

09 Apr '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40266 ) Change subject: ec/google/chromeec: Update ec_commands.h ...................................................................... ec/google/chromeec: Update ec_commands.h This change copies ec_commands.h directly from Chromium OS EC repo at sha b3c3f6a8f. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I940f5c7fe8ad4d989a1dfcd6da3ccf9fc151ec56 --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 183 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/40266/1 diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 7b5a067..18be8d3 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -39,12 +39,13 @@ extern "C" { #endif +#ifdef CHROMIUM_EC /* * CHROMIUM_EC is defined by the Makefile system of Chromium EC repository. * It is used to not include macros that may cause conflicts in foreign * projects (refer to crbug.com/984623). */ -#ifdef CHROMIUM_EC + /* * Include common.h for CONFIG_HOSTCMD_ALIGNED, if it's defined. This * generates more efficient code for accessing request/response structures on @@ -54,8 +55,18 @@ #include "compile_time_macros.h" #else - #define BUILD_ASSERT(_cond) +#endif /* CHROMIUM_EC */ + +#ifdef __KERNEL__ +#include <linux/limits.h> +#else +/* + * Defines macros that may be needed but are for sure defined by the linux + * kernel. This section is removed when cros_ec_commands.h is generated (by + * util/make_linux_ec_commands_h.sh). + * cros_ec_commands.h looks more integrated to the kernel. + */ #ifndef BIT #define BIT(nr) (1UL << (nr)) @@ -65,7 +76,7 @@ #define BIT_ULL(nr) (1ULL << (nr)) #endif -#endif /* CHROMIUM_EC */ +#endif /* __KERNEL__ */ /* * Current version of this protocol @@ -1073,10 +1084,22 @@ /* Get version number */ #define EC_CMD_GET_VERSION 0x0002 -enum ec_current_image { +#if !defined(CHROMIUM_EC) && !defined(__KERNEL__) +/* + * enum ec_current_image is deprecated and replaced by enum ec_image. This + * macro exists for backwards compatibility of external projects until they + * have been updated: b/149987779. + */ +#define ec_current_image ec_image +#endif + +enum ec_image { EC_IMAGE_UNKNOWN = 0, EC_IMAGE_RO, - EC_IMAGE_RW + EC_IMAGE_RW, + EC_IMAGE_RW_A = EC_IMAGE_RW, + EC_IMAGE_RO_B, + EC_IMAGE_RW_B }; /** @@ -1084,7 +1107,7 @@ * @version_string_ro: Null-terminated RO firmware version string. * @version_string_rw: Null-terminated RW firmware version string. * @reserved: Unused bytes; was previously RW-B firmware version string. - * @current_image: One of ec_current_image. + * @current_image: One of ec_image. */ struct ec_response_get_version { char version_string_ro[32]; @@ -1390,6 +1413,12 @@ * MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37, + /* + * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2. + * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should + * be sent to RO to be precise. + */ + EC_FEATURE_EFS2 = 38, /* The MCU is a System Companion Processor (SCP). */ EC_FEATURE_SCP = 39, /* The MCU is an Integrated Sensor Hub */ @@ -1808,6 +1837,68 @@ BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); +/** + * Get information about the key used to sign the RW firmware. + * For more details on the fields, see "struct vb21_packed_key". + */ +#define EC_CMD_RWSIG_INFO 0x001B +#define EC_VER_RWSIG_INFO 0 + +#define VBOOT2_KEY_ID_BYTES 20 + +#ifdef CHROMIUM_EC +/* Don't force external projects to depend on the vboot headers. */ +#include "vb21_struct.h" +BUILD_ASSERT(sizeof(struct vb2_id) == VBOOT2_KEY_ID_BYTES); +#endif + +struct ec_response_rwsig_info { + /** + * Signature algorithm used by the key + * (enum vb2_signature_algorithm). + */ + uint16_t sig_alg; + + /** + * Hash digest algorithm used with the key + * (enum vb2_hash_algorithm). + */ + uint16_t hash_alg; + + /** Key version. */ + uint32_t key_version; + + /** Key ID (struct vb2_id). */ + uint8_t key_id[VBOOT2_KEY_ID_BYTES]; + + uint8_t key_is_valid; + + /** Alignment padding. */ + uint8_t reserved[3]; +} __ec_align4; + +BUILD_ASSERT(sizeof(struct ec_response_rwsig_info) == 32); + +/** + * Get information about the system, such as reset flags, locked state, etc. + */ +#define EC_CMD_SYSINFO 0x001C +#define EC_VER_SYSINFO 0 + +enum sysinfo_flags { + SYSTEM_IS_LOCKED = BIT(0), + SYSTEM_IS_FORCE_LOCKED = BIT(1), + SYSTEM_JUMP_ENABLED = BIT(2), + SYSTEM_JUMPED_TO_CURRENT_IMAGE = BIT(3), + SYSTEM_REBOOT_AT_SHUTDOWN = BIT(4) +}; + +struct ec_response_sysinfo { + uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ + uint32_t current_image; /**< enum ec_current_image */ + uint32_t flags; /**< enum sysinfo_flags */ +} __ec_align4; + /*****************************************************************************/ /* PWM commands */ @@ -2412,7 +2503,7 @@ /* * Sensor Offset command is a setter/getter command for the offset - * used for calibration. + * used for factory calibration. * The offsets can be calculated by the host, or via * PERFORM_CALIB command. */ @@ -2457,6 +2548,11 @@ */ MOTIONSENSE_CMD_SENSOR_SCALE = 18, + /* + * Read the current online calibration values (if available). + */ + MOTIONSENSE_CMD_ONLINE_CALIB_READ = 19, + /* Number of motionsense sub-commands. */ MOTIONSENSE_NUM_CMDS }; @@ -2508,6 +2604,7 @@ MOTIONSENSE_CHIP_TCS3400 = 20, MOTIONSENSE_CHIP_LIS2DW12 = 21, MOTIONSENSE_CHIP_LIS2DWL = 22, + MOTIONSENSE_CHIP_LIS2DS = 23, MOTIONSENSE_CHIP_MAX, }; @@ -2540,6 +2637,12 @@ }; } __ec_todo_packed; +/* Response to AP reporting calibration data for a given sensor. */ +struct ec_response_online_calibration_data { + /** The calibration values. */ + int16_t data[3]; +}; + /* Note: used in ec_response_get_next_data */ struct ec_response_motion_sense_fifo_info { /* Size of the fifo */ @@ -2653,7 +2756,7 @@ */ struct __ec_todo_unpacked { uint8_t sensor_num; - } info, info_3, data, fifo_flush, list_activities; + } info, info_3, info_4, data, fifo_flush, list_activities; /* * Used for MOTIONSENSE_CMD_PERFORM_CALIB: @@ -2663,6 +2766,7 @@ uint8_t sensor_num; uint8_t enable; } perform_calib; + /* * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR * and MOTIONSENSE_CMD_SENSOR_RANGE. @@ -2795,6 +2899,15 @@ */ int16_t hys_degree; } tablet_mode_threshold; + + /* + * Used for MOTIONSENSE_CMD_ONLINE_CALIB_READ: + * Allow reading a single sensor's online calibration value. + */ + struct __ec_todo_unpacked { + uint8_t sensor_num; + } online_calib_read; + }; } __ec_todo_packed; @@ -2915,6 +3028,8 @@ struct ec_response_motion_sense_fifo_data fifo_read; + struct ec_response_online_calibration_data online_calib_read; + struct __ec_todo_packed { uint16_t reserved; uint32_t enabled; @@ -3572,6 +3687,9 @@ /* We have entered DisplayPort Alternate Mode on a Type-C port. */ EC_MKBP_EVENT_DP_ALT_MODE_ENTERED = 10, + /* New online calibration values are available. */ + EC_MKBP_EVENT_ONLINE_CALIBRATION = 11, + /* Number of MKBP events */ EC_MKBP_EVENT_COUNT, }; @@ -5220,27 +5338,24 @@ PD_CC_NONE = 0, /* No port partner attached */ /* From DFP perspective */ + PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ /* From UFP perspective */ - PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ + PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ }; -#define USBC_CABLE_TYPE_UNDEF 0 /* Undefined */ -#define USBC_CABLE_TYPE_PASSIVE 3 /* Passive cable attached */ -#define USBC_CABLE_TYPE_ACTIVE 4 /* Active cable attached */ - /* Active/Passive Cable */ -#define USB_PD_MUX_TBT_ACTIVE_CABLE BIT(0) +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) /* Optical/Non-optical cable */ -#define USB_PD_MUX_TBT_CABLE_TYPE BIT(1) +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) /* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ -#define USB_PD_MUX_TBT_ADAPTER BIT(2) -/* Active Link enabled/disabled */ -#define USB_PD_MUX_TBT_LINK BIT(3) +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) +/* Active Link Uni-Direction */ +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) /* * Underdevelopement : @@ -5253,10 +5368,10 @@ char state[32]; uint8_t cc_state; /* enum pd_cc_states representing cc state */ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ - uint8_t cable_type; /* USBC_CABLE_TYPE_*cable_type */ - uint8_t control_flags; /* USB_PD_MUX_*flags */ - uint8_t cable_speed; - uint8_t cable_gen; /* rounded_support */ + uint8_t reserved; /* Reserved for future use */ + uint8_t control_flags; /* USB_PD_CTRL_*flags */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; #define EC_CMD_USB_PD_PORTS 0x0102 @@ -5352,7 +5467,7 @@ * TODO(rspangler) but it's not aligned! * Should have been reserved[2]. */ - uint32_t current_image; /* One of ec_current_image */ + uint32_t current_image; /* One of ec_image */ } __ec_align1; /* Read USB-PD Accessory info */ @@ -5546,6 +5661,10 @@ #define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ #define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ + +/* USB-C Dock connected */ +#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ @@ -5633,6 +5752,7 @@ CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ + CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ CBI_TAG_COUNT, }; @@ -5694,6 +5814,9 @@ #define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ #define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ #define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */ +#define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This + * enables PD in RO for Chromebox. + */ struct ec_response_uptime_info { /* @@ -5921,6 +6044,43 @@ } __ec_align1; /*****************************************************************************/ +/* + * Button press simulation + * + * This command is used to simulate a button press. + * Supported commands are vup(volume up) vdown(volume down) & rec(recovery) + * Time duration for which button needs to be pressed is an optional parameter. + * + * NOTE: This is only available on unlocked devices for testing purposes only. + */ +#define EC_CMD_BUTTON 0x0129 + +struct ec_params_button { + /* Button mask aligned to enum keyboard_button_type */ + uint32_t btn_mask; + + /* Duration in milliseconds button needs to be pressed */ + uint32_t press_ms; +} __ec_align1; + +enum keyboard_button_type { + KEYBOARD_BUTTON_POWER = 0, + KEYBOARD_BUTTON_VOLUME_DOWN = 1, + KEYBOARD_BUTTON_VOLUME_UP = 2, + KEYBOARD_BUTTON_RECOVERY = 3, + KEYBOARD_BUTTON_CAPSENSE_1 = 4, + KEYBOARD_BUTTON_CAPSENSE_2 = 5, + KEYBOARD_BUTTON_CAPSENSE_3 = 6, + KEYBOARD_BUTTON_CAPSENSE_4 = 7, + KEYBOARD_BUTTON_CAPSENSE_5 = 8, + KEYBOARD_BUTTON_CAPSENSE_6 = 9, + KEYBOARD_BUTTON_CAPSENSE_7 = 10, + KEYBOARD_BUTTON_CAPSENSE_8 = 11, + + KEYBOARD_BUTTON_COUNT +}; + +/*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ /*****************************************************************************/ -- To view, visit https://review.coreboot.org/c/coreboot/+/40266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I940f5c7fe8ad4d989a1dfcd6da3ccf9fc151ec56 Gerrit-Change-Number: 40266 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Remove unneeded whitespaces
by HAOUAS Elyes (Code Review) 09 Apr '20

09 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39991 ) Change subject: soc/intel: Remove unneeded whitespaces ...................................................................... soc/intel: Remove unneeded whitespaces Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/acpi/lpit.asl M src/soc/intel/common/acpi/platform.asl M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/39991/1 diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 6ae4975..0d2d9c3 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -78,7 +78,7 @@ /* * Save the current PM bits then * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ + */ If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 8984f14..57f7505 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -43,7 +43,7 @@ /* * Save the current PM bits then * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ + */ If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index b3278f5..ede2208 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -19,7 +19,7 @@ * The mapping fields ae Address, Pin, Source, Source Index. */ -#define GEN_PCIE_LEGACY_IRQ() \ +#define GEN_PCIE_LEGACY_IRQ() \ Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/39991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d Gerrit-Change-Number: 39991 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma: Remove unneeded white space
by HAOUAS Elyes (Code Review) 09 Apr '20

09 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39990 ) Change subject: drivers/intel/gma: Remove unneeded white space ...................................................................... drivers/intel/gma: Remove unneeded white space Change-Id: I816cfe0e3114fe270c6c48014705dbee3b10fd50 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/i915_reg.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/39990/1 diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 38ea72a..4ebdc59 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -242,9 +242,9 @@ #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) #define MI_BATCH_NON_SECURE (1) /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ -#define MI_BATCH_NON_SECURE_I965 (1<<8) +#define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_PPGTT_HSW (1<<8) -#define MI_BATCH_NON_SECURE_HSW (1<<13) +#define MI_BATCH_NON_SECURE_HSW (1<<13) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816cfe0e3114fe270c6c48014705dbee3b10fd50 Gerrit-Change-Number: 39990 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically
by HAOUAS Elyes (Code Review) 09 Apr '20

09 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40226 ) Change subject: sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically ...................................................................... sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/early_smbus.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/40226/1 diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 9164c58..44a6846 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -8,7 +8,7 @@ static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 3a1369a..1c01301 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -14,7 +14,7 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + const pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ if (pci_read_config16(dev, 0x2) != 0x27da) -- To view, visit https://review.coreboot.org/c/coreboot/+/40226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8 Gerrit-Change-Number: 40226 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i945: Use 'const' to set pci_devfn_t statically
by HAOUAS Elyes (Code Review) 09 Apr '20

09 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40227 ) Change subject: nb/intel/i945: Use 'const' to set pci_devfn_t statically ...................................................................... nb/intel/i945: Use 'const' to set pci_devfn_t statically Change-Id: I879dd2fc61bc385486b506e2123f32629a67f518 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/40227/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 368ebd2..d7bc1c6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -498,10 +498,10 @@ u32 timeout; u32 reg32; u16 reg16; - pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); + const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); u8 tmp_secondary = 0x0a; - pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); + const pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); @@ -761,7 +761,7 @@ static void i945_setup_root_complex_topology(void) { u32 reg32; - pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); + const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); /* Egress Port Root Topology */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I879dd2fc61bc385486b506e2123f32629a67f518 Gerrit-Change-Number: 40227 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro
by HAOUAS Elyes (Code Review) 09 Apr '20

09 Apr '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40225 ) Change subject: sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro ...................................................................... sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/lynxpoint/early_smbus.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40225/1 diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index f3151af..0275078 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/smbus_host.h> @@ -17,7 +18,7 @@ pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 0c99a22..b87c872 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/smbus_host.h> @@ -17,7 +18,7 @@ pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index f3151af..0275078 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/smbus_host.h> @@ -17,7 +18,7 @@ pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1; /* Set SMBus I/O base. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf Gerrit-Change-Number: 40225 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Allow variants to not necessarily be laptops
by Edward O'Callaghan (Code Review) 09 Apr '20

09 Apr '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40252 ) Change subject: mb/google/hatch: Allow variants to not necessarily be laptops ...................................................................... mb/google/hatch: Allow variants to not necessarily be laptops In some cases Hatch variants are not laptop form-factors such as Puff. Ensure that the base configuration does not assume the form factor and allow variants to elect their intended use-case. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name 2 files changed, 23 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/40252/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 04790e0..9f09bfa 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -26,6 +26,9 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE +config BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + def_bool n + if BOARD_GOOGLE_BASEBOARD_HATCH config CHROMEOS @@ -134,8 +137,13 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN - # FIXME: allow kconfig to select on a subset of boards only - select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_PUFF select VBOOT_LID_SWITCH endif # BOARD_GOOGLE_BASEBOARD_HATCH + +if BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP + +config VBOOT + select VBOOT_EARLY_EC_SYNC + +endif # BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 454561b..ac64a9e 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -3,38 +3,45 @@ config BOARD_GOOGLE_AKEMI bool "-> Akemi" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_DRATINI bool "-> Dratini" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_JINLON bool "-> Jinlon" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select DRIVERS_GFX_GENERIC config BOARD_GOOGLE_KOHAKU bool "-> Kohaku" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_KINDRED bool "-> Kindred" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMMON_MMC_OVERRIDE config BOARD_GOOGLE_HELIOS bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 @@ -42,11 +49,13 @@ config BOARD_GOOGLE_MUSHU bool "-> Mushu" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PALKIA bool "-> Palkia" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 @@ -54,6 +63,7 @@ config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_PUFF @@ -67,6 +77,7 @@ config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011 @@ -74,9 +85,11 @@ config BOARD_GOOGLE_STRYKE bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 config BOARD_GOOGLE_SUSHI bool "-> Sushi" select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_GOOGLE_BASEBOARD_HATCH_LAPTOP select BOARD_ROMSIZE_KB_16384 -- To view, visit https://review.coreboot.org/c/coreboot/+/40252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33 Gerrit-Change-Number: 40252 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in gerrit-avatars[master]: Add my avatar
by Scott Chao (Code Review) 09 Apr '20

09 Apr '20

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/40289 ) Change subject: Add my avatar ...................................................................... Add my avatar Change-Id: Ia6743c1a60ddb530a6fe5e080e437e7ed1710ac3 Signed-off-by: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> --- A 1002883.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/89/40289/1 diff --git a/1002883.jpg b/1002883.jpg new file mode 100644 index 0000000..a05f7be --- /dev/null +++ b/1002883.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/40289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: Ia6743c1a60ddb530a6fe5e080e437e7ed1710ac3 Gerrit-Change-Number: 40289 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott.chao(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add ECC support
by Angel Pons (Code Review) 09 Apr '20

09 Apr '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22215 ) Change subject: nb/intel/sandybridge/raminit: Add ECC support ...................................................................... Patch Set 17: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/22215/16/src/northbridge/intel/san… File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/22215/16/src/northbridge/intel/san… PS16, Line 341: printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n", > Maybe don't add it here on the previous patchset? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/22215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1206746332c9939a78b67e7b48d3098bdef8a2ed Gerrit-Change-Number: 22215 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Apr 2020 12:59:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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