coreboot-gerrit March 2020

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Change in coreboot[master]: mainboard: drop 5 broken ROMCC_BOOTBLOCK boards
by Mike Banon (Code Review) 11 Mar '20

11 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38905 ) Change subject: mainboard: drop 5 broken ROMCC_BOOTBLOCK boards ...................................................................... mainboard: drop 5 broken ROMCC_BOOTBLOCK boards The source code of these 5 boards can't be successfully built after a simple switch away from ROMCC_BOOTBLOCK which we did for many other AMD boards. See my failed attempts at CB:37976, CB:37979, CB:37980, CB:37981 and CB:37982. Unless someone is really interested in fixing and if their code doesn't hold any other value, they could be dropped. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ia62c15a565f0284525b4e1856f7c430b733bf178 --- D src/mainboard/amd/bettong/BiosCallOuts.c D src/mainboard/amd/bettong/BiosCallOuts.h D src/mainboard/amd/bettong/Kconfig D src/mainboard/amd/bettong/Kconfig.name D src/mainboard/amd/bettong/Makefile.inc D src/mainboard/amd/bettong/OemCustomize.c D src/mainboard/amd/bettong/README D src/mainboard/amd/bettong/acpi/carrizo_fch.asl D src/mainboard/amd/bettong/acpi/gpe.asl D src/mainboard/amd/bettong/acpi/mainboard.asl D src/mainboard/amd/bettong/acpi/routing.asl D src/mainboard/amd/bettong/acpi/sleep.asl D src/mainboard/amd/bettong/acpi/usb_oc.asl D src/mainboard/amd/bettong/acpi_tables.c D src/mainboard/amd/bettong/board_info.txt D src/mainboard/amd/bettong/boardid.c D src/mainboard/amd/bettong/cmos.layout D src/mainboard/amd/bettong/devicetree.cb D src/mainboard/amd/bettong/dsdt.asl D src/mainboard/amd/bettong/fchec.c D src/mainboard/amd/bettong/irq_tables.c D src/mainboard/amd/bettong/mainboard.c D src/mainboard/amd/bettong/mptable.c D src/mainboard/amd/bettong/romstage.c D src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c D src/mainboard/amd/db-ft3b-lc/Kconfig D src/mainboard/amd/db-ft3b-lc/Kconfig.name D src/mainboard/amd/db-ft3b-lc/Makefile.inc D src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex D src/mainboard/amd/db-ft3b-lc/OemCustomize.c D src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl D src/mainboard/amd/db-ft3b-lc/acpi/ide.asl D src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl D src/mainboard/amd/db-ft3b-lc/acpi/routing.asl D src/mainboard/amd/db-ft3b-lc/acpi/si.asl D src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl D src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl D src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl D src/mainboard/amd/db-ft3b-lc/acpi_tables.c D src/mainboard/amd/db-ft3b-lc/board_info.txt D src/mainboard/amd/db-ft3b-lc/cmos.layout D src/mainboard/amd/db-ft3b-lc/devicetree.cb D src/mainboard/amd/db-ft3b-lc/dsdt.asl D src/mainboard/amd/db-ft3b-lc/irq_tables.c D src/mainboard/amd/db-ft3b-lc/mainboard.c D src/mainboard/amd/db-ft3b-lc/mptable.c D src/mainboard/amd/db-ft3b-lc/romstage.c D src/mainboard/amd/lamar/BiosCallOuts.c D src/mainboard/amd/lamar/Kconfig D src/mainboard/amd/lamar/Kconfig.name D src/mainboard/amd/lamar/Makefile.inc D src/mainboard/amd/lamar/OemCustomize.c D src/mainboard/amd/lamar/acpi/gpe.asl D src/mainboard/amd/lamar/acpi/mainboard.asl D src/mainboard/amd/lamar/acpi/routing.asl D src/mainboard/amd/lamar/acpi/si.asl D src/mainboard/amd/lamar/acpi/sleep.asl D src/mainboard/amd/lamar/acpi/thermal.asl D src/mainboard/amd/lamar/acpi/usb_oc.asl D src/mainboard/amd/lamar/acpi_tables.c D src/mainboard/amd/lamar/board_info.txt D src/mainboard/amd/lamar/cmos.layout D src/mainboard/amd/lamar/devicetree.cb D src/mainboard/amd/lamar/dsdt.asl D src/mainboard/amd/lamar/irq_tables.c D src/mainboard/amd/lamar/mainboard.c D src/mainboard/amd/lamar/mptable.c D src/mainboard/amd/lamar/romstage.c D src/mainboard/amd/olivehillplus/BiosCallOuts.c D src/mainboard/amd/olivehillplus/Kconfig D src/mainboard/amd/olivehillplus/Kconfig.name D src/mainboard/amd/olivehillplus/Makefile.inc D src/mainboard/amd/olivehillplus/OemCustomize.c D src/mainboard/amd/olivehillplus/acpi/gpe.asl D src/mainboard/amd/olivehillplus/acpi/ide.asl D src/mainboard/amd/olivehillplus/acpi/mainboard.asl D src/mainboard/amd/olivehillplus/acpi/routing.asl D src/mainboard/amd/olivehillplus/acpi/si.asl D src/mainboard/amd/olivehillplus/acpi/sleep.asl D src/mainboard/amd/olivehillplus/acpi/thermal.asl D src/mainboard/amd/olivehillplus/acpi/usb_oc.asl D src/mainboard/amd/olivehillplus/acpi_tables.c D src/mainboard/amd/olivehillplus/board_info.txt D src/mainboard/amd/olivehillplus/cmos.layout D src/mainboard/amd/olivehillplus/devicetree.cb D src/mainboard/amd/olivehillplus/dsdt.asl D src/mainboard/amd/olivehillplus/irq_tables.c D src/mainboard/amd/olivehillplus/mainboard.c D src/mainboard/amd/olivehillplus/mptable.c D src/mainboard/amd/olivehillplus/romstage.c D src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex D src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex D src/mainboard/bap/ode_e21XX/BiosCallOuts.c D src/mainboard/bap/ode_e21XX/Kconfig D src/mainboard/bap/ode_e21XX/Kconfig.name D src/mainboard/bap/ode_e21XX/Makefile.inc D src/mainboard/bap/ode_e21XX/OemCustomize.c D src/mainboard/bap/ode_e21XX/acpi/gpe.asl D src/mainboard/bap/ode_e21XX/acpi/ide.asl D src/mainboard/bap/ode_e21XX/acpi/mainboard.asl D src/mainboard/bap/ode_e21XX/acpi/routing.asl D src/mainboard/bap/ode_e21XX/acpi/si.asl D src/mainboard/bap/ode_e21XX/acpi/sleep.asl D src/mainboard/bap/ode_e21XX/acpi/superio.asl D src/mainboard/bap/ode_e21XX/acpi/thermal.asl D src/mainboard/bap/ode_e21XX/acpi/usb_oc.asl D src/mainboard/bap/ode_e21XX/acpi_tables.c D src/mainboard/bap/ode_e21XX/board_info.txt D src/mainboard/bap/ode_e21XX/cmos.layout D src/mainboard/bap/ode_e21XX/devicetree.cb D src/mainboard/bap/ode_e21XX/dsdt.asl D src/mainboard/bap/ode_e21XX/irq_tables.c D src/mainboard/bap/ode_e21XX/mainboard.c D src/mainboard/bap/ode_e21XX/mptable.c D src/mainboard/bap/ode_e21XX/romstage.c 116 files changed, 0 insertions(+), 9,893 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38905/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/38905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia62c15a565f0284525b4e1856f7c430b733bf178 Gerrit-Change-Number: 38905 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smm: add case intrusion to SMI handler
by Patrick Georgi (Code Review) 11 Mar '20

11 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39265 ) Change subject: soc/intel/common/block/smm: add case intrusion to SMI handler ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/39265/6/src/soc/intel/common/block… File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/39265/6/src/soc/intel/common/block… PS6, Line 434: if (!tco_sts) > I guess what Michael meant is that it's only ever called in a TCO SMI, and so it shouldn't be called […] Note: if we agree that this code should be eliminated by an #if in the southbridge_smi array, that probably should be a separate commit (and this one would apparently be ready to go in and therefore should this comment should be marked resolved.) -- To view, visit https://review.coreboot.org/c/coreboot/+/39265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Gerrit-Change-Number: 39265 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 11 Mar 2020 14:47:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Save DIMM info by available nodes
by Jes Klinke (Code Review) 11 Mar '20

11 Mar '20

Hello Jamie Ryu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39359 to review the following change. Change subject: soc/intel/tigerlake: Save DIMM info by available nodes ...................................................................... soc/intel/tigerlake: Save DIMM info by available nodes TEST= make build image returns correct dimm info by mosys and dmidecode with TGL-U and TGL-Y + MICA + LPDDR4 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596 --- M src/soc/intel/tigerlake/romstage/romstage.c 1 file changed, 40 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/39359/1 diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 17efc98..f592bb0 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -37,22 +37,23 @@ /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { - int channel, dimm, dimm_max, index; + int node, channel, dimm, dimm_max, index; size_t hob_size; const CONTROLLER_INFO *ctrlr_info; const CHANNEL_INFO *channel_info; const DIMM_INFO *src_dimm; struct dimm_info *dest_dimm; struct memory_info *mem_info; - const MEMORY_INFO_DATA_HOB *memory_info_hob; + const MEMORY_INFO_DATA_HOB *meminfo_hob; const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = fsp_find_extension_hob_by_guid( + meminfo_hob = fsp_find_extension_hob_by_guid( smbios_memory_info_guid, &hob_size); - if (memory_info_hob == NULL || hob_size == 0) { + if (meminfo_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } @@ -68,40 +69,46 @@ } memset(mem_info, 0, sizeof(*mem_info)); - /* Describe the first N DIMMs in the system */ + /* Save available DIMM information */ index = 0; dimm_max = ARRAY_SIZE(mem_info->dimm); - ctrlr_info = &memory_info_hob->Controller[0]; - for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { - channel_info = &ctrlr_info->ChannelInfo[channel]; - if (channel_info->Status != CHANNEL_PRESENT) - continue; - for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { - src_dimm = &channel_info->DimmInfo[dimm]; - dest_dimm = &mem_info->dimm[index]; - - if (src_dimm->Status != DIMM_PRESENT) + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; + channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) continue; - u8 memProfNum = memory_info_hob->MemoryProfile; + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; + dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; - /* Populate the DIMM information */ - dimm_info_fill(dest_dimm, - src_dimm->DimmCapacity, - memory_info_hob->MemoryType, - memory_info_hob->ConfiguredMemoryClockSpeed, - src_dimm->RankInDimm, - channel_info->ChannelId, - src_dimm->DimmId, - (const char *)src_dimm->ModulePartNum, - sizeof(src_dimm->ModulePartNum), - src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth, - memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport, - src_dimm->MfgId, - src_dimm->SpdModuleType); - index++; + u8 memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); + index++; + } } } mem_info->dimm_cnt = index; -- To view, visit https://review.coreboot.org/c/coreboot/+/39359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596 Gerrit-Change-Number: 39359 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 7...
by Sumeet R Pawnikar (Code Review) 11 Mar '20

11 Mar '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39395 ) Change subject: mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77 degree C ...................................................................... mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77 degree C PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Drallion. Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39395/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d0006d6..60be8c9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -175,6 +175,9 @@ register "tcc_offset" = "1" + # PCH Thermal Trip Temperature in deg C + register "common_soc_config.pch_thermal_trip" = "77" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/39395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a Gerrit-Change-Number: 39395 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: tco: enable intruder SMI if selected
by 9elements QA (Code Review) 11 Mar '20

11 Mar '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39264 ) Change subject: soc/intel/common/block: tco: enable intruder SMI if selected ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1250 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1249 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1248 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/39264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7 Gerrit-Change-Number: 39264 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Mar 2020 14:41:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: Add LP_4G_2133 SPD
by Raymond Chung (Code Review) 11 Mar '20

11 Mar '20

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39271 ) Change subject: mb/google/hatch: Add LP_4G_2133 SPD ...................................................................... mb/google/hatch: Add LP_4G_2133 SPD Add LPDDR3 4GB 2133MHz SPD file. BUG=b:149226871 TEST=Build and check cbfs has the spd.bin Change-Id: I1598774a87eecc76082286540beadaa3c26eda69 Signed-off-by: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> --- A src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/39271/1 diff --git a/src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex b/src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex new file mode 100644 index 0000000..fc7b9c8 --- /dev/null +++ b/src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex @@ -0,0 +1,32 @@ +24 20 0F 0E 15 19 01 08 00 00 00 0B 03 03 00 00 +00 00 08 FF D4 01 00 00 78 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 08 7F C2 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/39271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1598774a87eecc76082286540beadaa3c26eda69 Gerrit-Change-Number: 39271 Gerrit-PatchSet: 1 Gerrit-Owner: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Enable pcie rp11 for optane
by Wonkyu Kim (Code Review) 11 Mar '20

11 Mar '20

Hello Wonkyu Kim, Nick Vaccaro, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39420 to review the following change. Change subject: mb/google/volteer: Enable pcie rp11 for optane ...................................................................... mb/google/volteer: Enable pcie rp11 for optane Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk related pins. Configuring pciecontroller3 to be set from 2x2. This will by done by auto detecting optane memory: enabling HybridStorageMode. BUG=b:148604250 BRANCH=chromeos TEST='Build, boot and look for two NVMe devices with lspci on Volteer' Cq-Depend: chrome-internal:2501837 Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda(a)intel.com> Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/core… Tested-by: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39420/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 070e4f6..cb704c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -46,6 +46,10 @@ register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + # Enable Optane PCIE 11 using clk 0 + register "PcieRpEnable[10]" = "1" + register "HybridStorageMode" = "1" + # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" @@ -312,7 +316,7 @@ device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.4 off end # RP13 0xA0B4 device pci 1d.5 off end # RP14 0xA0B5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628 Gerrit-Change-Number: 39420 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/tigerlake: Correct FSP log interface for JSL
by Ronak Kanabar (Code Review) 11 Mar '20

11 Mar '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39280 ) Change subject: soc/tigerlake: Correct FSP log interface for JSL ...................................................................... soc/tigerlake: Correct FSP log interface for JSL Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/1 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 56124f4..3dc87ee 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -70,7 +70,7 @@ /* Set CPU Ratio */ m_cfg->CpuRatio = 0; m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); -- To view, visit https://review.coreboot.org/c/coreboot/+/39280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Gerrit-Change-Number: 39280 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Fix stale device pointer usage
by Karthik Ramasubramanian (Code Review) 11 Mar '20

11 Mar '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39405 ) Change subject: soc/intel/tigerlake: Fix stale device pointer usage ...................................................................... soc/intel/tigerlake: Fix stale device pointer usage TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7 --- M src/soc/intel/tigerlake/fsp_params_jsl.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39405/1 diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 6cb3b67..fa36e81 100644 --- a/src/soc/intel/tigerlake/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c @@ -143,7 +143,8 @@ } /* SDCard related configuration */ - params->ScsSdCardEnabled = pcidev_path_on_root(PCH_DEVFN_SDCARD) ? dev->enabled : 0; + params->ScsSdCardEnabled = (dev = pcidev_path_on_root(PCH_DEVFN_SDCARD)) ? + dev->enabled : 0; params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/39405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7 Gerrit-Change-Number: 39405 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/cbfs.c: Remove unused macro
by HAOUAS Elyes (Code Review) 11 Mar '20

11 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39410 ) Change subject: commonlib/cbfs.c: Remove unused macro ...................................................................... commonlib/cbfs.c: Remove unused macro Change-Id: I330de4357fa48ee3d76a97a682b389ef42e7a135 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/cbfs.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39410/1 diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index be0de9f..b03a3dc 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -18,9 +18,6 @@ #include <string.h> #include <vb2_sha.h> -#if !defined(ERROR) -#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -#endif #if !defined(LOG) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/39410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I330de4357fa48ee3d76a97a682b389ef42e7a135 Gerrit-Change-Number: 39410 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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