coreboot-gerrit March 2020

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Change in coreboot[master]: util/inteltool: Makefile: add src/arch to includes
by Patrick Georgi (Code Review) 15 Mar '20

15 Mar '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39525 ) Change subject: util/inteltool: Makefile: add src/arch to includes ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/39525/5/util/inteltool/Makefile File util/inteltool/Makefile: https://review.coreboot.org/c/coreboot/+/39525/5/util/inteltool/Makefile@48 PS5, Line 48: ARCH = $(subst _64,,$(shell uname -m)) That looks both superfluous (do we ever expect _intel_tool to be usable on a non-intel architecture?) and Linux specific (while inteltool comes with a bunch of accomodations for other operating systems). -- To view, visit https://review.coreboot.org/c/coreboot/+/39525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157178a055a259e40c57f3915671d3b8966fbb96 Gerrit-Change-Number: 39525 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 15 Mar 2020 13:08:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: powermgt: rename variable for consistency
by Patrick Georgi (Code Review) 15 Mar '20

15 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39507 ) Change subject: util/inteltool: powermgt: rename variable for consistency ...................................................................... util/inteltool: powermgt: rename variable for consistency Rename size variable for consistency with the other subsystems. Change-Id: I9407193ac9e34685362619cfd45384156e2385c3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39507 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/powermgt.c 1 file changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 2dfc05d..54a3045 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -669,7 +669,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { - size_t i, size = 0; + size_t i, pm_registers_size = 0; uint16_t pmbase; const io_register_t *pm_registers; uint64_t pwrmbase_phys = 0; @@ -757,13 +757,13 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; - size = ARRAY_SIZE(pch_pm_registers); + pm_registers_size = ARRAY_SIZE(pch_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH10: case PCI_DEVICE_ID_INTEL_ICH10R: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = ich10_pm_registers; - size = ARRAY_SIZE(ich10_pm_registers); + pm_registers_size = ARRAY_SIZE(ich10_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: @@ -772,7 +772,7 @@ case PCI_DEVICE_ID_INTEL_NM10: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich7_pm_registers; - size = ARRAY_SIZE(ich7_pm_registers); + pm_registers_size = ARRAY_SIZE(ich7_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH9DH: case PCI_DEVICE_ID_INTEL_ICH9DO: @@ -782,39 +782,39 @@ case PCI_DEVICE_ID_INTEL_ICH9ME: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich9_pm_registers; - size = ARRAY_SIZE(ich9_pm_registers); + pm_registers_size = ARRAY_SIZE(ich9_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: case PCI_DEVICE_ID_INTEL_ICH8ME: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers; - size = ARRAY_SIZE(ich8_pm_registers); + pm_registers_size = ARRAY_SIZE(ich8_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH6: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich6_pm_registers; - size = ARRAY_SIZE(ich6_pm_registers); + pm_registers_size = ARRAY_SIZE(ich6_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH5: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich5_pm_registers; - size = ARRAY_SIZE(ich5_pm_registers); + pm_registers_size = ARRAY_SIZE(ich5_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH4: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich4_pm_registers; - size = ARRAY_SIZE(ich4_pm_registers); + pm_registers_size = ARRAY_SIZE(ich4_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH2: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich2_pm_registers; - size = ARRAY_SIZE(ich2_pm_registers); + pm_registers_size = ARRAY_SIZE(ich2_pm_registers); break; case PCI_DEVICE_ID_INTEL_ICH0: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich0_pm_registers; - size = ARRAY_SIZE(ich0_pm_registers); + pm_registers_size = ARRAY_SIZE(ich0_pm_registers); break; case PCI_DEVICE_ID_INTEL_82371XX: acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 3); @@ -826,13 +826,13 @@ pci_free_dev(acpi); pm_registers = i82371xx_pm_registers; - size = ARRAY_SIZE(i82371xx_pm_registers); + pm_registers_size = ARRAY_SIZE(i82371xx_pm_registers); break; case PCI_DEVICE_ID_INTEL_I63XX: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = i63xx_pm_registers; - size = ARRAY_SIZE(i63xx_pm_registers); + pm_registers_size = ARRAY_SIZE(i63xx_pm_registers); break; case PCI_DEVICE_ID_INTEL_CM236: @@ -847,7 +847,7 @@ pci_free_dev(acpi); pm_registers = sunrise_pm_registers; - size = ARRAY_SIZE(sunrise_pm_registers); + pm_registers_size = ARRAY_SIZE(sunrise_pm_registers); break; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); @@ -856,7 +856,7 @@ printf("PMBASE = 0x%04x (IO)\n\n", pmbase); - for (i = 0; i < size; i++) { + for (i = 0; i < pm_registers_size; i++) { switch (pm_registers[i].size) { case 8: printf("pmbase+0x%04x: 0x%08x (%s)\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/39507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9407193ac9e34685362619cfd45384156e2385c3 Gerrit-Change-Number: 39507 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: powermgt: initialize register size variables
by Patrick Georgi (Code Review) 15 Mar '20

15 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39513 ) Change subject: util/inteltool: powermgt: initialize register size variables ...................................................................... util/inteltool: powermgt: initialize register size variables Initialize register size variables to prevent segfaults. Change-Id: Ib89bf6f7c7582efdea1c54d1316ed8f33a87cfcc Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39513 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/powermgt.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 9933b04..2dfc05d 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -669,7 +669,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { - size_t i, size; + size_t i, size = 0; uint16_t pmbase; const io_register_t *pm_registers; uint64_t pwrmbase_phys = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib89bf6f7c7582efdea1c54d1316ed8f33a87cfcc Gerrit-Change-Number: 39513 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/model_2065x: Add missing CPU IDs
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38943 ) Change subject: cpu/intel/model_2065x: Add missing CPU IDs ...................................................................... cpu/intel/model_2065x: Add missing CPU IDs The missing CPU IDs were found on CPU-World's database: - 0x20650: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132688 - 0x20651: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132689 - 0x20652: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132690 - 0x20654: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132692 - 0x20655: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132693 Note that these CPUs are not Nehalem, but rather Arrandale on laptops and Clarksdale on desktops, so also update the comments accordingly. Change-Id: I285961b62b9a8ada5a1659cd9ad75f7075259664 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/model_2065x_init.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38943/1 diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index b736943..93fcc46 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -342,9 +342,13 @@ .init = model_2065x_init, }; +/* Arrandale / Clarksdale CPU IDs */ static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x20652 }, /* Intel Nehalem */ - { X86_VENDOR_INTEL, 0x20655 }, /* Intel Nehalem */ + { X86_VENDOR_INTEL, 0x20650 }, + { X86_VENDOR_INTEL, 0x20651 }, + { X86_VENDOR_INTEL, 0x20652 }, + { X86_VENDOR_INTEL, 0x20654 }, + { X86_VENDOR_INTEL, 0x20655 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I285961b62b9a8ada5a1659cd9ad75f7075259664 Gerrit-Change-Number: 38943 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: treewide: Replace uses of "Nehalem"
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38942 ) Change subject: treewide: Replace uses of "Nehalem" ...................................................................... treewide: Replace uses of "Nehalem" The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/common/fsb.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/model_2065x.h M src/drivers/intel/gma/Kconfig M src/include/cpu/intel/em64t101_save_state.h M src/northbridge/intel/ironlake/northbridge.c M src/security/tpm/Kconfig 7 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38942/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 726ab1c..3dfcd0b 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -48,7 +48,7 @@ *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; - case 0x25: /* Nehalem BCLK fixed at 133MHz */ + case 0x25: /* Arrandale BCLK fixed at 133MHz */ *fsb = 133; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1868876..af2606c 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -338,5 +338,5 @@ } struct chip_operations cpu_intel_model_2065x_ops = { - CHIP_NAME("Intel Nehalem CPU") + CHIP_NAME("Intel Arrandale CPU") }; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 730ab35..0a07f3c 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -15,7 +15,7 @@ #ifndef _CPU_INTEL_MODEL_2065X_H #define _CPU_INTEL_MODEL_2065X_H -/* Nehalem bus clock is fixed at 133MHz */ +/* Arrandale bus clock is fixed at 133MHz */ #define IRONLAKE_BCLK 133 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 87889d3..c35e44e 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -39,7 +39,7 @@ To be set by northbridge or mainboard Kconfig. For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz - DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's + DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz. diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 7493c85..5d3f9ed 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -20,7 +20,7 @@ /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: - * - Nehalem + * - Westmere * - SandyBridge * - IvyBridge * - Haswell diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index fe8eed3..91bcc11 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -263,10 +263,10 @@ .ops_pci = &intel_pci_ops, }; -static const struct pci_driver mc_driver_44 __pci_driver = { +static const struct pci_driver mc_driver_ard __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Nehalem */ + .device = 0x0044, /* Arrandale DRAM controller */ }; static struct device_operations cpu_bus_ops = { @@ -288,7 +288,7 @@ } struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") + CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") .enable_dev = enable_dev, .init = ironlake_init, }; diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 95c0bb9..fbe1735 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -99,7 +99,7 @@ Select this to ignore POSTINIT INVALID return codes on TPM startup. This is useful on platforms where a previous stage issued a TPM startup. Examples of use cases are Intel TXT - or VBOOT on the Intel Nehalem northbridge which issues a + or VBOOT on the Intel Arrandale processor, which issues a CPU-only reset during the romstage. endmenu # Trusted Platform Module (tpm) -- To view, visit https://review.coreboot.org/c/coreboot/+/38942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Gerrit-Change-Number: 38942 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Rename to ironlake
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38941 ) Change subject: nb/intel/nehalem: Rename to ironlake ...................................................................... nb/intel/nehalem: Rename to ironlake The code is for Arrandale CPUs, whose System Agent is Ironlake. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Makefile.inc M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/x86/Kconfig M src/drivers/intel/gma/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t410/romstage.c M src/mainboard/lenovo/t410/smihandler.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/packardbell/ms2290/Kconfig M src/mainboard/packardbell/ms2290/devicetree.cb M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c R src/northbridge/intel/ironlake/Kconfig R src/northbridge/intel/ironlake/Makefile.inc R src/northbridge/intel/ironlake/acpi.c R src/northbridge/intel/ironlake/acpi/hostbridge.asl R src/northbridge/intel/ironlake/acpi/ironlake.asl R src/northbridge/intel/ironlake/bootblock.c R src/northbridge/intel/ironlake/chip.h R src/northbridge/intel/ironlake/early_init.c R src/northbridge/intel/ironlake/finalize.c R src/northbridge/intel/ironlake/gma.c R src/northbridge/intel/ironlake/ironlake.h R src/northbridge/intel/ironlake/memmap.c R src/northbridge/intel/ironlake/northbridge.c R src/northbridge/intel/ironlake/raminit.c R src/northbridge/intel/ironlake/raminit.h R src/northbridge/intel/ironlake/raminit_tables.c R src/northbridge/intel/ironlake/raminit_tables.h R src/northbridge/intel/ironlake/romstage.c R src/northbridge/intel/ironlake/smi.c M src/southbridge/intel/common/firmware/Kconfig M src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/smihandler.c 46 files changed, 76 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38941/1 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 904b61bb..1849f19 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,7 +10,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 51acc278..1868876 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -216,7 +216,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3; + clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3; /* Calculate CPU TDP in mW */ power_max = 25000; @@ -277,7 +277,7 @@ /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * NEHALEM_BCLK + ratio / 3; + clock = ratio * IRONLAKE_BCLK + ratio / 3; acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f6982d9..730ab35 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -16,7 +16,7 @@ #define _CPU_INTEL_MODEL_2065X_H /* Nehalem bus clock is fixed at 133MHz */ -#define NEHALEM_BCLK 133 +#define IRONLAKE_BCLK 133 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index a9c28f6..b736943 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -197,7 +197,7 @@ wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); } static void set_energy_perf_bias(u8 policy) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 76446a0..f6dfca3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -140,7 +140,7 @@ bool default y if NORTHBRIDGE_INTEL_I945 default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_IRONLAKE default n config SERIALIZED_SMM_INITIALIZATION diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2071351..87889d3 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -66,7 +66,7 @@ config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ - || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ + || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ @@ -83,7 +83,7 @@ config GFX_GMA_INTERNAL_IS_LVDS bool depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT - default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE default n if GFX_GMA @@ -99,7 +99,7 @@ default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL - default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE + default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X config GFX_GMA_INTERNAL_PORT diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 5d60565..86cfce8 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 808e057..e18ec38 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index 4f67bd8..f8e989a 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -45,7 +45,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <northbridge/intel/ironlake/acpi/ironlake.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 4908ec5..f15a919 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -20,7 +20,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 91cb0ce..70a9e5d 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -19,7 +19,7 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a94d24e..42cf8f9 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 3ababc9..ba4434c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 4f67bd8..f8e989a 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -45,7 +45,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <northbridge/intel/ironlake/acpi/ironlake.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 4cd3bde..ebfe7a8 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <ec/acpi/ec.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/bd82x6x/pch.h> #include "dock.h" #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index aec63db..8bf6f90 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -21,7 +21,7 @@ #include <ec/acpi/ec.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 91cb0ce..70a9e5d 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -19,7 +19,7 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 8194002..4fc971f 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bf1c171..21b6a6d 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index bbd2b29..e53d728 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -39,7 +39,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <northbridge/intel/ironlake/acpi/ironlake.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 169b0ac..805eecb 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <arch/io.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 1f9d229..03ea86d 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> /* Seems copied from Lenovo Thinkpad x201, might be wrong */ const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index bc5067b..2d77564 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/ironlake/Kconfig similarity index 95% rename from src/northbridge/intel/nehalem/Kconfig rename to src/northbridge/intel/ironlake/Kconfig index a119b81..4f76dab 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -config NORTHBRIDGE_INTEL_NEHALEM +config NORTHBRIDGE_INTEL_IRONLAKE bool select CPU_INTEL_MODEL_2065X select VGA @@ -22,7 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP -if NORTHBRIDGE_INTEL_NEHALEM +if NORTHBRIDGE_INTEL_IRONLAKE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc similarity index 94% rename from src/northbridge/intel/nehalem/Makefile.inc rename to src/northbridge/intel/ironlake/Makefile.inc index 225f0ce..1fde37d 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE),y) bootblock-y += bootblock.c diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/ironlake/acpi.c similarity index 98% rename from src/northbridge/intel/nehalem/acpi.c rename to src/northbridge/intel/ironlake/acpi.c index 462cdc0..aa83369 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -22,7 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include "nehalem.h" +#include "ironlake.h" unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl similarity index 100% rename from src/northbridge/intel/nehalem/acpi/hostbridge.asl rename to src/northbridge/intel/ironlake/acpi/hostbridge.asl diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl similarity index 97% rename from src/northbridge/intel/nehalem/acpi/nehalem.asl rename to src/northbridge/intel/ironlake/acpi/ironlake.asl index 404801e..659234b4 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "../nehalem.h" +#include "../ironlake.h" #include "hostbridge.asl" #include <southbridge/intel/common/rcba.h> diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c similarity index 100% rename from src/northbridge/intel/nehalem/bootblock.c rename to src/northbridge/intel/ironlake/bootblock.c diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/ironlake/chip.h similarity index 89% rename from src/northbridge/intel/nehalem/chip.h rename to src/northbridge/intel/ironlake/chip.h index a9d136b..dad03da 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H -#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H +#ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H +#define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H #include <drivers/intel/gma/i915.h> @@ -25,7 +25,7 @@ * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ -struct northbridge_intel_nehalem_config { +struct northbridge_intel_ironlake_config { u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ @@ -48,4 +48,4 @@ u16 pci_mmio_size; }; -#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ +#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/ironlake/early_init.c similarity index 96% rename from src/northbridge/intel/nehalem/early_init.c rename to src/northbridge/intel/ironlake/early_init.c index a809121..fe4ad7f 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -26,9 +26,9 @@ #include <cpu/intel/turbo.h> #include <arch/cpu.h> -#include "nehalem.h" +#include "ironlake.h" -static void nehalem_setup_bars(void) +static void ironlake_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); @@ -114,7 +114,7 @@ wrmsr(IA32_MISC_ENABLE, m); } -void nehalem_early_initialization(int chipset_type) +void ironlake_early_initialization(int chipset_type) { u32 capid0_a; u8 reg8; @@ -126,14 +126,14 @@ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); reg8 &= ~7; /* Clear 2:0 */ - if (chipset_type == NEHALEM_MOBILE) + if (chipset_type == IRONLAKE_MOBILE) reg8 |= 1; /* Set bit 0 */ pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); } /* Setup all BARs required for early PCIe and raminit */ - nehalem_setup_bars(); + ironlake_setup_bars(); s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/ironlake/finalize.c similarity index 94% rename from src/northbridge/intel/nehalem/finalize.c rename to src/northbridge/intel/ironlake/finalize.c index c03b067..f76124b 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ -#include "nehalem.h" +#include "ironlake.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) -void intel_nehalem_finalize_smm(void) +void intel_ironlake_finalize_smm(void) { MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/ironlake/gma.c similarity index 96% rename from src/northbridge/intel/nehalem/gma.c rename to src/northbridge/intel/ironlake/gma.c index d717e48..27c0827 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -33,7 +33,7 @@ #include <types.h> #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do @@ -93,7 +93,7 @@ static void gma_pm_init_post_vbios(struct device *dev) { - struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct northbridge_intel_ironlake_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); @@ -177,7 +177,7 @@ if (!acpi_is_wakeup_s3() && CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct northbridge_intel_ironlake_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); @@ -223,7 +223,7 @@ if (!dev) { return NULL; } - struct northbridge_intel_nehalem_config *chip = dev->chip_info; + struct northbridge_intel_ironlake_config *chip = dev->chip_info; return &chip->gfx; } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/ironlake/ironlake.h similarity index 94% rename from src/northbridge/intel/nehalem/nehalem.h rename to src/northbridge/intel/ironlake/ironlake.h index 493c5b1..aa8cb7f 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ +#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ +#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #ifndef __ASSEMBLER__ @@ -99,9 +99,9 @@ #define D1F0_VC0RCTL 0x114 /* Chipset types */ -#define NEHALEM_MOBILE 0 -#define NEHALEM_DESKTOP 1 -#define NEHALEM_SERVER 2 +#define IRONLAKE_MOBILE 0 +#define IRONLAKE_DESKTOP 1 +#define IRONLAKE_SERVER 2 /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 @@ -249,14 +249,14 @@ #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 -void intel_nehalem_finalize_smm(void); +void intel_ironlake_finalize_smm(void); int bridge_silicon_revision(void); -void nehalem_early_initialization(int chipset_type); -void nehalem_late_initialization(void); +void ironlake_early_initialization(int chipset_type); +void ironlake_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap); #endif #endif -#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ +#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/ironlake/memmap.c similarity index 98% rename from src/northbridge/intel/nehalem/memmap.c rename to src/northbridge/intel/ironlake/memmap.c index 5de4b80..b2d61fe 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -23,7 +23,7 @@ #include <cpu/x86/smm.h> #include <program_loading.h> #include <cpu/intel/smm_reloc.h> -#include "nehalem.h" +#include "ironlake.h" static uintptr_t smm_region_start(void) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c similarity index 97% rename from src/northbridge/intel/nehalem/northbridge.c rename to src/northbridge/intel/ironlake/northbridge.c index 1718307..fe8eed3 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" #include <cpu/intel/smm_reloc.h> static int bridge_revision_id = -1; @@ -228,7 +228,7 @@ } /* Disable unused PEG devices based on devicetree before PCI enumeration */ -static void nehalem_init(void *const chip_info) +static void ironlake_init(void *const chip_info) { u32 deven_mask = UINT32_MAX; const struct device *dev; @@ -287,8 +287,8 @@ } } -struct chip_operations northbridge_intel_nehalem_ops = { +struct chip_operations northbridge_intel_ironlake_ops = { CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") .enable_dev = enable_dev, - .init = nehalem_init, + .init = ironlake_init, }; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/ironlake/raminit.c similarity index 99% rename from src/northbridge/intel/nehalem/raminit.c rename to src/northbridge/intel/ironlake/raminit.c index 7735522..1bd7941 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -40,7 +40,7 @@ #include <types.h> #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" #include "raminit.h" #include "raminit_tables.h" @@ -1367,7 +1367,7 @@ static unsigned int get_mmio_size(void) { const struct device *dev; - const struct northbridge_intel_nehalem_config *cfg = NULL; + const struct northbridge_intel_ironlake_config *cfg = NULL; dev = pcidev_path_on_root(HOST_BRIDGE); if (dev) diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/ironlake/raminit.h similarity index 97% rename from src/northbridge/intel/nehalem/raminit.h rename to src/northbridge/intel/ironlake/raminit.h index 9a200d4..1a55407 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -16,7 +16,7 @@ #ifndef RAMINIT_H #define RAMINIT_H -#include "nehalem.h" +#include "ironlake.h" void chipset_init(const int s3resume); /* spd_addrmap is array of 4 elements: diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c similarity index 100% rename from src/northbridge/intel/nehalem/raminit_tables.c rename to src/northbridge/intel/ironlake/raminit_tables.c diff --git a/src/northbridge/intel/nehalem/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h similarity index 100% rename from src/northbridge/intel/nehalem/raminit_tables.h rename to src/northbridge/intel/ironlake/raminit_tables.h diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/ironlake/romstage.c similarity index 92% rename from src/northbridge/intel/nehalem/romstage.c rename to src/northbridge/intel/ironlake/romstage.c index eceb8c2..fdd71b4 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -22,12 +22,12 @@ #include <cpu/x86/lapic.h> #include <timestamp.h> #include <romstage_handoff.h> -#include "nehalem.h" +#include "ironlake.h" #include <arch/romstage.h> #include <device/pci_def.h> #include <device/device.h> -#include <northbridge/intel/nehalem/chip.h> -#include <northbridge/intel/nehalem/raminit.h> +#include <northbridge/intel/ironlake/chip.h> +#include <northbridge/intel/ironlake/raminit.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> @@ -44,7 +44,7 @@ enable_lapic(); /* TODO, make this configurable */ - nehalem_early_initialization(NEHALEM_MOBILE); + ironlake_early_initialization(IRONLAKE_MOBILE); early_pch_init(); diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/ironlake/smi.c similarity index 96% rename from src/northbridge/intel/nehalem/smi.c rename to src/northbridge/intel/ironlake/smi.c index 8c19852..64c1fa5 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include "nehalem.h" +#include "ironlake.h" #include <cpu/intel/smm_reloc.h> diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index eb63d34..134f780 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -59,7 +59,7 @@ config CHECK_ME bool "Verify the integrity of the supplied ME/TXE firmware" default n - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ @@ -71,7 +71,7 @@ config USE_ME_CLEANER bool "Strip down the Intel ME/TXE firmware" - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c index 8d7a918..9aac07b 100644 --- a/src/southbridge/intel/ibexpeak/early_cir.c +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -14,7 +14,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include "pch.h" /* This sets up magic Chipset Initialization Registers */ @@ -53,7 +53,7 @@ /* Intel 5 Series Chipset and Intel 3400 Series Chipset External Design Specification (EDS) 13.8.1.1 */ - if (chipset_type == NEHALEM_DESKTOP) + if (chipset_type == IRONLAKE_DESKTOP) pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 56331cc..b455cef 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> @@ -47,7 +47,7 @@ early_gpio_init(); enable_smbus(); /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); + pch_setup_cir(IRONLAKE_MOBILE); southbridge_configure_default_intmap(); pch_default_disable(); early_usb_init(mainboard_usb_ports); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3988188..e670c9a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -34,7 +34,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmutil.h> @@ -185,6 +185,6 @@ { intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); + intel_ironlake_finalize_smm(); intel_model_2065x_finalize_smm(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Gerrit-Change-Number: 38941 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

8 20

Change in coreboot[master]: util/inteltool: powermgt: drop dead code
by Patrick Georgi (Code Review) 15 Mar '20

15 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39559 ) Change subject: util/inteltool: powermgt: drop dead code ...................................................................... util/inteltool: powermgt: drop dead code Drop dummy entry. Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39559 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/powermgt.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 8da12d2..9933b04 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -849,10 +849,6 @@ pm_registers = sunrise_pm_registers; size = ARRAY_SIZE(sunrise_pm_registers); break; - - case 0x1234: // Dummy for non-existent functionality - printf("This southbridge does not have PMBASE.\n"); - return 1; default: printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n"); return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/39559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1 Gerrit-Change-Number: 39559 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/inteltool: gpio: drop dead code
by Patrick Georgi (Code Review) 15 Mar '20

15 Mar '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39558 ) Change subject: util/inteltool: gpio: drop dead code ...................................................................... util/inteltool: gpio: drop dead code Drop dummy entry. Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39558 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/inteltool/gpio.c 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 9610fd6..55c32ba 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1076,9 +1076,6 @@ case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; - case 0x1234: // Dummy for non-existent functionality - printf("This southbridge does not have GPIOBASE.\n"); - return 1; default: printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n"); return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/39558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934 Gerrit-Change-Number: 39558 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: ec/google/wilco: Store LID status into LIDS
by EricR Lai (Code Review) 15 Mar '20

15 Mar '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39497 ) Change subject: ec/google/wilco: Store LID status into LIDS ...................................................................... ec/google/wilco: Store LID status into LIDS Store LID status into LIDS. Then Intel driver can reference it. TEST=check LID status by evtest Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba --- M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/lid.asl 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/39497/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 8fcd0dd..fddd730 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -60,6 +60,9 @@ /* Initialize UCSI */ ^UCSI.INIT () + + // Initialize LID switch state + Store (R (P1LC), \LIDS) } /* diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl index 818e135..b85b7aa 100644 --- a/src/ec/google/wilco/acpi/lid.asl +++ b/src/ec/google/wilco/acpi/lid.asl @@ -22,6 +22,7 @@ Method (_LID, 0, NotSerialized) { - Return (R (P1LC)) + Store (R (P1LC), \LIDS) + Return (\LIDS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba Gerrit-Change-Number: 39497 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: nb/intel/i945/raminit: Use boolean type for helper variables
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39536 ) Change subject: nb/intel/i945/raminit: Use boolean type for helper variables ...................................................................... nb/intel/i945/raminit: Use boolean type for helper variables Change-Id: I465a68f281534cd9fc5a7bde02c32d1353cfdaed Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/39536/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index fe68909..a92118c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2027,7 +2027,7 @@ static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) { u32 chan0 = 0, chan1 = 0; - int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; + bool chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); -- To view, visit https://review.coreboot.org/c/coreboot/+/39536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I465a68f281534cd9fc5a7bde02c32d1353cfdaed Gerrit-Change-Number: 39536 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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