coreboot-gerrit March 2020

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Change in coreboot[master]: nb/intel/i945/raminit: Remove space for correct alignment
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39535 ) Change subject: nb/intel/i945/raminit: Remove space for correct alignment ...................................................................... nb/intel/i945/raminit: Remove space for correct alignment Change-Id: I35d14541e0eab4474b03a9d2f114c7aa3e92918c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/39535/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 6321753..fe68909 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2029,7 +2029,7 @@ u32 chan0 = 0, chan1 = 0; int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; - chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); -- To view, visit https://review.coreboot.org/c/coreboot/+/39535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d14541e0eab4474b03a9d2f114c7aa3e92918c Gerrit-Change-Number: 39535 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p8z77-m_pro: Conistently spell *PRO* in board name uppercase
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39350 ) Change subject: mb/asus/p8z77-m_pro: Conistently spell *PRO* in board name uppercase ...................................................................... mb/asus/p8z77-m_pro: Conistently spell *PRO* in board name uppercase Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/mainboard/asus/p8z77-m_pro.md M src/mainboard/asus/p8z77-m_pro/early_init.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/39350/1 diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md index 2d9f612..1101089 100644 --- a/Documentation/mainboard/asus/p8z77-m_pro.md +++ b/Documentation/mainboard/asus/p8z77-m_pro.md @@ -1,6 +1,6 @@ -# ASUS P8Z77-M Pro +# ASUS P8Z77-M PRO -This page describes how to run coreboot on the [ASUS P8Z77-M Pro] +This page describes how to run coreboot on the [ASUS P8Z77-M PRO] ## Flashing coreboot @@ -163,6 +163,6 @@ - [Flash chip datasheet][W25Q64FVA1Q] -[ASUS P8Z77-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ +[ASUS P8Z77-M PRO]: https://www.asus.com/Motherboards/P8Z77M_PRO/ [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf [flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 6c76a7a..d2c2355 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -154,7 +154,7 @@ */ usb3_streams }, - /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */ + /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ .ddr3lv_support = 1, /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, * but might cause some system instability ! -- To view, visit https://review.coreboot.org/c/coreboot/+/39350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14 Gerrit-Change-Number: 39350 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: Docs: Fix link for ASUS P8Z77-M Pro
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39349 ) Change subject: Docs: Fix link for ASUS P8Z77-M Pro ...................................................................... Docs: Fix link for ASUS P8Z77-M Pro Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/mainboard/asus/p8z77-m_pro.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/39349/1 diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md index 7c84149..2d9f612 100644 --- a/Documentation/mainboard/asus/p8z77-m_pro.md +++ b/Documentation/mainboard/asus/p8z77-m_pro.md @@ -163,6 +163,6 @@ - [Flash chip datasheet][W25Q64FVA1Q] -[ASUS P8Z88-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ +[ASUS P8Z77-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf [flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/c/coreboot/+/39349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0 Gerrit-Change-Number: 39349 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd_bin: Add spaces around operator
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39528 ) Change subject: lib/spd_bin: Add spaces around operator ...................................................................... lib/spd_bin: Add spaces around operator Change-Id: Ic0571d06e94708dd5e151621ab7790f3c9f775c2 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/lib/spd_bin.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39528/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 35bcb4c..8477659 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -175,7 +175,7 @@ void print_spd_info(uint8_t spd[]) { - char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + char spd_name[DDR4_SPD_PART_LEN + 1] = { 0 }; int type = spd[SPD_DRAM_TYPE]; int banks = spd_get_banks(spd, type); int capmb = spd_get_capmb(spd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0571d06e94708dd5e151621ab7790f3c9f775c2 Gerrit-Change-Number: 39528 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Re-flow comment for 96 characters
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39457 ) Change subject: soc/intel/icelake: Re-flow comment for 96 characters ...................................................................... soc/intel/icelake: Re-flow comment for 96 characters Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/icelake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/39457/1 diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 99f606b..5aea2ee 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -30,10 +30,7 @@ uint32_t mask = 0; if (!dev || !dev->enabled) { - /* - * Skip IGD initialization in FSP if device - * is disabled in devicetree.cb. - */ + /* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/39457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef Gerrit-Change-Number: 39457 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Correct past participle in comment
by Paul Menzel (Code Review) 15 Mar '20

15 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39456 ) Change subject: soc/intel/icelake: Correct past participle in comment ...................................................................... soc/intel/icelake: Correct past participle in comment Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/icelake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/39456/1 diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 8dd6bfd..99f606b 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -32,7 +32,7 @@ if (!dev || !dev->enabled) { /* * Skip IGD initialization in FSP if device - * is disable in devicetree.cb. + * is disabled in devicetree.cb. */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d Gerrit-Change-Number: 39456 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Match RP number with TGL EDS
by Wonkyu Kim (Code Review) 15 Mar '20

15 Mar '20

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39490 ) Change subject: soc/intel/tigerlake: Match RP number with TGL EDS ...................................................................... soc/intel/tigerlake: Match RP number with TGL EDS Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2. BUG=b:151208838 TEST=build RVP successfully Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129 --- M src/soc/intel/tigerlake/acpi/pcie.asl 1 file changed, 0 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/39490/1 diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index 0191454..63e4d84 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -313,70 +313,3 @@ } } -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/39490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129 Gerrit-Change-Number: 39490 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd_bin: Cleanup spd_get_banks
by EricR Lai (Code Review) 15 Mar '20

15 Mar '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39496 ) Change subject: lib/spd_bin: Cleanup spd_get_banks ...................................................................... lib/spd_bin: Cleanup spd_get_banks Remove the switch case in spd_get_banks. The new DDR type still adapt DDR4 attributes. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 --- M src/lib/spd_bin.c 1 file changed, 6 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/39496/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 625eec8..1300ac8 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -78,22 +78,15 @@ static const int ddr3_banks[4] = { 8, 16, 32, 64 }; static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; - switch (dram_type) { - /* DDR3 and LPDDR3_Intel have the same bank definition */ - case SPD_DRAM_DDR3: - case SPD_DRAM_LPDDR3_INTEL: - if (index >= ARRAY_SIZE(ddr3_banks)) - return -1; - return ddr3_banks[index]; - /* LPDDR3, LPDDR4 and DDR4 have the same bank definition */ - case SPD_DRAM_LPDDR3_JEDEC: - case SPD_DRAM_DDR4: - case SPD_DRAM_LPDDR4: + + if (use_ddr4_params(dram_type)) { if (index >= ARRAY_SIZE(ddr4_banks)) return -1; return ddr4_banks[index]; - default: - return -1; + } else { + if (index >= ARRAY_SIZE(ddr3_banks)) + return -1; + return ddr3_banks[index]; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Gerrit-Change-Number: 39496 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information
by EricR Lai (Code Review) 15 Mar '20

15 Mar '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39495 ) Change subject: lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information ...................................................................... lib/spd_bin: Add LPDDR4X,DDR5 and LPDDR5 SPD information Follow JESD 21-C: DDR4 SPD Document Release 4 to add new DDR type. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 --- M src/include/spd_bin.h M src/lib/spd_bin.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39495/1 diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index c78f7c3..fb771f2 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -29,6 +29,9 @@ #define SPD_DRAM_LPDDR3_JEDEC 0x0F #define SPD_DRAM_DDR4 0x0C #define SPD_DRAM_LPDDR4 0x10 +#define SPD_DRAM_LPDDR4X 0x11 +#define SPD_DRAM_DDR5 0x12 +#define SPD_DRAM_LPDDR5 0x13 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define DDR3_ORGANIZATION 7 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 35bcb4c..625eec8 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -36,10 +36,13 @@ case SPD_DRAM_DDR3: case SPD_DRAM_LPDDR3_INTEL: return false; - /* LPDDR3, LPDDR4 and DDR4 share the same attributes */ + /* Below DDR type share the same attributes */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: case SPD_DRAM_LPDDR4: + case SPD_DRAM_LPDDR4X: + case SPD_DRAM_DDR5: + case SPD_DRAM_LPDDR5: return true; default: printk(BIOS_ERR, "Defaulting to using DDR4 params. Please add dram_type check for %d to %s\n", @@ -60,6 +63,12 @@ return "DDR4"; case SPD_DRAM_LPDDR4: return "LPDDR4"; + case SPD_DRAM_LPDDR4X: + return "LPDDR4X"; + case SPD_DRAM_DDR5: + return "DDR5"; + case SPD_DRAM_LPDDR5: + return "LPDDR5"; } return "UNKNOWN"; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I455c9e4c884ae74c72572be6dc2bd281a660e517 Gerrit-Change-Number: 39495 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable CNVi through dev_enabled
by Srinidhi N Kaushik (Code Review) 15 Mar '20

15 Mar '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39465 ) Change subject: soc/intel/tigerlake: Enable CNVi through dev_enabled ...................................................................... soc/intel/tigerlake: Enable CNVi through dev_enabled Check for dev enabled status for CNVi and update the UPD accordingly. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/39465/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d23148a..93c8126 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -214,10 +214,6 @@ /* Enable Pch iSCLK */ uint8_t pch_isclk; - /* CNVi */ - uint8_t CnviMode; - uint8_t CnviBtCore; - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { FORCE_DISABLE, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 14997c5..7863fd9 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -150,8 +150,11 @@ params->PchLanEnable = dev->enabled; /* CNVi */ - params->CnviMode = config->CnviMode; - params->CnviBtCore = config->CnviBtCore; + dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); + if (dev) + params->CnviMode = dev->enabled; + else + params->CnviMode = 0; /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; -- To view, visit https://review.coreboot.org/c/coreboot/+/39465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051 Gerrit-Change-Number: 39465 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020