coreboot-gerrit March 2020

coreboot-gerrit@coreboot.org

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3326 discussions

Change in coreboot[master]: util/amdfwtool : Fix file open error msg
by Felix Held (Code Review) 17 Mar '20

17 Mar '20

Hello Eric Peers, Rob Barnes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39598 to review the following change. Change subject: util/amdfwtool : Fix file open error msg ...................................................................... util/amdfwtool : Fix file open error msg Print out the name of the file that failed to open. BUG=none TEST=rerun build-board.sh with missing files BRANCH=none Signed-off-by: Eric Peers <epeers(a)google.com> Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Rob Barnes <robbarnes(a)google.com> Commit-Queue: Rob Barnes <robbarnes(a)google.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39598/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 5bcc0a7..4f1e8ba 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -575,7 +575,8 @@ fd = open(src_file, O_RDONLY); if (fd < 0) { - printf("Error: %s\n", strerror(errno)); + printf("Error opening file: %s: %s\n", + src_file, strerror(errno)); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Gerrit-Change-Number: 39598 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake
by Franklin (Yanjin) He (Code Review) 17 Mar '20

17 Mar '20

Franklin (Yanjin) He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39579 ) Change subject: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake ...................................................................... Patch Set 3: (5 comments) Marked off comments addressed in the latest patchset https://review.coreboot.org/c/coreboot/+/39579/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39579/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/apollolake: enable GMM in devicetree for Gemini Lake > Almost what I was looking for, no need for the patch to be Private. […] Done https://review.coreboot.org/c/coreboot/+/39579/1//COMMIT_MSG@9 PS1, Line 9: Enables GMM if the pci device is enabled in the device tree for Gemini > s/device tree/devicetree/ Done https://review.coreboot.org/c/coreboot/+/39579/1//COMMIT_MSG@10 PS1, Line 10: Lake > . […] Done https://review.coreboot.org/c/coreboot/+/39579/1//COMMIT_MSG@12 PS1, Line 12: A port of 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b > This ports `commit <hash>`. […] Done https://review.coreboot.org/c/coreboot/+/39579/1//COMMIT_MSG@16 PS1, Line 16: > This might be just a Gerrit display thing. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Gerrit-Change-Number: 39579 Gerrit-PatchSet: 3 Gerrit-Owner: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 23:00:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake
by Karthik Ramasubramanian (Code Review) 17 Mar '20

17 Mar '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39579 ) Change subject: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/39579/1/src/soc/intel/apollolake/c… File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/c/coreboot/+/39579/1/src/soc/intel/apollolake/c… PS1, Line 637: silconfig->Gmm = dev ? dev->enabled : 0; > Considering this function is glk_fsk_silicon.. […] Is it required on all the GLK devices or is it required for select variants? If only for select variants, then no need to print an error and enable it only on those variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/39579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Gerrit-Change-Number: 39579 Gerrit-PatchSet: 3 Gerrit-Owner: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 22:58:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Franklin (Yanjin) He <franklinh(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by Bora Guvendik (Code Review) 17 Mar '20

17 Mar '20

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 5: > Patch Set 3: > > > Patch Set 3: > > > > > Patch Set 3: > > > > > > Should we create deltaue in variants as well? Or just let it in baseboard? I think it is different variants. > > > > The plan is to add deltaur once we have the GPIO config. for the moment we focus on Deltan > > LGTM. I ended up adding deltaur in variants to make buildbot happy. Let me know if it looks ok. -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Mar 2020 22:54:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake
by Franklin (Yanjin) He (Code Review) 17 Mar '20

17 Mar '20

Franklin (Yanjin) He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39579 ) Change subject: soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/39579/1/src/soc/intel/apollolake/c… File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/c/coreboot/+/39579/1/src/soc/intel/apollolake/c… PS1, Line 637: silconfig->Gmm = dev ? dev->enabled : 0; > I am not sure if adding an error print here is really correct. […] Considering this function is glk_fsk_silicon..blah, this should only be called for Gemini Lake APs which does have this device. -- To view, visit https://review.coreboot.org/c/coreboot/+/39579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Gerrit-Change-Number: 39579 Gerrit-PatchSet: 2 Gerrit-Owner: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Franklin (Yanjin) He <franklinh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Mar 2020 22:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Set I2c clock reference to 150MHz
by Felix Held (Code Review) 17 Mar '20

17 Mar '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39589 ) Change subject: soc/amd/picasso: Set I2c clock reference to 150MHz ...................................................................... soc/amd/picasso: Set I2c clock reference to 150MHz Picasso uses a 150MHz reference clock for the Designware I2c devices. This update allows us to get the correct speeds out. BUG=b:143885765 TEST=Trembyle has 400kHz I2c clock Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… --- M src/soc/amd/picasso/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/39589/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index acceb00..e193755 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -196,7 +196,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 150 config PICASSO_LPC_IOMUX bool -- To view, visit https://review.coreboot.org/c/coreboot/+/39589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60 Gerrit-Change-Number: 39589 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/designware: Add 150MHz clock speed
by Felix Held (Code Review) 17 Mar '20

17 Mar '20

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39588 to review the following change. Change subject: drivers/i2c/designware: Add 150MHz clock speed ...................................................................... drivers/i2c/designware: Add 150MHz clock speed BUG=b:143885765 TEST=I2c clock speed on trembyle is 400kHz Change-Id: I50e904822823a6fc173d4d4b76f0882b4ce81ae8 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Daniel Kurtz <djkurtz(a)chromium.org> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/39588/1 diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 9eda827..5e57e5a 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -214,6 +214,13 @@ }, }, { + .clk_speed_mhz = 150, + .freq = { + .ticks = 600, + .ns = 4000, + }, + }, + { .clk_speed_mhz = 216, .freq = { .ticks = 1080, -- To view, visit https://review.coreboot.org/c/coreboot/+/39588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50e904822823a6fc173d4d4b76f0882b4ce81ae8 Gerrit-Change-Number: 39588 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by Tim Wawrzynczak (Code Review) 17 Mar '20

17 Mar '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39502 ) Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... Patch Set 5: > Patch Set 4: > > This two projects are like combine Sarien and Drallion... So far I can tell from HW design. I've been thinking of it like Volteer (TGL) + Drallion (Wilco) 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Mar 2020 22:41:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/deltaur: add deltaur mainboard initial support
by Bora Guvendik (Code Review) 17 Mar '20

17 Mar '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Selma Bensaid, Duncan Laurie, Tim Wawrzynczak, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39502 to look at the new patch set (#5). Change subject: mb/google/deltaur: add deltaur mainboard initial support ...................................................................... mb/google/deltaur: add deltaur mainboard initial support Created a new Google baseboard named deltaur, taking volteer as a starting point. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 --- A src/mainboard/google/deltaur/Kconfig A src/mainboard/google/deltaur/Kconfig.name A src/mainboard/google/deltaur/Makefile.inc A src/mainboard/google/deltaur/board_info.txt A src/mainboard/google/deltaur/bootblock.c A src/mainboard/google/deltaur/chromeos.c A src/mainboard/google/deltaur/chromeos.fmd A src/mainboard/google/deltaur/dsdt.asl A src/mainboard/google/deltaur/ec.c A src/mainboard/google/deltaur/mainboard.c A src/mainboard/google/deltaur/smihandler.c A src/mainboard/google/deltaur/variants/baseboard/Makefile.inc A src/mainboard/google/deltaur/variants/baseboard/devicetree.cb A src/mainboard/google/deltaur/variants/baseboard/gpio.c A src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/deltaur/variants/deltan/Makefile.inc A src/mainboard/google/deltaur/variants/deltan/gpio.c A src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h A src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h A src/mainboard/google/deltaur/variants/deltan/overridetree.cb A src/mainboard/google/deltaur/variants/deltaur/Makefile.inc A src/mainboard/google/deltaur/variants/deltaur/gpio.c A src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h A src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h A src/mainboard/google/deltaur/variants/deltaur/overridetree.cb 27 files changed, 841 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39502/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Gerrit-Change-Number: 39502 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src (minus soc and mainboard): Remove copyright notices
by Patrick Georgi (Code Review) 17 Mar '20

17 Mar '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39611 ) Change subject: src (minus soc and mainboard): Remove copyright notices ...................................................................... src (minus soc and mainboard): Remove copyright notices They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/Kconfig M src/commonlib/include/commonlib/stdlib.h M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/64bit/entry64.inc M src/drivers/amd/agesa/exit_car.S M src/drivers/analogix/anx7625/Kconfig M src/drivers/analogix/anx7625/Makefile.inc M src/drivers/analogix/anx7625/anx7625.c M src/drivers/analogix/anx7625/anx7625.h M src/drivers/aspeed/common/ast_drv.h M src/drivers/aspeed/common/ast_main.c M src/drivers/aspeed/common/ast_post.c M src/drivers/aspeed/common/ast_tables.h M src/drivers/gfx/generic/chip.h M src/drivers/gfx/generic/generic.c M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/ptn3460/ptn3460.h M src/drivers/i2c/rt1011/chip.h M src/drivers/i2c/rt1011/rt1011.c M src/drivers/ipmi/ipmi_fru.c M src/drivers/ipmi/ipmi_ops.c M src/drivers/ipmi/ipmi_ops.h M src/drivers/spi/spi_sdcard.c M src/drivers/uart/pl011.h M src/ec/acpi/ec.asl M src/ec/acpi/ec.c M src/ec/acpi/ec.h M src/ec/compal/ene932/acpi/ac.asl M src/ec/compal/ene932/acpi/battery.asl M src/ec/compal/ene932/acpi/ec.asl M src/ec/compal/ene932/acpi/superio.asl M src/ec/compal/ene932/chip.h M src/ec/compal/ene932/ec.c M src/ec/compal/ene932/ec.h M src/ec/ec.h M src/ec/google/chromeec/acpi/ac.asl M src/ec/google/chromeec/acpi/als.asl M src/ec/google/chromeec/acpi/battery.asl M src/ec/google/chromeec/acpi/cros_ec.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/emem.asl M src/ec/google/chromeec/acpi/keyboard_backlight.asl M src/ec/google/chromeec/acpi/pd.asl M src/ec/google/chromeec/acpi/superio.asl M src/ec/google/chromeec/acpi/tbmc.asl M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_acpi.c M src/ec/google/chromeec/ec_boardid.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/ec_skuid.c M src/ec/google/chromeec/ec_spi.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/smm.h M src/ec/google/chromeec/switches.c M src/ec/google/chromeec/vboot_storage.c M src/ec/google/chromeec/vstore.c M src/ec/google/common/mec.c M src/ec/google/common/mec.h M src/ec/google/wilco/acpi/ac.asl M src/ec/google/wilco/acpi/battery.asl M src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_dev.asl M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl M src/ec/google/wilco/acpi/lid.asl M src/ec/google/wilco/acpi/platform.asl M src/ec/google/wilco/acpi/privacy.asl M src/ec/google/wilco/acpi/superio.asl M src/ec/google/wilco/acpi/ucsi.asl M src/ec/google/wilco/acpi/vbtn.asl M src/ec/google/wilco/boardid.c M src/ec/google/wilco/bootblock.c M src/ec/google/wilco/bootblock.h M src/ec/google/wilco/chip.c M src/ec/google/wilco/chip.h M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h M src/ec/google/wilco/ec.h M src/ec/google/wilco/mailbox.c M src/ec/google/wilco/romstage.c M src/ec/google/wilco/romstage.h M src/ec/google/wilco/smihandler.c M src/ec/google/wilco/smm.h M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/Makefile.inc M src/ec/hp/kbc1126/acpi/ac.asl M src/ec/hp/kbc1126/acpi/battery.asl M src/ec/hp/kbc1126/acpi/ec.asl M src/ec/hp/kbc1126/acpi/lid.asl M src/ec/hp/kbc1126/chip.h M src/ec/hp/kbc1126/early_init.c M src/ec/hp/kbc1126/ec.c M src/ec/hp/kbc1126/ec.h M src/ec/kontron/it8516e/acpi/ec.asl M src/ec/kontron/it8516e/acpi/pm_channels.asl M src/ec/kontron/it8516e/chip.h M src/ec/kontron/it8516e/ec.c M src/ec/kontron/it8516e/ec.h M src/ec/kontron/kempld/chip.h M src/ec/kontron/kempld/early_kempld.c M src/ec/kontron/kempld/kempld.c M src/ec/kontron/kempld/kempld.h M src/ec/kontron/kempld/kempld_internal.h M src/ec/lenovo/h8/acpi/ac.asl M src/ec/lenovo/h8/acpi/battery.asl M src/ec/lenovo/h8/acpi/beep.asl M src/ec/lenovo/h8/acpi/ec.asl M src/ec/lenovo/h8/acpi/lid.asl M src/ec/lenovo/h8/acpi/sleepbutton.asl M src/ec/lenovo/h8/acpi/systemstatus.asl M src/ec/lenovo/h8/acpi/thinkpad.asl M src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl M src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl M src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl M src/ec/lenovo/h8/bluetooth.c M src/ec/lenovo/h8/chip.h M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/h8.h M src/ec/lenovo/h8/panic.c M src/ec/lenovo/h8/sense.c M src/ec/lenovo/h8/ssdt.c M src/ec/lenovo/h8/vboot.c M src/ec/lenovo/h8/wwan.c M src/ec/lenovo/pmh7/chip.h M src/ec/lenovo/pmh7/pmh7.c M src/ec/lenovo/pmh7/pmh7.h M src/ec/purism/librem/acpi/ac.asl M src/ec/purism/librem/acpi/battery.asl M src/ec/purism/librem/acpi/ec.asl M src/ec/quanta/ene_kb3940q/acpi/ac.asl M src/ec/quanta/ene_kb3940q/acpi/battery.asl M src/ec/quanta/ene_kb3940q/acpi/ec.asl M src/ec/quanta/ene_kb3940q/acpi/superio.asl M src/ec/quanta/ene_kb3940q/chip.h M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/ene_kb3940q/ec.h M src/ec/quanta/it8518/acpi/ac.asl M src/ec/quanta/it8518/acpi/battery.asl M src/ec/quanta/it8518/acpi/ec.asl M src/ec/quanta/it8518/acpi/superio.asl M src/ec/quanta/it8518/chip.h M src/ec/quanta/it8518/ec.c M src/ec/quanta/it8518/ec.h M src/ec/roda/it8518/Kconfig M src/ec/roda/it8518/Makefile.inc M src/ec/roda/it8518/acpi/ac.asl M src/ec/roda/it8518/acpi/battery.asl M src/ec/roda/it8518/acpi/ec.asl M src/ec/roda/it8518/acpi/lid.asl M src/ec/roda/it8518/chip.h M src/ec/roda/it8518/ec.c M src/ec/smsc/mec1308/acpi/ac.asl M src/ec/smsc/mec1308/acpi/battery.asl M src/ec/smsc/mec1308/acpi/ec.asl M src/ec/smsc/mec1308/chip.h M src/ec/smsc/mec1308/ec.c M src/ec/smsc/mec1308/ec.h M src/include/assert.h M src/include/base3.h M src/include/bcd.h M src/include/boardid.h M src/include/boot_device.h M src/include/bootblock_common.h M src/include/bootmem.h M src/include/bootmode.h M src/include/bootsplash.h M src/include/bootstate.h M src/include/cbfs.h M src/include/cbmem.h M src/include/console/cbmem_console.h M src/include/console/console.h M src/include/console/flash.h M src/include/console/ne2k.h M src/include/console/post_codes.h M src/include/console/spi.h M src/include/console/uart.h M src/include/console/usb.h M src/include/console/vtxprintf.h M src/include/cper.h M src/include/cpu/amd/msr.h M src/include/cpu/intel/l2_cache.h M src/include/cpu/intel/microcode.h M src/include/cpu/intel/speedstep.h M src/include/cpu/intel/turbo.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/cr.h M src/include/cpu/x86/mp.h M src/include/cpu/x86/name.h M src/include/cpu/x86/pae.h M src/include/cpu/x86/smm.h M src/include/crc_byte.h M src/include/device/azalia.h M src/include/device/azalia_device.h M src/include/device/dram/common.h M src/include/device/dram/ddr2.h M src/include/device/dram/ddr3.h M src/include/device/dram/ddr4.h M src/include/device/i2c.h M src/include/device/i2c_simple.h M src/include/device/pci_ehci.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h M src/include/device/spi.h M src/include/dimm_info_util.h M src/include/edid.h M src/include/efi/efi_datatype.h M src/include/elog.h M src/include/fmap.h M src/include/gic.h M src/include/gpio.h M src/include/halt.h M src/include/imd.h M src/include/lib.h M src/include/memlayout.h M src/include/memrange.h M src/include/mrc_cache.h M src/include/nhlt.h M src/include/pc80/i8254.h M src/include/pc80/i8259.h M src/include/pc80/vga.h M src/include/pc80/vga_io.h M src/include/program_loading.h M src/include/random.h M src/include/reg_script.h M src/include/region_file.h M src/include/rmodule.h M src/include/romstage_handoff.h M src/include/rtc.h M src/include/sar.h M src/include/sdram_mode.h M src/include/smbios.h M src/include/smmstore.h M src/include/spd.h M src/include/spd_bin.h M src/include/spd_ddr2.h M src/include/spi_bitbang.h M src/include/spi_sdcard.h M src/include/stage_cache.h M src/include/superio/conf_mode.h M src/include/symbols.h M src/include/thread.h M src/include/timer.h M src/include/timestamp.h M src/include/trace.h M src/include/types.h M src/include/uuid.h M src/include/wrdd.h M src/lib/Makefile.inc M src/lib/boot_device.c M src/lib/bootblock.c M src/lib/bootmem.c M src/lib/bootmode.c M src/lib/bootsplash.c M src/lib/cbfs.c M src/lib/cbmem_common.c M src/lib/cbmem_console.c M src/lib/cbmem_stage_cache.c M src/lib/coreboot_table.c M src/lib/crc_byte.c M src/lib/decompressor.c M src/lib/dimm_info_util.c M src/lib/ext_stage_cache.c M src/lib/fit_payload.c M src/lib/fmap.c M src/lib/gcc.c M src/lib/gcov-glue.c M src/lib/gnat/Makefile.inc M src/lib/gpio.c M src/lib/halt.c M src/lib/hardwaremain.c M src/lib/hw-time-timer.adb M src/lib/imd.c M src/lib/imd_cbmem.c M src/lib/jpeg.c M src/lib/jpeg.h M src/lib/libgcc.c M src/lib/memrange.c M src/lib/nhlt.c M src/lib/primitive_memtest.c M src/lib/prog_loaders.c M src/lib/prog_ops.c M src/lib/program.ld M src/lib/reg_script.c M src/lib/region_file.c M src/lib/reset.c M src/lib/rmodule.c M src/lib/romstage_handoff.c M src/lib/rtc.c M src/lib/selfboot.c M src/lib/spd_bin.c M src/lib/thread.c M src/lib/timer.c M src/lib/timer_queue.c M src/lib/timestamp.c M src/lib/trace.c M src/lib/wrdd.c M src/northbridge/amd/agesa/BiosCallOuts.h M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/Makefile.inc M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/agesa/dimmSpd.h M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family14/Makefile.inc M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family14/pci_devs.h M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family15tn/Makefile.inc M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family15tn/chip.h M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family15tn/pci_devs.h M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/agesa/family16kb/Makefile.inc M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/chip.h M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/agesa/family16kb/pci_devs.h M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/agesa/state_machine.h M src/northbridge/amd/pi/00630F01/Kconfig M src/northbridge/amd/pi/00630F01/Makefile.inc M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/chip.h M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00630F01/iommu.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00630F01/pci_devs.h M src/northbridge/amd/pi/00660F01/Kconfig M src/northbridge/amd/pi/00660F01/Makefile.inc M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl M src/northbridge/amd/pi/00660F01/chip.h M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00730F01/Makefile.inc M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/chip.h M src/northbridge/amd/pi/00730F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/iommu.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/00730F01/pci_devs.h M src/northbridge/amd/pi/00730F01/state_machine.c M src/northbridge/amd/pi/Kconfig M src/northbridge/amd/pi/Makefile.inc M src/northbridge/amd/pi/dimmSpd.h M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/romstage.c M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/gm45/acpi/peg.asl M src/northbridge/intel/gm45/chip.h M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/early_reset.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_rcomp_calibration.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/acpi/peg.asl M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/mchbar_regs.h M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/pcie.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/raminit.h M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i440bx/Makefile.inc M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl M src/northbridge/intel/i440bx/i440bx.h M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i440bx/northbridge.h M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/acpi/hostbridge.asl M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/acpi/igd.asl M src/northbridge/intel/i945/acpi/peg.asl M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/errata.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/i945/romstage.c M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/Makefile.inc M src/northbridge/intel/ironlake/acpi.c M src/northbridge/intel/ironlake/acpi/hostbridge.asl M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/chip.h M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/finalize.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/ironlake/raminit.h M src/northbridge/intel/ironlake/raminit_tables.c M src/northbridge/intel/ironlake/raminit_tables.h M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc M src/northbridge/intel/pineview/acpi.c M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/pineview/acpi/peg.asl M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/iomap.h M src/northbridge/intel/pineview/mchbar_regs.h M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/pineview/raminit.h M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/peg.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/common.c M src/northbridge/intel/sandybridge/early_dmi.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/gma.h M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit.h M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/raminit_native.h M src/northbridge/intel/sandybridge/raminit_sandy.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/acpi.c M src/northbridge/intel/x4x/acpi/hostbridge.asl M src/northbridge/intel/x4x/acpi/peg.asl M src/northbridge/intel/x4x/acpi/x4x.asl M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/chip.h M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/iomap.h M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/x4x.h M src/security/Kconfig M src/security/intel/Kconfig M src/security/intel/txt/Kconfig M src/security/memory/Kconfig M src/security/memory/memory.c M src/security/memory/memory.h M src/security/memory/memory_clear.c M src/security/tpm/Kconfig M src/security/tpm/tis.h M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/common/tss_common.h M src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/vendor/cr50/Kconfig M src/security/tpm/tss/vendor/cr50/cr50.h M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/bootmode.c M src/security/vboot/common.c M src/security/vboot/misc.h M src/security/vboot/mrc_cache_hash_tpm.c M src/security/vboot/symbols.h M src/security/vboot/vbnv.c M src/security/vboot/vbnv.h M src/security/vboot/vbnv_cmos.c M src/security/vboot/vbnv_ec.c M src/security/vboot/vbnv_flash.c M src/security/vboot/vbnv_layout.h M src/security/vboot/vboot_common.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/security/vboot/verstage.c M src/southbridge/amd/agesa/Kconfig M src/southbridge/amd/agesa/Makefile.inc M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl M src/southbridge/amd/agesa/hudson/acpi/audio.asl M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/agesa/hudson/acpi/lpc.asl M src/southbridge/amd/agesa/hudson/acpi/pci_int.asl M src/southbridge/amd/agesa/hudson/acpi/pcie.asl M src/southbridge/amd/agesa/hudson/acpi/usb.asl M src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h M src/southbridge/amd/agesa/hudson/amd_pci_int_types.h M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/chip.h M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/ide.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/imc.h M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/pci.c M src/southbridge/amd/agesa/hudson/pci_devs.h M src/southbridge/amd/agesa/hudson/pcie.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/smbus.c M src/southbridge/amd/agesa/hudson/smbus.h M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/smi_util.c M src/southbridge/amd/agesa/hudson/smihandler.c M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/cimx/Kconfig M src/southbridge/amd/cimx/Makefile.inc M src/southbridge/amd/cimx/sb800/Amd.h M src/southbridge/amd/cimx/sb800/AmdSbLib.h M src/southbridge/amd/cimx/sb800/Kconfig M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/SBPLATFORM.h M src/southbridge/amd/cimx/sb800/acpi/audio.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/lpc.asl M src/southbridge/amd/cimx/sb800/acpi/pcie.asl M src/southbridge/amd/cimx/sb800/acpi/smbus.asl M src/southbridge/amd/cimx/sb800/acpi/usb.asl M src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h M src/southbridge/amd/cimx/sb800/amd_pci_int_types.h M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/cfg.h M src/southbridge/amd/cimx/sb800/chip.h M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/cimx/sb800/fan.c M src/southbridge/amd/cimx/sb800/fan.h M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/lpc.h M src/southbridge/amd/cimx/sb800/pci_devs.h M src/southbridge/amd/cimx/sb800/ramtop.c M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb800/sb_cimx.h M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/cimx/sb800/smbus.h M src/southbridge/amd/cimx/sb800/smbus_spd.c M src/southbridge/amd/cimx/sb800/smbus_spd.h M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/common/acpi/sleepstates.asl M src/southbridge/amd/common/amd_defs.h M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/amd/common/amd_pci_util.h M src/southbridge/amd/common/reset.h M src/southbridge/amd/pi/Kconfig M src/southbridge/amd/pi/Makefile.inc M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/acpi/AmdImc.asl M src/southbridge/amd/pi/hudson/acpi/audio.asl M src/southbridge/amd/pi/hudson/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/lpc.asl M src/southbridge/amd/pi/hudson/acpi/pci_int.asl M src/southbridge/amd/pi/hudson/acpi/pcie.asl M src/southbridge/amd/pi/hudson/acpi/usb.asl M src/southbridge/amd/pi/hudson/amd_pci_int_defs.h M src/southbridge/amd/pi/hudson/amd_pci_int_types.h M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/chip.h M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/amd/pi/hudson/fchec.h M src/southbridge/amd/pi/hudson/gpio.c M src/southbridge/amd/pi/hudson/gpio.h M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/ide.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/imc.h M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/pci.c M src/southbridge/amd/pi/hudson/pci_devs.h M src/southbridge/amd/pi/hudson/pcie.c M src/southbridge/amd/pi/hudson/reset.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/smbus.c M src/southbridge/amd/pi/hudson/smbus.h M src/southbridge/amd/pi/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/pi/hudson/smi_util.c M src/southbridge/amd/pi/hudson/smihandler.c M src/southbridge/amd/pi/hudson/uart.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/acpi/audio.asl M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/irqlinks.asl M src/southbridge/intel/bd82x6x/acpi/lpc.asl M src/southbridge/intel/bd82x6x/acpi/pch.asl M src/southbridge/intel/bd82x6x/acpi/sata.asl M src/southbridge/intel/bd82x6x/acpi/usb.asl M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/early_me_mrc.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/acpi/pcie.asl M src/southbridge/intel/common/acpi/pcie_port.asl M src/southbridge/intel/common/acpi/platform.asl M src/southbridge/intel/common/acpi/sleepstates.asl M src/southbridge/intel/common/acpi/smbus.asl M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/finalize.h M src/southbridge/intel/common/firmware/Kconfig M src/southbridge/intel/common/firmware/Makefile.inc M src/southbridge/intel/common/gpio.c M src/southbridge/intel/common/gpio.h M src/southbridge/intel/common/madt.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmclib.c M src/southbridge/intel/common/pmclib.h M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/rcba.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h M src/southbridge/intel/common/rtc.c M src/southbridge/intel/common/rtc.h M src/southbridge/intel/common/smbus.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/Makefile.inc M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/acpi/intx.asl M src/southbridge/intel/i82371eb/acpi/isabridge.asl M src/southbridge/intel/i82371eb/acpi/pirq.asl M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/chip.h M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82371eb/i82371eb.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/usb.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/chip.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/ide.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/nvs.h M src/southbridge/intel/i82801dx/pci.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801dx/usb.c M src/southbridge/intel/i82801dx/usb2.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/acpi/ac97.asl M src/southbridge/intel/i82801gx/acpi/audio.asl M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/acpi/ich7.asl M src/southbridge/intel/i82801gx/acpi/irqlinks.asl M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/pata.asl M src/southbridge/intel/i82801gx/acpi/pci.asl M src/southbridge/intel/i82801gx/acpi/sata.asl M src/southbridge/intel/i82801gx/acpi/usb.asl M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/nic.c M src/southbridge/intel/i82801gx/nvs.h M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/sata.h M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/Makefile.inc M src/southbridge/intel/i82801ix/acpi/audio.asl M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801ix/acpi/irqlinks.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl M src/southbridge/intel/i82801ix/acpi/pci.asl M src/southbridge/intel/i82801ix/acpi/sata.asl M src/southbridge/intel/i82801ix/acpi/usb.asl M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801ix/dmi_setup.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/nvs.h M src/southbridge/intel/i82801ix/pci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/Makefile.inc M src/southbridge/intel/i82801jx/acpi/audio.asl M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/acpi/irqlinks.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl M src/southbridge/intel/i82801jx/acpi/pci.asl M src/southbridge/intel/i82801jx/acpi/sata.asl M src/southbridge/intel/i82801jx/acpi/usb.asl M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/nvs.h M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/Makefile.inc M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/ibexpeak/chip.h M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/early_thermal.c M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/acpi/audio.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/irqlinks.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/sata.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/early_me.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/hda_verb.h M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/nvs.h M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/ricoh/rl5c476/Kconfig M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ricoh/rl5c476/rl5c476.h M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/Kconfig M src/southbridge/ti/pci7420/Makefile.inc M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/chip.h M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pci7420/pci7420.h M src/southbridge/ti/pcixx12/Kconfig M src/southbridge/ti/pcixx12/Makefile.inc M src/southbridge/ti/pcixx12/pcixx12.c M src/vendorcode/amd/Kconfig M src/vendorcode/amd/agesa/common/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f15tn/Makefile.inc M src/vendorcode/amd/agesa/f16kb/Makefile.inc M src/vendorcode/amd/cimx/sb800/Makefile.inc M src/vendorcode/amd/cimx/sb900/Makefile.inc M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/cavium/Kconfig M src/vendorcode/cavium/Makefile.inc M src/vendorcode/eltan/Makefile.inc M src/vendorcode/eltan/security/Kconfig M src/vendorcode/eltan/security/Makefile.inc M src/vendorcode/eltan/security/mboot/Kconfig M src/vendorcode/eltan/security/mboot/Makefile.inc M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/eltan/security/mboot/mboot.h M src/vendorcode/eltan/security/mboot/mboot_func.c M src/vendorcode/eltan/security/verified_boot/Kconfig M src/vendorcode/eltan/security/verified_boot/Makefile.inc M src/vendorcode/eltan/security/verified_boot/vboot_check.c M src/vendorcode/eltan/security/verified_boot/vboot_check.h M src/vendorcode/google/Kconfig M src/vendorcode/google/Makefile.inc M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/acpi.c M src/vendorcode/google/chromeos/acpi/amac.asl M src/vendorcode/google/chromeos/acpi/chromeos.asl M src/vendorcode/google/chromeos/acpi/gnvs.asl M src/vendorcode/google/chromeos/acpi/ramoops.asl M src/vendorcode/google/chromeos/acpi/vpd.asl M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/cr50_enable_update.c M src/vendorcode/google/chromeos/dsm_calib.c M src/vendorcode/google/chromeos/elog.c M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/gnvs.h M src/vendorcode/google/chromeos/ramoops.c M src/vendorcode/google/chromeos/sar.c M src/vendorcode/google/chromeos/symbols.h M src/vendorcode/google/chromeos/tpm2.c M src/vendorcode/google/chromeos/vpd_calibration.c M src/vendorcode/google/chromeos/vpd_mac.c M src/vendorcode/google/chromeos/vpd_serialno.c M src/vendorcode/google/chromeos/watchdog.c M src/vendorcode/google/chromeos/wrdd.c M src/vendorcode/google/smbios.c M src/vendorcode/intel/Kconfig M src/vendorcode/intel/Makefile.inc M src/vendorcode/siemens/Kconfig M src/vendorcode/siemens/Makefile.inc M src/vendorcode/siemens/hwilib/Makefile.inc M src/vendorcode/siemens/hwilib/hwilib.c M src/vendorcode/siemens/hwilib/hwilib.h 986 files changed, 0 insertions(+), 1,256 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/39611/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Gerrit-Change-Number: 39611 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2020