coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: soc/mediatek: dsi: Unify format to bpp conversion
by Yu-Ping Wu (Code Review) 12 Feb '20

12 Feb '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34770 ) Change subject: soc/mediatek: dsi: Unify format to bpp conversion ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/34770/11/src/soc/mediatek/common/d… File src/soc/mediatek/common/dsi.c: https://review.coreboot.org/c/coreboot/+/34770/11/src/soc/mediatek/common/d… PS11, Line 29: MIPI_DSI_FMT_RGB666 > Probably, yeah. Otherwise I wouldn't know what the difference between 666 and 666_PACKED should be. Uploaded CB:38845 -- To view, visit https://review.coreboot.org/c/coreboot/+/34770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd405220b73859e5592c68f498af07eef8d7edbc Gerrit-Change-Number: 34770 Gerrit-PatchSet: 11 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 12 Feb 2020 03:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/hatch/mainboard.c: Accommodate larger SKU id space
by Edward O'Callaghan (Code Review) 12 Feb '20

12 Feb '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38844 ) Change subject: mainboard/hatch/mainboard.c: Accommodate larger SKU id space ...................................................................... Patch Set 2: Code-Review+2 > Patch Set 2: > > (2 comments) Much better! -- To view, visit https://review.coreboot.org/c/coreboot/+/38844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5a3f47989f596b838739becfb1da1bdaf16dd27 Gerrit-Change-Number: 38844 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Feb 2020 02:49:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/hatch/mainboard.c: Accommodate larger SKU id space
by Kangheui Won (Code Review) 12 Feb '20

12 Feb '20

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38844 ) Change subject: mainboard/hatch/mainboard.c: Accommodate larger SKU id space ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/38844/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38844/1//COMMIT_MSG@7 PS1, Line 7: mainboard/hatch: Change SKU_MAX to 0x7FFFFFFF > mainboard/hatch/mainboard. […] Done https://review.coreboot.org/c/coreboot/+/38844/1//COMMIT_MSG@9 PS1, Line 9: Default > This doesn't add anything that the code doesn't already say. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5a3f47989f596b838739becfb1da1bdaf16dd27 Gerrit-Change-Number: 38844 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Feb 2020 02:44:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/hatch/mainboard.c: Accommodate larger SKU id space
by Kangheui Won (Code Review) 12 Feb '20

12 Feb '20

Hello Edward O'Callaghan, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38844 to look at the new patch set (#2). Change subject: mainboard/hatch/mainboard.c: Accommodate larger SKU id space ...................................................................... mainboard/hatch/mainboard.c: Accommodate larger SKU id space Allow INT32_MAX SKU id encodings beyond UINT8_MAX. This allows for the SKU id to accommodate up to 4 bytes however we reserve the highest bit for SKU_UNKNOWN to be encoded. BUG=b:149348474 BRANCH=none TEST=none Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ic5a3f47989f596b838739becfb1da1bdaf16dd27 --- M src/mainboard/google/hatch/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/38844/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5a3f47989f596b838739becfb1da1bdaf16dd27 Gerrit-Change-Number: 38844 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mainboard/hatch: Change SKU_MAX to 0x7FFFFFFF
by Edward O'Callaghan (Code Review) 12 Feb '20

12 Feb '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38844 ) Change subject: mainboard/hatch: Change SKU_MAX to 0x7FFFFFFF ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/38844/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38844/1//COMMIT_MSG@7 PS1, Line 7: mainboard/hatch: Change SKU_MAX to 0x7FFFFFFF mainboard/hatch/mainboard.c: Accommodate larger SKU id space https://review.coreboot.org/c/coreboot/+/38844/1//COMMIT_MSG@9 PS1, Line 9: Default This doesn't add anything that the code doesn't already say. I think you want to say something like: ``` Allow INT32_MAX sku id encodings beyond UINT8_MAX. This allows for the sku id to accommodate up to 4 bytes however we reserve the highest bit for SKU_UNKNOWN to be encoded. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/38844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5a3f47989f596b838739becfb1da1bdaf16dd27 Gerrit-Change-Number: 38844 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Feb 2020 02:41:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/hatch: Change SKU_MAX to 0x7FFFFFFF
by Kangheui Won (Code Review) 12 Feb '20

12 Feb '20

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38844 ) Change subject: mainboard/hatch: Change SKU_MAX to 0x7FFFFFFF ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/38844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5a3f47989f596b838739becfb1da1bdaf16dd27 Gerrit-Change-Number: 38844 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Wed, 12 Feb 2020 02:07:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: dsi: Unify format to bpp conversion
by Julius Werner (Code Review) 12 Feb '20

12 Feb '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34770 ) Change subject: soc/mediatek: dsi: Unify format to bpp conversion ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/34770/11/src/soc/mediatek/common/d… File src/soc/mediatek/common/dsi.c: https://review.coreboot.org/c/coreboot/+/34770/11/src/soc/mediatek/common/d… PS11, Line 29: MIPI_DSI_FMT_RGB666 > Happened to see this. Compared to kernel [1], should we return 24 here? […] Probably, yeah. Otherwise I wouldn't know what the difference between 666 and 666_PACKED should be. -- To view, visit https://review.coreboot.org/c/coreboot/+/34770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd405220b73859e5592c68f498af07eef8d7edbc Gerrit-Change-Number: 34770 Gerrit-PatchSet: 11 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 12 Feb 2020 01:59:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by Brandon Breitenstein (Code Review) 12 Feb '20

12 Feb '20

Brandon Breitenstein has uploaded a new patch set (#20) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37871 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... soc/intel/common/block: Enable PMC IPC driver In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 103 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37871/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/37871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3ed262fc700ccc891ec68997a108f5bfbaf9ed Gerrit-Change-Number: 37871 Gerrit-PatchSet: 20 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Device enumeration based on IORESOURCE_ASSIGNED
by Jonathan Zhang (Code Review) 12 Feb '20

12 Feb '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38547 ) Change subject: Device enumeration based on IORESOURCE_ASSIGNED ...................................................................... Device enumeration based on IORESOURCE_ASSIGNED Intel Xeon Scalable Processors has Split IIO architecture, and also in order to support multiple sockets, it is necessary to run device enumeration in consideration of IORESOURCE_ASSIGNED status. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: I69e100ea658fefec905321197b5bd6da1e0e647a --- M src/device/device.c 1 file changed, 18 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38547/1 diff --git a/src/device/device.c b/src/device/device.c index 236b768..879382c 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -380,6 +380,18 @@ if (!resource->size) continue; + /* Skip if IO resource was assigned */ + if (resource->flags & IORESOURCE_ASSIGNED) { + /* Warn if it looks like APICs aren't declared. */ + if(resource->limit == 0xffffffff) { + printk(BIOS_ERR, + "Resource limit looks wrong! (no APIC?)\n"); + printk(BIOS_ERR, "%s %02lx limit %08llx\n", + dev_path(dev), resource->index, resource->limit); + } + continue; + } + /* Propagate the resource alignment to the bridge resource. */ if (resource->align > bridge->align) bridge->align = resource->align; @@ -388,15 +400,6 @@ if (bridge->limit > resource->limit) bridge->limit = resource->limit; - /* Warn if it looks like APICs aren't declared. */ - if ((resource->limit == 0xffffffff) && - (resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, - "Resource limit looks wrong! (no APIC?)\n"); - printk(BIOS_ERR, "%s %02lx limit %08llx\n", - dev_path(dev), resource->index, resource->limit); - } - if (resource->flags & IORESOURCE_IO) { /* * Don't allow potential aliases over the legacy PCI @@ -434,7 +437,7 @@ * address positively decoded by the bridge. */ bridge->size = round(base, bridge->gran) - - round(bridge->base, bridge->align); + round(bridge->base, bridge->align); printk(BIOS_SPEW, "%s %s: base: %llx size: %llx align: %d gran: %d" " limit: %llx done\n", dev_path(bus->dev), @@ -717,6 +720,9 @@ if ((res->flags & IORESOURCE_FIXED)) continue; + if ((res->flags & IORESOURCE_ASSIGNED)) + continue; + lim = resource_limit(&limits, res); if (!lim) continue; @@ -1065,6 +1071,8 @@ for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; + if (res->flags & IORESOURCE_ASSIGNED) + continue; if (res->flags & IORESOURCE_MEM) { allocate_resources(child->link_list, res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); -- To view, visit https://review.coreboot.org/c/coreboot/+/38547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69e100ea658fefec905321197b5bd6da1e0e647a Gerrit-Change-Number: 38547 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

7 28

Change in coreboot[master]: soc/intel/tigerlake: Add code for early tcss
by Brandon Breitenstein (Code Review) 12 Feb '20

12 Feb '20

Brandon Breitenstein has uploaded a new patch set (#32) to the change originally created by Shaunak Saha. ( https://review.coreboot.org/c/coreboot/+/37870 ) Change subject: soc/intel/tigerlake: Add code for early tcss ...................................................................... soc/intel/tigerlake: Add code for early tcss In order for USB Type-C to be detected prior to loading Kernel PMC IPC driver is needed to communicate with PMC in order to correctly set the USB Mux settings. This patch is adding in support for early detection of both USB and Display Port. BUG=b:141608957 BRANCH=NONE TEST: built and booted TGL U RVP Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.c A src/soc/intel/tigerlake/early_tcss.c A src/soc/intel/tigerlake/include/soc/early_tcss.h 5 files changed, 278 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/37870/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/37870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45c3fe9d4a2ec2f2f51b78cca2bd7e623540c00e Gerrit-Change-Number: 37870 Gerrit-PatchSet: 32 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-CC: Divya Sasidharan <divya.s.sasidharan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020