coreboot-gerrit November 2020

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Change in coreboot[master]: sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib exec...
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47080 ) Change subject: sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib execution ...................................................................... sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib execution Change-Id: I213f6063ba8a06740488f44dabf377659bb70579 --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/sc7280/mmu.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47080/1 diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 8844f18..9927677 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -6,5 +6,5 @@ void platform_romstage_main(void) { /* QCLib: DDR init & train */ - qclib_load_and_run(); + //qclib_load_and_run(); } diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c index 9905c29..f6e85a6 100644 --- a/src/soc/qualcomm/sc7280/mmu.c +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -16,6 +16,8 @@ mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_RAM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)(2UL * GiB), (2UL * GiB) , CACHED_RAM); mmu_enable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213f6063ba8a06740488f44dabf377659bb70579 Gerrit-Change-Number: 47080 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: HACK PATCH: To support SPI-NOR driver for Rumi
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47079 ) Change subject: sc7280: HACK PATCH: To support SPI-NOR driver for Rumi ...................................................................... sc7280: HACK PATCH: To support SPI-NOR driver for Rumi - In Rumi, GPIO emulation is not present and CS assert/deassert is done through controller - In soc, CS assert/deassert is done using GPIO - Disable SBL_EN bit in QSPI master config register Change-Id: I2a53c1094b90ac7896e835864848467c52d2a03e Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/qspi.c 1 file changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47079/1 diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c index 3c627a5..fba8f89 100644 --- a/src/soc/qualcomm/sc7280/qspi.c +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -123,15 +123,17 @@ * So to support read transfers that are not preceded by write, set * transfer fragment bit = 1 */ - next->fragment = 1; + next->fragment = 0; next->reserved2 = 0; next->length = 0; next->bounce_src = 0; next->bounce_dst = 0; next->bounce_length = 0; - if (current) + if (current) { current->next_descriptor = (uint32_t)(uintptr_t) next; + current->fragment = 1; + } return next; } @@ -169,6 +171,7 @@ ptr = (void *)(uintptr_t) desc->data_address; if (write) { + desc->fragment = 1; memcpy(ptr, data, data_bytes); } else { desc->bounce_src = (uint32_t)(uintptr_t) ptr; @@ -190,10 +193,12 @@ desc->data_address = (uint32_t)(uintptr_t) data; desc->length = data_bytes; - if (write) + if (write) { + desc->fragment = 1; dcache_clean_by_mva(data, data_bytes); - else + } else { dcache_invalidate_by_mva(data, data_bytes); + } } static void queue_data(uint8_t *data, uint32_t data_bytes, @@ -235,7 +240,7 @@ tx_data_delay = 0; mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | - (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (spi_mode << SPI_MODE_SHIFT) | (PIN_HOLDN) | (FB_CLK_EN) | -- To view, visit https://review.coreboot.org/c/coreboot/+/47079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a53c1094b90ac7896e835864848467c52d2a03e Gerrit-Change-Number: 47079 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: HACK PATCH: sc7280: Comment out gpio and clock dependency
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47078 ) Change subject: HACK PATCH: sc7280: Comment out gpio and clock dependency ...................................................................... HACK PATCH: sc7280: Comment out gpio and clock dependency As clock and gpio supports are not yet present in kodiak build, commenting out those inorder to compile QSPI driver. Change-Id: I148a7bd7910a6d23cbec354fe88b35644a8716bf Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/include/soc/qspi.h M src/soc/qualcomm/sc7280/qspi.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47078/1 diff --git a/src/soc/qualcomm/sc7280/include/soc/qspi.h b/src/soc/qualcomm/sc7280/include/soc/qspi.h index 6c40e7e..570a7cb 100644 --- a/src/soc/qualcomm/sc7280/include/soc/qspi.h +++ b/src/soc/qualcomm/sc7280/include/soc/qspi.h @@ -6,6 +6,8 @@ #ifndef __SOC_QUALCOMM_SC7280_QSPI_H__ #define __SOC_QUALCOMM_SC7280_QSPI_H__ +#define QSPI_BASE 0x088DC000 + struct sc7280_qspi_regs { u32 mstr_cfg; u32 ahb_mstr_cfg; diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c index a6837bc..3c627a5 100644 --- a/src/soc/qualcomm/sc7280/qspi.c +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -7,7 +7,7 @@ #include <soc/addressmap.h> #include <soc/qspi.h> #include <soc/gpio.h> -#include <soc/clock.h> +//#include <soc/clock.h> #include <symbols.h> #include <assert.h> #include <gpio.h> @@ -136,6 +136,7 @@ return next; } +/* static void cs_change(enum cs_state state) { gpio_set(GPIO(15), state == CS_DEASSERT); @@ -154,6 +155,7 @@ gpio_configure(GPIO(14), GPIO14_FUNC_QSPI_CLK, GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); } +*/ static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, enum qspi_mode data_mode, bool write) @@ -251,20 +253,20 @@ void quadspi_init(uint32_t hz) { assert(dcache_line_bytes() == CACHE_LINE_SIZE); - clock_configure_qspi(hz * 4); - configure_gpios(); +// clock_configure_qspi(hz * 4); +// configure_gpios(); reg_init(); } int sc7280_claim_bus(const struct spi_slave *slave) { - cs_change(CS_ASSERT); +// cs_change(CS_ASSERT); return 0; } void sc7280_release_bus(const struct spi_slave *slave) { - cs_change(CS_DEASSERT); +// cs_change(CS_DEASSERT); } static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, -- To view, visit https://review.coreboot.org/c/coreboot/+/47078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148a7bd7910a6d23cbec354fe88b35644a8716bf Gerrit-Change-Number: 47078 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: report hardware watchdog reset after reboot
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45070 ) Change subject: trogdor: report hardware watchdog reset after reboot ...................................................................... trogdor: report hardware watchdog reset after reboot Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I3d03d775634e4f50f83b0e8e16b106b1183ec46b --- M src/soc/qualcomm/sc7180/soc.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45070/1 diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..b529bf6 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -6,6 +6,11 @@ #include <soc/mmu_common.h> #include <soc/symbols.h> #include <soc/aop.h> +#include <elog.h> +#include <console/console.h> + +#define AOSS_CC_RESET_STATUS 0x0C2F0020 +#define WDOG_RESET_BIT_MASK 0x1 static void soc_read_resources(struct device *dev) { @@ -19,6 +24,14 @@ static void soc_init(struct device *dev) { + volatile unsigned int aoss = *(unsigned int *)AOSS_CC_RESET_STATUS; + + printk(BIOS_INFO, "\nSOC: AOSS_CC_RESET_STATUS : %x\n", aoss & WDOG_RESET_BIT_MASK); + printk(BIOS_INFO, "AOSS_CC_RESET_STATUS[%x]..[%x]\n", AOSS_CC_RESET_STATUS, aoss); + + if(aoss & WDOG_RESET_BIT_MASK) + elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED); + aop_fw_load_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d03d775634e4f50f83b0e8e16b106b1183ec46b Gerrit-Change-Number: 45070 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Add UART support
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47526 ) Change subject: sc7280: Add UART support ...................................................................... sc7280: Add UART support This implements the UART driver in SoC Change-Id: Idc91f05c530ae41f212d6a4124dd5796aeaa8dfc Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/qupv3_uart.c 3 files changed, 162 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47526/1 diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index 2fef404..d6f56ba 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -36,4 +36,10 @@ int default 16 +config UART_FOR_CONSOLE + int + default 5 + help + Select the QUP instance to be used for UART console output. + endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 876d7d9..acbb36d 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -19,7 +19,7 @@ verstage-$(CONFIG_SC7280_QSPI) += qspi.c verstage-y += clock.c verstage-y += gpio.c -verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c verstage-y += qupv3_config.c verstage-y += qcom_qup_se.c @@ -34,7 +34,7 @@ romstage-$(CONFIG_SC7280_QSPI) += qspi.c romstage-y += clock.c romstage-y += gpio.c -romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c romstage-y += qupv3_config.c romstage-y += qcom_qup_se.c @@ -46,7 +46,7 @@ ramstage-$(CONFIG_SC7280_QSPI) += qspi.c ramstage-y += clock.c ramstage-y += gpio.c -ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c diff --git a/src/soc/qualcomm/sc7280/qupv3_uart.c b/src/soc/qualcomm/sc7280/qupv3_uart.c new file mode 100644 index 0000000..5679a25 --- /dev/null +++ b/src/soc/qualcomm/sc7280/qupv3_uart.c @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <boot/coreboot_tables.h> +#include <console/uart.h> +#include <soc/clock.h> +#include <soc/qcom_qup_se.h> +#include <soc/qupv3_config.h> +#include <types.h> + +/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ + +#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK 0x1 +#define GENI_STATUS_S_GENI_CMD_ACTIVE_MASK 0x1000 + +#define UART_TX_WATERMARK_MARGIN 4 /* Represented in words */ +#define UART_RX_WATERMARK_MARGIN 8 /* Represented in words */ +#define UART_RX_RFR_WATERMARK_MARGIN 4 /* Represented in words */ +#define UART_TX_BITS_PER_WORD 8 +#define UART_RX_BITS_PER_WORD 8 +#define START_UART_TX 0x8000000 +#define START_UART_RX 0x8000000 + +/* UART FIFO Packing Configuration. */ +/* Start_idx:0, direction:0, len:7, stop:0 */ +#define UART_TX_PACK_VECTOR0 0x0E +/* Start_idx:8, direction:0, len:7, stop:0 */ +#define UART_TX_PACK_VECTOR1 0x10E +/* Start_idx:16, direction:0, len:7, stop:0 */ +#define UART_TX_PACK_VECTOR2 0x20E +/* Start_idx:24, direction:0, len:7, stop:1 */ +#define UART_TX_PACK_VECTOR3 0x30F +/* Start_idx:0, direction:0, len:7, stop:1 */ +#define UART_RX_PACK_VECTOR0 0xF +#define UART_RX_PACK_VECTOR2 0x00 + +void uart_tx_flush(unsigned int idx) +{ + struct qup_regs *regs = qup[idx].regs; + + while (read32(&regs->geni_status) & + GENI_STATUS_M_GENI_CMD_ACTIVE_MASK) + ; +} + +void uart_init(unsigned int idx) +{ + struct qup_regs *regs = qup[idx].regs; + unsigned int reg_value; + unsigned int div, baud_rate, uart_freq; + + /* + * If the RX (secondary) sequencer is already active, it means the core + * has been already initialized in the previous stage. Skip + * configuration + */ + if (read32(&regs->geni_status) & GENI_STATUS_S_GENI_CMD_ACTIVE_MASK) + return; + + qupv3_se_fw_load_and_init(idx, SE_PROTOCOL_UART, FIFO); + clock_enable_qup(idx); + + reg_value = read32(&regs->geni_fw_revision_ro); + reg_value &= GENI_FW_REVISION_RO_PROTOCOL_MASK; + reg_value >>= GENI_FW_REVISION_RO_PROTOCOL_SHIFT; + + assert(reg_value == SE_PROTOCOL_UART); + + baud_rate = get_uart_baudrate(); + + /* sc7280 requires 16 clock pulses to sample 1 bit of data */ + uart_freq = baud_rate * 16; + + div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq); + write32(&regs->geni_ser_m_clk_cfg, (div << 4) | 1); + write32(&regs->geni_ser_s_clk_cfg, (div << 4) | 1); + + /* GPIO Configuration */ + gpio_configure(qup[idx].pin[2], qup[idx].func[2], GPIO_PULL_UP, + GPIO_2MA, GPIO_OUTPUT); + gpio_configure(qup[idx].pin[3], qup[idx].func[3], GPIO_PULL_UP, + GPIO_2MA, GPIO_INPUT); + + write32(&regs->geni_tx_watermark_reg, UART_TX_WATERMARK_MARGIN); + write32(&regs->geni_rx_watermark_reg, FIFO_DEPTH + - UART_RX_WATERMARK_MARGIN); + write32(&regs->geni_rx_rfr_watermark_reg, + FIFO_DEPTH - UART_RX_RFR_WATERMARK_MARGIN); + + write32(&regs->uart_tx_word_len, UART_TX_BITS_PER_WORD); + write32(&regs->uart_rx_word_len, UART_RX_BITS_PER_WORD); + + /* Disable TX parity calculation */ + write32(&regs->uart_tx_parity_cfg, 0x0); + /* Ignore CTS line status for TX communication */ + write32(&regs->uart_tx_trans_cfg_reg, 0x2); + /* Disable RX parity calculation */ + write32(&regs->uart_rx_parity_cfg, 0x0); + /* Disable parity, framing and break check on received word */ + write32(&regs->uart_rx_trans_cfg, 0x0); + /* Set UART TX stop bit len to one UART bit length */ + write32(&regs->uart_tx_stop_bit_len, 0x0); + write32(&regs->uart_rx_stale_cnt, 0x16 * 10); + + write32(&regs->geni_tx_packing_cfg0, UART_TX_PACK_VECTOR0 | + (UART_TX_PACK_VECTOR1 << 10)); + write32(&regs->geni_tx_packing_cfg1, UART_TX_PACK_VECTOR2 | + (UART_TX_PACK_VECTOR3 << 10)); + write32(&regs->geni_rx_packing_cfg0, UART_RX_PACK_VECTOR0); + write32(&regs->geni_rx_packing_cfg1, UART_RX_PACK_VECTOR2); + + /* Start RX */ + write32(&regs->geni_s_cmd0, START_UART_RX); +} + +unsigned char uart_rx_byte(unsigned int idx) +{ + struct qup_regs *regs = qup[idx].regs; + + if (read32(&regs->geni_rx_fifo_status) & RX_FIFO_WC_MSK) + return read32(&regs->geni_rx_fifon) & 0xFF; + return 0; +} + +void uart_tx_byte(unsigned int idx, unsigned char data) +{ + struct qup_regs *regs = qup[idx].regs; + + uart_tx_flush(idx); + + write32(&regs->uart_tx_trans_len, 1); + /* Start TX */ + write32(&regs->geni_m_cmd0, START_UART_TX); + write32(&regs->geni_tx_fifon, data); +} + +uintptr_t uart_platform_base(unsigned int idx) +{ + return (uintptr_t)qup[idx].regs; +} + +void uart_fill_lb(void *data) +{ + struct lb_serial serial = {0}; + + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = get_uart_baudrate(); + serial.regwidth = 4; + serial.input_hertz = SRC_XO_HZ; + + lb_add_serial(&serial, data); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc91f05c530ae41f212d6a4124dd5796aeaa8dfc Gerrit-Change-Number: 47526 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: sc7280: Add QUPv3 FW load & config
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47525 ) Change subject: sc7280: Add QUPv3 FW load & config ...................................................................... sc7280: Add QUPv3 FW load & config UART driver requires firmware loading Change-Id: I7975ac24d2aa9857e9893d41cc5a2d683deb035b Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/bootblock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h A src/soc/qualcomm/sc7280/include/soc/qupv3_config.h A src/soc/qualcomm/sc7280/qcom_qup_se.c A src/soc/qualcomm/sc7280/qupv3_config.c 7 files changed, 1,024 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/47525/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index f6bc207..876d7d9 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -10,6 +10,8 @@ bootblock-y += clock.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-y += qupv3_config.c +bootblock-y += qcom_qup_se.c ################################################################################ verstage-y += timer.c @@ -18,6 +20,8 @@ verstage-y += clock.c verstage-y += gpio.c verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +verstage-y += qupv3_config.c +verstage-y += qcom_qup_se.c ################################################################################ romstage-y += cbmem.c @@ -31,6 +35,8 @@ romstage-y += clock.c romstage-y += gpio.c romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +romstage-y += qupv3_config.c +romstage-y += qcom_qup_se.c ################################################################################ ramstage-y += soc.c @@ -41,6 +47,8 @@ ramstage-y += clock.c ramstage-y += gpio.c ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +ramstage-y += qupv3_config.c +ramstage-y += qcom_qup_se.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index d0934c0..24f6262 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -4,10 +4,12 @@ #include <soc/clock.h> #include <soc/mmu.h> #include <soc/qspi.h> +#include <soc/qupv3_config.h> void bootblock_soc_init(void) { clock_init(); sc7280_mmu_init(); - quadspi_init(37500 * KHz); + quadspi_init(25 * MHz); + qupv3_fw_init(); } diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index d2e50f2..867b5cc 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -10,4 +10,29 @@ #define QSPI_BASE 0x088DC000 #define TLMM_TILE_BASE 0x0F100000 +/* + * QUP SERIAL ENGINE BASE ADDRESSES + */ +/* QUPV3_0 */ +#define QUP_SERIAL0_BASE 0x00980000 +#define QUP_SERIAL1_BASE 0x00984000 +#define QUP_SERIAL2_BASE 0x00988000 +#define QUP_SERIAL3_BASE 0x0098C000 +#define QUP_SERIAL4_BASE 0x00990000 +#define QUP_SERIAL5_BASE 0x00994000 +#define QUP_SERIAL6_BASE 0x00998000 +#define QUP_SERIAL7_BASE 0x0099C000 +#define QUP_WRAP0_BASE 0x009C0000 + +/* QUPV3_1 */ +#define QUP_SERIAL8_BASE 0x00A80000 +#define QUP_SERIAL9_BASE 0x00A84000 +#define QUP_SERIAL10_BASE 0x00A88000 +#define QUP_SERIAL11_BASE 0x00A8C000 +#define QUP_SERIAL12_BASE 0x00A90000 +#define QUP_SERIAL13_BASE 0x00A94000 +#define QUP_SERIAL14_BASE 0x00A98000 +#define QUP_SERIAL15_BASE 0x00A9C000 +#define QUP_WRAP1_BASE 0x00AC0000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h new file mode 100644 index 0000000..eb70eb3 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_QCOM_QUP_SE_H__ +#define __SOC_QCOM_QUP_SE_H__ + +#include <console/console.h> +#include <device/mmio.h> +#include <gpio.h> +#include <soc/addressmap.h> +#include <timer.h> +#include <types.h> + +#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) + +/* GENI_OUTPUT_CTRL fields */ +#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) + +/* GENI_FORCE_DEFAULT_REG fields */ +#define FORCE_DEFAULT BIT(0) + +#define GENI_FW_REVISION_RO_PROTOCOL_MASK 0x0000FF00 +#define GENI_FW_REVISION_RO_PROTOCOL_SHIFT 0x00000008 + +/* GENI_CGC_CTRL fields */ +#define CFG_AHB_CLK_CGC_ON BIT(0) +#define CFG_AHB_WR_ACLK_CGC_ON BIT(1) +#define DATA_AHB_CLK_CGC_ON BIT(2) +#define SCLK_CGC_ON BIT(3) +#define TX_CLK_CGC_ON BIT(4) +#define RX_CLK_CGC_ON BIT(5) +#define EXT_CLK_CGC_ON BIT(6) +#define PROG_RAM_HCLK_OFF BIT(8) +#define PROG_RAM_SCLK_OFF BIT(9) +#define DEFAULT_CGC_EN (CFG_AHB_CLK_CGC_ON | CFG_AHB_WR_ACLK_CGC_ON \ + | DATA_AHB_CLK_CGC_ON | SCLK_CGC_ON \ + | TX_CLK_CGC_ON | RX_CLK_CGC_ON | EXT_CLK_CGC_ON) + +/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ +#define SER_CLK_EN BIT(0) +#define CLK_DIV_SHFT 4 +#define CLK_DIV_MSK (0xFFF << CLK_DIV_SHFT) + +/* FIFO_IF_DISABLE_RO fields */ +#define FIFO_IF_DISABLE BIT(0) + +/* FW_REVISION_RO fields */ +#define FW_REV_PROTOCOL_MSK GENMASK(15, 8) +#define FW_REV_PROTOCOL_SHFT 8 +#define FW_REV_VERSION_SHFT 0 + +/* GENI_CLK_SEL fields */ +#define CLK_SEL_MSK GENMASK(2, 0) + +/* SE_GENI_DMA_MODE_EN */ +#define GENI_DMA_MODE_EN BIT(0) + +/* GENI_M_CMD0 fields */ +#define M_OPCODE_MSK GENMASK(31, 27) +#define M_OPCODE_SHFT 27 +#define M_PARAMS_MSK GENMASK(26, 0) + +/* GENI_M_CMD_CTRL_REG */ +#define M_GENI_CMD_CANCEL BIT(2) +#define M_GENI_CMD_ABORT BIT(1) +#define M_GENI_DISABLE BIT(0) + +/* GENI_S_CMD0 fields */ +#define S_OPCODE_MSK GENMASK(31, 27) +#define S_OPCODE_SHFT 27 +#define S_PARAMS_MSK GENMASK(26, 0) + +/* GENI_S_CMD_CTRL_REG */ +#define S_GENI_CMD_CANCEL BIT(2) +#define S_GENI_CMD_ABORT BIT(1) +#define S_GENI_DISABLE BIT(0) + +/* GENI_M_IRQ_EN fields */ +#define M_CMD_DONE_EN BIT(0) +#define M_CMD_OVERRUN_EN BIT(1) +#define M_ILLEGAL_CMD_EN BIT(2) +#define M_CMD_FAILURE_EN BIT(3) +#define M_CMD_CANCEL_EN BIT(4) +#define M_CMD_ABORT_EN BIT(5) +#define M_TIMESTAMP_EN BIT(6) +#define M_RX_IRQ_EN BIT(7) +#define M_GP_SYNC_IRQ_0_EN BIT(8) +#define M_GP_IRQ_0_EN BIT(9) +#define M_GP_IRQ_1_EN BIT(10) +#define M_GP_IRQ_2_EN BIT(11) +#define M_GP_IRQ_3_EN BIT(12) +#define M_GP_IRQ_4_EN BIT(13) +#define M_GP_IRQ_5_EN BIT(14) +#define M_IO_DATA_DEASSERT_EN BIT(22) +#define M_IO_DATA_ASSERT_EN BIT(23) +#define M_RX_FIFO_RD_ERR_EN BIT(24) +#define M_RX_FIFO_WR_ERR_EN BIT(25) +#define M_RX_FIFO_WATERMARK_EN BIT(26) +#define M_RX_FIFO_LAST_EN BIT(27) +#define M_TX_FIFO_RD_ERR_EN BIT(28) +#define M_TX_FIFO_WR_ERR_EN BIT(29) +#define M_TX_FIFO_WATERMARK_EN BIT(30) +#define M_SEC_IRQ_EN BIT(31) +#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ + M_IO_DATA_DEASSERT_EN | \ + M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ + M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ + M_TX_FIFO_WR_ERR_EN) + +/* GENI_S_IRQ_EN fields */ +#define S_CMD_DONE_EN BIT(0) +#define S_CMD_OVERRUN_EN BIT(1) +#define S_ILLEGAL_CMD_EN BIT(2) +#define S_CMD_FAILURE_EN BIT(3) +#define S_CMD_CANCEL_EN BIT(4) +#define S_CMD_ABORT_EN BIT(5) +#define S_GP_SYNC_IRQ_0_EN BIT(8) +#define S_GP_IRQ_0_EN BIT(9) +#define S_GP_IRQ_1_EN BIT(10) +#define S_GP_IRQ_2_EN BIT(11) +#define S_GP_IRQ_3_EN BIT(12) +#define S_GP_IRQ_4_EN BIT(13) +#define S_GP_IRQ_5_EN BIT(14) +#define S_IO_DATA_DEASSERT_EN BIT(22) +#define S_IO_DATA_ASSERT_EN BIT(23) +#define S_RX_FIFO_RD_ERR_EN BIT(24) +#define S_RX_FIFO_WR_ERR_EN BIT(25) +#define S_RX_FIFO_WATERMARK_EN BIT(26) +#define S_RX_FIFO_LAST_EN BIT(27) +#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ + S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) + +/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ +#define WATERMARK_MSK GENMASK(5, 0) + +/* GENI_TX_FIFO_STATUS fields */ +#define TX_FIFO_WC GENMASK(27, 0) + +/* GENI_RX_FIFO_STATUS fields */ +#define RX_LAST BIT(31) +#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) +#define RX_LAST_BYTE_VALID_SHFT 28 +#define RX_FIFO_WC_MSK GENMASK(24, 0) + +/* SE_IRQ_EN fields */ +#define DMA_RX_IRQ_EN BIT(0) +#define DMA_TX_IRQ_EN BIT(1) +#define GENI_M_IRQ_EN BIT(2) +#define GENI_S_IRQ_EN BIT(3) + +/* SE_DMA_GENERAL_CFG */ +#define DMA_RX_CLK_CGC_ON BIT(0) +#define DMA_TX_CLK_CGC_ON BIT(1) +#define DMA_AHB_SLV_CFG_ON BIT(2) +#define AHB_SEC_SLV_CLK_CGC_ON BIT(3) +#define DUMMY_RX_NON_BUFFERABLE BIT(4) +#define RX_DMA_ZERO_PADDING_EN BIT(5) +#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) +#define RX_DMA_IRQ_DELAY_SHFT 6 + +#define DEFAULT_SE_CLK (19200 * KHz) +#define GENI_DFS_IF_CFG_DFS_IF_EN_BMSK BIT(0) + +/* FIFO BUFFER PARAMETERS */ +#define BYTES_PER_FIFO_WORD 4 +#define FIFO_WIDTH 32 +#define FIFO_DEPTH 16 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +/* PACKING CONFIGURATION VECTOR */ + +/* start_idx:x: Bit position to move + * direction:1: MSB to LSB + * len:7: Represents bits-per-word = 8 + * stop:0: Till it's 1, FIFO bit shift continues + */ + +/* Start_idx:7, direction:1, len:7, stop:0 */ +#define PACK_VECTOR0 0x0FE +/* Start_idx:15, direction:1, len:7, stop:0 */ +#define PACK_VECTOR1 0x1FE +/* Start_idx:23, direction:1, len:7, stop:0 */ +#define PACK_VECTOR2 0x2FE +/* Start_idx:31, direction:1, len:7, stop:1 */ +#define PACK_VECTOR3 0x3FF + +enum qup_se { + QUPV3_0_SE0, + QUPV3_0_SE1, + QUPV3_0_SE2, + QUPV3_0_SE3, + QUPV3_0_SE4, + QUPV3_0_SE5, + QUPV3_1_SE0, + QUPV3_1_SE1, + QUPV3_1_SE2, + QUPV3_1_SE3, + QUPV3_1_SE4, + QUPV3_1_SE5, + QUPV3_SE_MAX, +}; + +enum se_protocol { + SE_PROTOCOL_SPI = 1, + SE_PROTOCOL_UART = 2, + SE_PROTOCOL_I2C = 3, + SE_PROTOCOL_I3C = 4, + SE_PROTOCOL_MAX = 5 +}; + +enum se_mode { + NONE, + GSI, + FIFO, + CPU_DMA, + MIXED +}; + +struct qup_regs { + u32 geni_init_cfg_revision; + u32 geni_s_init_cfg_revision; + u8 _reserved1[0x10 - 0x08]; + u32 geni_general_cfg; + u32 geni_rx_fifo_ctrl; + u8 _reserved2[0x20 - 0x18]; + u32 geni_force_default_reg; + u32 geni_output_ctrl; + u32 geni_cgc_ctrl; + u32 geni_char_cfg; + u32 geni_char_data_n; + u8 _reserved3[0x40 - 0x34]; + u32 geni_status; + u32 geni_test_bus_ctrl; + u32 geni_ser_m_clk_cfg; + u32 geni_ser_s_clk_cfg; + u32 geni_prog_rom_ctrl_reg; + u8 _reserved4[0x60 - 0x54]; + u32 geni_clk_ctrl_ro; + u32 fifo_if_disable_ro; + u32 geni_fw_revision_ro; + u32 geni_s_fw_revision_ro; + u32 geni_fw_multilock_protns_ro; + u32 geni_fw_multilock_msa_ro; + u32 geni_fw_multilock_sp_ro; + u32 geni_clk_sel; + u32 geni_dfs_if_cfg; + u8 _reserved5[0x100 - 0x084]; + u32 geni_cfg_reg0; + u32 geni_cfg_reg1; + u32 geni_cfg_reg2; + u32 geni_cfg_reg3; + u32 geni_cfg_reg4; + u32 geni_cfg_reg5; + u32 geni_cfg_reg6; + u32 geni_cfg_reg7; + u32 geni_cfg_reg8; + u32 geni_cfg_reg9; + u32 geni_cfg_reg10; + u32 geni_cfg_reg11; + u32 geni_cfg_reg12; + u32 geni_cfg_reg13; + u32 geni_cfg_reg14; + u32 geni_cfg_reg15; + u32 geni_cfg_reg16; + u32 geni_cfg_reg17; + u32 geni_cfg_reg18; + u8 _reserved6[0x200 - 0x14C]; + u32 geni_cfg_reg64; + u32 geni_cfg_reg65; + u32 geni_cfg_reg66; + u32 geni_cfg_reg67; + u32 geni_cfg_reg68; + u32 geni_cfg_reg69; + u32 geni_cfg_reg70; + u32 geni_cfg_reg71; + u32 geni_cfg_reg72; + u32 spi_cpha; + u32 geni_cfg_reg74; + u32 proto_loopback_cfg; + u32 spi_cpol; + u32 i2c_noise_cancellation_ctl; + u32 i2c_monitor_ctl; + u32 geni_cfg_reg79; + u32 geni_cfg_reg80; + u32 geni_cfg_reg81; + u32 geni_cfg_reg82; + u32 spi_demux_output_inv; + u32 spi_demux_sel; + u32 geni_byte_granularity; + u32 geni_dma_mode_en; + u32 uart_tx_trans_cfg_reg; + u32 geni_tx_packing_cfg0; + u32 geni_tx_packing_cfg1; + union { + u32 uart_tx_word_len; + u32 spi_word_len; + }; + union { + u32 uart_tx_stop_bit_len; + u32 i2c_tx_trans_len; + u32 spi_tx_trans_len; + }; + union { + u32 uart_tx_trans_len; + u32 i2c_rx_trans_len; + u32 spi_rx_trans_len; + }; + u32 spi_pre_post_cmd_dly; + u32 i2c_scl_counters; + u32 geni_cfg_reg95; + u32 uart_rx_trans_cfg; + u32 geni_rx_packing_cfg0; + u32 geni_rx_packing_cfg1; + u32 uart_rx_word_len; + u32 geni_cfg_reg100; + u32 uart_rx_stale_cnt; + u32 geni_cfg_reg102; + u32 geni_cfg_reg103; + u32 geni_cfg_reg104; + u32 uart_tx_parity_cfg; + u32 uart_rx_parity_cfg; + u32 uart_manual_rfr; + u32 geni_cfg_reg108; + u32 geni_cfg_reg109; + u32 geni_cfg_reg110; + u8 _reserved7[0x600 - 0x2BC]; + u32 geni_m_cmd0; + u32 geni_m_cmd_ctrl_reg; + u8 _reserved8[0x10 - 0x08]; + u32 geni_m_irq_status; + u32 geni_m_irq_enable; + u32 geni_m_irq_clear; + u32 geni_m_irq_en_set; + u32 geni_m_irq_en_clear; + u32 geni_m_cmd_err_status; + u32 geni_m_fw_err_status; + u8 _reserved9[0x30 - 0x2C]; + u32 geni_s_cmd0; + u32 geni_s_cmd_ctrl_reg; + u8 _reserved10[0x40 - 0x38]; + u32 geni_s_irq_status; + u32 geni_s_irq_enable; + u32 geni_s_irq_clear; + u32 geni_s_irq_en_set; + u32 geni_s_irq_en_clear; + u8 _reserved11[0x700 - 0x654]; + u32 geni_tx_fifon; + u8 _reserved12[0x780 - 0x704]; + u32 geni_rx_fifon; + u8 _reserved13[0x800 - 0x784]; + u32 geni_tx_fifo_status; + u32 geni_rx_fifo_status; + u32 geni_tx_fifo_threshold; + u32 geni_tx_watermark_reg; + u32 geni_rx_watermark_reg; + u32 geni_rx_rfr_watermark_reg; + u8 _reserved14[0x900 - 0x818]; + u32 geni_gp_output_reg; + u8 _reserved15[0x908 - 0x904]; + u32 geni_ios; + u32 geni_timestamp; + u32 geni_m_gp_length; + u32 geni_s_gp_length; + u8 _reserved16[0x920 - 0x918]; + u32 geni_hw_irq_en; + u32 geni_hw_irq_ignore_on_active; + u8 _reserved17[0x930 - 0x928]; + u32 geni_hw_irq_cmd_param_0; + u8 _reserved18[0xA00 - 0x934]; + u32 geni_i3c_ibi_cfg_tablen; + u8 _reserved19[0xA80 - 0xA04]; + u32 geni_i3c_ibi_status; + u32 geni_i3c_ibi_rd_data; + u32 geni_i3c_ibi_search_pattern; + u32 geni_i3c_ibi_search_data; + u32 geni_i3c_sw_ibi_en; + u32 geni_i3c_sw_ibi_en_recover; + u8 _reserved20[0xC30 - 0xA98]; + u32 dma_tx_ptr_l; + u32 dma_tx_ptr_h; + u32 dma_tx_attr; + u32 dma_tx_length; + u32 dma_tx_irq_stat; + u32 dma_tx_irq_clr; + u32 dma_tx_irq_en; + u32 dma_tx_irq_en_set; + u32 dma_tx_irq_en_clr; + u32 dma_tx_length_in; + u32 dma_tx_fsm_rst; + u32 dma_tx_max_burst_size; + u8 _reserved21[0xD30 - 0xC60]; + u32 dma_rx_ptr_l; + u32 dma_rx_ptr_h; + u32 dma_rx_attr; + u32 dma_rx_length; + u32 dma_rx_irq_stat; + u32 dma_rx_irq_clr; + u32 dma_rx_irq_en; + u32 dma_rx_irq_en_set; + u32 dma_rx_irq_en_clr; + u32 dma_rx_length_in; + u32 dma_rx_fsm_rst; + u32 dma_rx_max_burst_size; + u32 dma_rx_flush; + u8 _reserved22[0xE14 - 0xD64]; + u32 se_irq_high_priority; + u32 se_gsi_event_en; + u32 se_irq_en; + u32 dma_if_en_ro; + u32 se_hw_param_0; + u32 se_hw_param_1; + u32 se_hw_param_2; + u32 dma_general_cfg; + u8 _reserved23[0x40 - 0x34]; + u32 dma_debug_reg0; + u32 dma_test_bus_ctrl; + u32 se_top_test_bus_ctrl; + u8 _reserved24[0x1000 - 0x0E4C]; + u32 se_geni_fw_revision; + u32 se_s_fw_revision; + u8 _reserved25[0x10-0x08]; + u32 se_geni_cfg_ramn; + u8 _reserved26[0x2000 - 0x1014]; + u32 se_geni_clk_ctrl; + u32 se_dma_if_en; + u32 se_fifo_if_disable; + u32 se_geni_fw_multilock_protns; + u32 se_geni_fw_multilock_msa; + u32 se_geni_fw_multilock_sp; +}; +check_member(qup_regs, geni_clk_sel, 0x7C); +check_member(qup_regs, geni_cfg_reg108, 0x2B0); +check_member(qup_regs, geni_dma_mode_en, 0x258); +check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84); +check_member(qup_regs, dma_test_bus_ctrl, 0xE44); +check_member(qup_regs, se_geni_cfg_ramn, 0x1010); +check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014); + +struct qup { + struct qup_regs *regs; + gpio_t pin[4]; + u8 func[4]; +}; + +extern struct qup qup[16]; + +u32 qup_wait_for_m_irq(unsigned int bus); +u32 qup_wait_for_s_irq(unsigned int bus); +void qup_m_cancel_and_abort(unsigned int bus); +void qup_s_cancel_and_abort(unsigned int bus); +int qup_handle_transfer(unsigned int bus, const void *dout, void *din, + int size); + +#endif /* __SOC_QCOM_QUP_SE_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/qupv3_config.h b/src/soc/qualcomm/sc7280/include/soc/qupv3_config.h new file mode 100644 index 0000000..9c8b2f6 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qupv3_config.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SC7280_QUPV3_CONFIG_H_ +#define _SC7280_QUPV3_CONFIG_H_ + +#include <assert.h> +#include <soc/clock.h> +#include <soc/qcom_qup_se.h> + +#define QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK 0x00000001 +#define QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK 0x00000001 + +#define GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK 0x00000200 +#define GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK 0x00000100 + +#define GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK 0x00000001 + +#define DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008 +#define DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004 +#define DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001 + +#define DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK 0x00000010 +#define DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008 +#define DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004 +#define DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001 + +#define DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK 0x00000008 +#define DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK 0x00000004 +#define DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK 0x00000002 +#define DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK 0x00000001 + +#define GENI_CLK_CTRL_SER_CLK_SEL_BMSK 0x00000001 +#define DMA_IF_EN_DMA_IF_EN_BMSK 0x00000001 +#define SE_GSI_EVENT_EN_BMSK 0x0000000f +#define SE_IRQ_EN_RMSK 0x0000000f + +#define SIZE_GENI_FW_RAM 0x00000200 +#define MAX_OFFSET_CFG_REG 0x000001c4 +#define SEFW_MAGIC_HEADER 0x57464553 + +struct elf_se_hdr { + uint32_t magic; /* = 'SEFW' */ + uint32_t version; /* Structure version number */ + uint32_t core_version; /* QUPV3_HW_VERSION */ + uint16_t serial_protocol; /* Programmed into GENI_FW_REVISION */ + uint16_t fw_version; /* Programmed into GENI_FW_REVISION */ + uint16_t cfg_version; /* Programmed into GENI_INIT_CFG_REVISION */ + uint16_t fw_size_in_items; /* Number of (uint32_t) GENI_FW_RAM words */ + uint16_t fw_offset; /* Byte offset of GENI_FW_RAM array */ + uint16_t cfg_size_in_items;/* Number of GENI_FW_CFG index/value pairs */ + uint16_t cfg_idx_offset; /* Byte offset of GENI_FW_CFG index array */ + uint16_t cfg_val_offset; /* Byte offset of GENI_FW_CFG values array */ +}; + +struct qupv3_common_reg { + u8 reserved_1[0x118]; + u32 qupv3_se_ahb_m_cfg_reg; + u8 reserved_2[0x4]; + u32 qupv3_common_cfg_reg; +}; + +void qupv3_fw_init(void); +void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, + unsigned int mode); + +#endif /* _SC7280_QUPV3_CONFIG_H_ */ diff --git a/src/soc/qualcomm/sc7280/qcom_qup_se.c b/src/soc/qualcomm/sc7280/qcom_qup_se.c new file mode 100644 index 0000000..60e1fee --- /dev/null +++ b/src/soc/qualcomm/sc7280/qcom_qup_se.c @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/qcom_qup_se.h> + +struct qup qup[16] = { + [0] = { .regs = (void *)QUP_SERIAL0_BASE, + .pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3) }, + .func = { GPIO0_FUNC_QUP0_L0, GPIO1_FUNC_QUP0_L1, + GPIO2_FUNC_QUP0_L2, GPIO3_FUNC_QUP0_L3 } + }, + [1] = { .regs = (void *)QUP_SERIAL1_BASE, + .pin = { GPIO(4), GPIO(5), GPIO(6), GPIO(7) }, + .func = { GPIO4_FUNC_QUP0_L0, GPIO5_FUNC_QUP0_L1, + GPIO6_FUNC_QUP0_L2, GPIO7_FUNC_QUP0_L3 } + }, + [2] = { .regs = (void *)QUP_SERIAL2_BASE, + .pin = { GPIO(8), GPIO(9), GPIO(10), GPIO(11) }, + .func = { GPIO8_FUNC_QUP0_L0, GPIO9_FUNC_QUP0_L1, + GPIO10_FUNC_QUP0_L2, GPIO11_FUNC_QUP0_L3 } + }, + [3] = { .regs = (void *)QUP_SERIAL3_BASE, + .pin = { GPIO(12), GPIO(13), GPIO(14), GPIO(15) }, + .func = { GPIO12_FUNC_QUP0_L0, GPIO13_FUNC_QUP0_L1, + GPIO14_FUNC_QUP0_L2, GPIO15_FUNC_QUP0_L3 } + }, + [4] = { .regs = (void *)QUP_SERIAL4_BASE, + .pin = { GPIO(16), GPIO(17), GPIO(18), GPIO(19) }, + .func = { GPIO16_FUNC_QUP0_L0, GPIO17_FUNC_QUP0_L1, + GPIO18_FUNC_QUP0_L2, GPIO19_FUNC_QUP0_L3 } + }, + [5] = { .regs = (void *)QUP_SERIAL5_BASE, + .pin = { GPIO(20), GPIO(21), GPIO(22), GPIO(23) }, + .func = { GPIO20_FUNC_QUP0_L0, GPIO21_FUNC_QUP0_L1, + GPIO22_FUNC_QUP0_L2, GPIO23_FUNC_QUP0_L3 } + }, + [6] = { .regs = (void *)QUP_SERIAL6_BASE, + .pin = { GPIO(24), GPIO(25), GPIO(26), GPIO(27) }, + .func = { GPIO24_FUNC_QUP0_L0, GPIO25_FUNC_QUP0_L1, + GPIO26_FUNC_QUP0_L2, GPIO27_FUNC_QUP0_L3 } + }, + [7] = { .regs = (void *)QUP_SERIAL7_BASE, + .pin = { GPIO(28), GPIO(29), GPIO(30), GPIO(31) }, + .func = { GPIO28_FUNC_QUP0_L0, GPIO29_FUNC_QUP0_L1, + GPIO30_FUNC_QUP0_L2, GPIO31_FUNC_QUP0_L3 } + }, + [8] = { .regs = (void *)QUP_SERIAL8_BASE, + .pin = { GPIO(32), GPIO(33), GPIO(34), GPIO(35) }, + .func = { GPIO32_FUNC_QUP1_L0, GPIO33_FUNC_QUP1_L1, + GPIO34_FUNC_QUP1_L2, GPIO35_FUNC_QUP1_L3 } + }, + [9] = { .regs = (void *)QUP_SERIAL9_BASE, + .pin = { GPIO(36), GPIO(37), GPIO(38), GPIO(39) }, + .func = { GPIO36_FUNC_QUP1_L0, GPIO37_FUNC_QUP1_L1, + GPIO38_FUNC_QUP1_L2, GPIO39_FUNC_QUP1_L3 } + }, + [10] = { .regs = (void *)QUP_SERIAL10_BASE, + .pin = { GPIO(40), GPIO(41), GPIO(42), GPIO(43) }, + .func = { GPIO40_FUNC_QUP1_L0, GPIO41_FUNC_QUP1_L1, + GPIO42_FUNC_QUP1_L2, GPIO43_FUNC_QUP1_L3 } + }, + [11] = { .regs = (void *)QUP_SERIAL11_BASE, + .pin = { GPIO(44), GPIO(45), GPIO(46), GPIO(47) }, + .func = { GPIO44_FUNC_QUP1_L0, GPIO45_FUNC_QUP1_L1, + GPIO46_FUNC_QUP1_L2, GPIO47_FUNC_QUP1_L3 } + }, + [12] = { .regs = (void *)QUP_SERIAL12_BASE, + .pin = { GPIO(48), GPIO(49), GPIO(50), GPIO(51) }, + .func = { GPIO48_FUNC_QUP1_L0, GPIO49_FUNC_QUP1_L1, + GPIO50_FUNC_QUP1_L2, GPIO51_FUNC_QUP1_L3 } + }, + [13] = { .regs = (void *)QUP_SERIAL13_BASE, + .pin = { GPIO(52), GPIO(53), GPIO(54), GPIO(55) }, + .func = { GPIO52_FUNC_QUP1_L0, GPIO53_FUNC_QUP1_L1, + GPIO54_FUNC_QUP1_L2, GPIO55_FUNC_QUP1_L3 } + }, + [14] = { .regs = (void *)QUP_SERIAL14_BASE, + .pin = { GPIO(56), GPIO(57), GPIO(58), GPIO(59) }, + .func = { GPIO56_FUNC_QUP1_L0, GPIO57_FUNC_QUP1_L1, + GPIO58_FUNC_QUP1_L2, GPIO59_FUNC_QUP1_L3 } + }, + [15] = { .regs = (void *)QUP_SERIAL15_BASE, + .pin = { GPIO(60), GPIO(61), GPIO(62), GPIO(63) }, + .func = { GPIO60_FUNC_QUP1_L0, GPIO61_FUNC_QUP1_L1, + GPIO62_FUNC_QUP1_L2, GPIO63_FUNC_QUP1_L3 } + }, +}; + +u32 qup_wait_for_m_irq(unsigned int bus) +{ + struct stopwatch sw; + unsigned int m_irq = 0; + struct qup_regs *regs = qup[bus].regs; + + stopwatch_init_usecs_expire(&sw, 25); + while (!stopwatch_expired(&sw)) { + m_irq = read32(&regs->geni_m_irq_status); + if (m_irq) + break; + } + return m_irq; +} + +u32 qup_wait_for_s_irq(unsigned int bus) +{ + struct stopwatch sw; + unsigned int s_irq = 0; + struct qup_regs *regs = qup[bus].regs; + + stopwatch_init_usecs_expire(&sw, 25); + while (!stopwatch_expired(&sw)) { + s_irq = read32(&regs->geni_s_irq_status); + if (s_irq) + break; + } + return s_irq; +} + +static int handle_tx(unsigned int bus, const u8 *dout, + unsigned int tx_rem_bytes) +{ + int max_bytes = 0; + struct qup_regs *regs = qup[bus].regs; + + max_bytes = (FIFO_DEPTH - TX_WATERMARK) * BYTES_PER_FIFO_WORD; + max_bytes = MIN(tx_rem_bytes, max_bytes); + + buffer_to_fifo32((void *)dout, max_bytes, &regs->geni_tx_fifon, + 0, BYTES_PER_FIFO_WORD); + + if (tx_rem_bytes == max_bytes) + write32(&regs->geni_tx_watermark_reg, 0); + return max_bytes; +} + +static int handle_rx(unsigned int bus, u8 *din, unsigned int rx_rem_bytes) +{ + struct qup_regs *regs = qup[bus].regs; + u32 rx_fifo_status = read32(&regs->geni_rx_fifo_status); + int rx_bytes = 0; + + rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * BYTES_PER_FIFO_WORD; + rx_bytes = MIN(rx_rem_bytes, rx_bytes); + + buffer_from_fifo32(din, rx_bytes, &regs->geni_rx_fifon, + 0, BYTES_PER_FIFO_WORD); + return rx_bytes; +} + +void qup_m_cancel_and_abort(unsigned int bus) +{ + struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int m_irq; + + write32(&regs->geni_tx_watermark_reg, 0); + write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL); + + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_m_irq(bus); + if (m_irq & M_CMD_CANCEL_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_CANCEL_EN)) { + printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n", + __func__); + + write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_m_irq(bus); + if (m_irq & M_CMD_ABORT_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_ABORT_EN)) + printk(BIOS_INFO, "%s:Abort failed\n", __func__); + } +} + +void qup_s_cancel_and_abort(unsigned int bus) +{ + struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int s_irq; + u32 rx_fifo_status; + u8 buf[64]; /* FIFO size */ + + write32(&regs->geni_tx_watermark_reg, 0); + write32(&regs->geni_s_cmd_ctrl_reg, S_GENI_CMD_CANCEL); + + stopwatch_init_msecs_expire(&sw, 100); + do { + s_irq = qup_wait_for_s_irq(bus); + rx_fifo_status = read32(&regs->geni_rx_fifo_status); + if (rx_fifo_status & RX_LAST) + handle_rx(bus, buf, 64); /* Read whatever data available in FIFO */ + if (s_irq & S_CMD_CANCEL_EN) { + write32(&regs->geni_s_irq_clear, s_irq); + break; + } + write32(&regs->geni_s_irq_clear, s_irq); + } while (!stopwatch_expired(&sw)); + + if (!(s_irq & S_CMD_CANCEL_EN)) { + printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n", + __func__); + + write32(&regs->geni_s_cmd_ctrl_reg, S_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + s_irq = qup_wait_for_s_irq(bus); + if (s_irq & S_CMD_ABORT_EN) { + write32(&regs->geni_s_irq_clear, s_irq); + break; + } + write32(&regs->geni_s_irq_clear, s_irq); + } while (!stopwatch_expired(&sw)); + + if (!(s_irq & S_CMD_ABORT_EN)) + printk(BIOS_INFO, "%s:Abort failed\n", __func__); + } +} + +int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size) +{ + unsigned int m_irq; + struct stopwatch sw; + unsigned int rx_rem_bytes = din ? size : 0; + unsigned int tx_rem_bytes = dout ? size : 0; + struct qup_regs *regs = qup[bus].regs; + + stopwatch_init_msecs_expire(&sw, 1000); + do { + m_irq = qup_wait_for_m_irq(bus); + if ((m_irq & M_RX_FIFO_WATERMARK_EN) || + (m_irq & M_RX_FIFO_LAST_EN)) + rx_rem_bytes -= handle_rx(bus, din + size + - rx_rem_bytes, rx_rem_bytes); + if (m_irq & M_TX_FIFO_WATERMARK_EN) + tx_rem_bytes -= handle_tx(bus, dout + size + - tx_rem_bytes, tx_rem_bytes); + if (m_irq & M_CMD_DONE_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) { + printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__); + qup_m_cancel_and_abort(bus); + return -1; + } + return 0; +} diff --git a/src/soc/qualcomm/sc7280/qupv3_config.c b/src/soc/qualcomm/sc7280/qupv3_config.c new file mode 100644 index 0000000..3dbe3e6 --- /dev/null +++ b/src/soc/qualcomm/sc7280/qupv3_config.c @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <string.h> +#include <soc/qupv3_config.h> + +static struct elf_se_hdr *fw_list[SE_PROTOCOL_MAX]; + +void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, + unsigned int mode) +{ + uint32_t i; + uint32_t reg_value; + const uint8_t *cfg_idx_arr; + const uint32_t *cfg_val_arr; + const uint32_t *fw_val_arr; + struct elf_se_hdr *hdr; + struct qup_regs *regs = qup[bus].regs; + static const char * const filename[] = { + [SE_PROTOCOL_SPI] = "fallback/spi_fw", + [SE_PROTOCOL_UART] = "fallback/uart_fw", + [SE_PROTOCOL_I2C] = "fallback/i2c_fw", + }; + + if (protocol >= SE_PROTOCOL_MAX || !filename[protocol]) + die("*ERROR* * INVALID PROTOCOL ***\n"); + + if (!fw_list[protocol]) { + fw_list[protocol] = cbfs_boot_map_with_leak(filename[protocol], + CBFS_TYPE_RAW, NULL); + if (!fw_list[protocol]) + die("*ERROR* * cbfs_boot_map_with_leak failed ***\n"); + } + + hdr = fw_list[protocol]; + assert(hdr->magic == SEFW_MAGIC_HEADER) + + cfg_idx_arr = (const uint8_t *)hdr + hdr->cfg_idx_offset; + cfg_val_arr = (const uint32_t *)((uint8_t *)hdr + hdr->cfg_val_offset); + fw_val_arr = (const uint32_t *)((uint8_t *)hdr + hdr->fw_offset); + + /* Unlock SE for FW loading */ + write32(&regs->se_geni_fw_multilock_protns, 0x0); + write32(&regs->se_geni_fw_multilock_msa, 0x0); + + /* First, ensure GENI FW is disabled */ + write32(&regs->geni_output_ctrl, 0x0); + clrbits_le32(&regs->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + setbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK + | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); + write32(&regs->se_geni_clk_ctrl, 0x0); + clrbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK + | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); + + + /* HPG section 3.1.7.1 */ + if (protocol != SE_PROTOCOL_UART) { + setbits_le32(&regs->geni_dfs_if_cfg, + GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + /* configure clock dfsr */ + clock_configure_dfsr(bus); + } + + /* HPG section 3.1.7.2 */ + /* No Init Required */ + + /* HPG section 3.1.7.3 */ + write32(&regs->dma_general_cfg, + DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK | + DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK | + DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK | + DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK); + write32(&regs->geni_cgc_ctrl, DEFAULT_CGC_EN); + + /* HPG section 3.1.7.4 */ + write32(&regs->geni_init_cfg_revision, hdr->cfg_version); + write32(&regs->geni_s_init_cfg_revision, hdr->cfg_version); + + assert(cfg_idx_arr[hdr->cfg_size_in_items - 1] * sizeof(uint32_t) <= + MAX_OFFSET_CFG_REG); + + for (i = 0; i < hdr->cfg_size_in_items; i++) { + write32(&regs->geni_cfg_reg0 + cfg_idx_arr[i], + cfg_val_arr[i]); + } + + /* HPG section 3.1.7.9 */ + /* non-UART configuration, UART driver can configure as desired for UART + */ + write32(&regs->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* HPG section 3.1.7.5 */ + /* Don't change any SPI polarity, client driver will handle this */ + setbits_le32(&regs->geni_output_ctrl, DEFAULT_IO_OUTPUT_CTRL_MSK); + + /* HPG section 3.1.7.6 */ + reg_value = read32(&regs->geni_dma_mode_en); + if (mode == GSI) { + reg_value |= GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK; + write32(&regs->geni_dma_mode_en, reg_value); + write32(&regs->se_irq_en, 0x0); + write32(&regs->se_gsi_event_en, SE_GSI_EVENT_EN_BMSK); + } else if (mode == FIFO) { + reg_value &= ~GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK; + write32(&regs->geni_dma_mode_en, reg_value); + write32(&regs->se_irq_en, SE_IRQ_EN_RMSK); + write32(&regs->se_gsi_event_en, 0x0); + } else if (mode == CPU_DMA) { + reg_value |= GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK; + write32(&regs->geni_dma_mode_en, reg_value); + write32(&regs->se_irq_en, SE_IRQ_EN_RMSK); + write32(&regs->se_gsi_event_en, 0x0); + } + + /* HPG section 3.1.7.7 */ + write32(&regs->geni_m_irq_enable, + M_COMMON_GENI_M_IRQ_EN); + reg_value = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | + S_CMD_CANCEL_EN | S_CMD_ABORT_EN | + S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | + S_GP_IRQ_2_EN | S_GP_IRQ_3_EN | + S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN; + write32(&regs->geni_s_irq_enable, reg_value); + + /* HPG section 3.1.7.8 */ + /* GPI/DMA mode */ + reg_value = DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK | + DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK | + DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK; + write32(&regs->dma_tx_irq_en_set, reg_value); + + reg_value = DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK | + DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK | + DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK | + DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK; + write32(&regs->dma_rx_irq_en_set, reg_value); + + /* HPG section 3.1.7.10 */ + reg_value = (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) | + (hdr->fw_version & 0xFF << + FW_REV_VERSION_SHFT); + write32(&regs->se_geni_fw_revision, reg_value); + + reg_value = + (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) | + (hdr->fw_version & 0xFF << + FW_REV_VERSION_SHFT); + write32(&regs->se_s_fw_revision, reg_value); + + assert(hdr->fw_size_in_items <= SIZE_GENI_FW_RAM); + + memcpy((&regs->se_geni_cfg_ramn), fw_val_arr, + hdr->fw_size_in_items * sizeof(uint32_t)); + + /* HPG section 3.1.7.12 */ + write32(&regs->geni_force_default_reg, 0x1); + setbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK + |GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK); + setbits_le32(&regs->se_geni_clk_ctrl, GENI_CLK_CTRL_SER_CLK_SEL_BMSK); + clrbits_le32(&regs->geni_cgc_ctrl, + (GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK | + GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK)); + + /* HPG section 3.1.7.13 */ + /* GSI/DMA mode */ + setbits_le32(&regs->se_dma_if_en, DMA_IF_EN_DMA_IF_EN_BMSK); + + /* HPG section 3.1.7.14 */ + reg_value = read32(&regs->se_fifo_if_disable); + if ((mode == MIXED) || (mode == FIFO)) + reg_value &= ~FIFO_IF_DISABLE; + else + reg_value |= FIFO_IF_DISABLE; + write32(&regs->se_fifo_if_disable, reg_value); + write32(&regs->se_geni_clk_ctrl, 0x1); + + /* Lock SE from FW loading */ + write32(&regs->se_geni_fw_multilock_protns, 0x1); + write32(&regs->se_geni_fw_multilock_msa, 0x1); +} + +static void qup_common_init(int addr) +{ + struct qupv3_common_reg *qupv3_common; + /* HPG section 3.1.2 */ + qupv3_common = (struct qupv3_common_reg *)(uintptr_t) addr; + setbits32(&qupv3_common->qupv3_common_cfg_reg, + QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK); + + /* HPG section 3.1.7.3 */ + setbits32(&qupv3_common->qupv3_se_ahb_m_cfg_reg, + QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK); +} + +void qupv3_fw_init(void) +{ + uint8_t i; + + /* Turn on all QUP clocks */ + for (i = 0; i < QUPV3_SE_MAX; i++) + clock_enable_qup(i); + + qup_common_init(QUP_WRAP0_BASE); + qup_common_init(QUP_WRAP1_BASE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7975ac24d2aa9857e9893d41cc5a2d683deb035b Gerrit-Change-Number: 47525 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: sc7280: Add SPI-NOR support
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47075 ) Change subject: sc7280: Add SPI-NOR support ...................................................................... sc7280: Add SPI-NOR support This implements the SPI-NOR driver for the Qualcomm QSPI core. Change-Id: I4d4159939a57648c54dcb06aea3645f1dfe10903 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/include/soc/qspi.h A src/soc/qualcomm/sc7280/qspi.c M src/soc/qualcomm/sc7280/spi.c 6 files changed, 428 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/47075/1 diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index fc2f34b..c47ed29 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -24,4 +24,13 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK +config SC7280_QSPI + bool + default y if COMMON_CBFS_SPI_WRAPPER + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 16 + endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index d6f8d29..33f6def 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -6,10 +6,12 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ romstage-y += cbmem.c @@ -19,12 +21,14 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c +romstage-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ ramstage-y += soc.c ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 807bb25..9e04351 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -2,8 +2,10 @@ #include <bootblock_common.h> #include <soc/mmu.h> +#include <soc/qspi.h> void bootblock_soc_init(void) { sc7280_mmu_init(); + quadspi_init(37500 * KHz); } diff --git a/src/soc/qualcomm/sc7280/include/soc/qspi.h b/src/soc/qualcomm/sc7280/include/soc/qspi.h new file mode 100644 index 0000000..6c40e7e --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qspi.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> +#include <soc/addressmap.h> +#include <spi-generic.h> + +#ifndef __SOC_QUALCOMM_SC7280_QSPI_H__ +#define __SOC_QUALCOMM_SC7280_QSPI_H__ + +struct sc7280_qspi_regs { + u32 mstr_cfg; + u32 ahb_mstr_cfg; + u32 reserve_0; + u32 mstr_int_en; + u32 mstr_int_sts; + u32 pio_xfer_ctrl; + u32 pio_xfer_cfg; + u32 pio_xfer_sts; + u32 pio_dataout_1byte; + u32 pio_dataout_4byte; + u32 rd_fifo_cfg; + u32 rd_fifo_sts; + u32 rd_fifo_rst; + u32 reserve_1[3]; + u32 next_dma_desc_addr; + u32 current_dma_desc_addr; + u32 current_mem_addr; + u32 hw_version; + u32 rd_fifo[16]; +}; + +check_member(sc7280_qspi_regs, rd_fifo, 0x50); +static struct sc7280_qspi_regs * const sc7280_qspi = (void *) QSPI_BASE; + +// MSTR_CONFIG register + +#define TX_DATA_OE_DELAY_SHIFT 24 +#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) +#define TX_CS_N_DELAY_SHIFT 22 +#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) +#define TX_CLK_DELAY_SHIFT 20 +#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) +#define TX_DATA_DELAY_SHIFT 18 +#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) +#define LPA_BASE_SHIFT 14 +#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) +#define SBL_EN BIT(13) +#define CHIP_SELECT_NUM BIT(12) +#define SPI_MODE_SHIFT 10 +#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) +#define BIG_ENDIAN_MODE BIT(9) +#define DMA_ENABLE BIT(8) +#define PIN_WPN BIT(7) +#define PIN_HOLDN BIT(6) +#define FB_CLK_EN BIT(4) +#define FULL_CYCLE_MODE BIT(3) + +// MSTR_INT_ENABLE and MSTR_INT_STATUS register + +#define DMA_CHAIN_DONE BIT(31) +#define TRANSACTION_DONE BIT(16) +#define WRITE_FIFO_OVERRUN BIT(11) +#define WRITE_FIFO_FULL BIT(10) +#define HRESP_FROM_NOC_ERR BIT(3) +#define RESP_FIFO_RDY BIT(2) +#define RESP_FIFO_NOT_EMPTY BIT(1) +#define RESP_FIFO_UNDERRUN BIT(0) + +// PIO_TRANSFER_CONFIG register + +#define TRANSFER_FRAGMENT BIT(8) +#define MULTI_IO_MODE_SHIFT 1 +#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) +#define TRANSFER_DIRECTION BIT(0) + +// PIO_TRANSFER_STATUS register + +#define WR_FIFO_BYTES_SHIFT 16 +#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) + +// RD_FIFO_CONFIG register + +#define CONTINUOUS_MODE BIT(0) + +// RD_FIFO_STATUS register + +#define FIFO_EMPTY BIT(11) +#define WR_CNTS_SHIFT 4 +#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) +#define RDY_64BYTE BIT(3) +#define RDY_32BYTE BIT(2) +#define RDY_16BYTE BIT(1) +#define FIFO_RDY BIT(0) + +// RD_FIFO_RESET register + +#define RESET_FIFO BIT(0) + +#define QSPI_MAX_PACKET_COUNT 0xFFC0 + +void quadspi_init(uint32_t hz); +int sc7280_claim_bus(const struct spi_slave *slave); +int sc7280_setup_bus(const struct spi_slave *slave); +void sc7280_release_bus(const struct spi_slave *slave); +int sc7280_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +int sc7280_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +#endif /* __SOC_QUALCOMM_SC7280_QSPI_H__ */ diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c new file mode 100644 index 0000000..a6837bc --- /dev/null +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <arch/cache.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/qspi.h> +#include <soc/gpio.h> +#include <soc/clock.h> +#include <symbols.h> +#include <assert.h> +#include <gpio.h> +#include <string.h> + +#define CACHE_LINE_SIZE 64 + +static int curr_desc_idx = -1; + +struct cmd_desc { + uint32_t data_address; + uint32_t next_descriptor; + uint32_t direction:1; + uint32_t multi_io_mode:3; + uint32_t reserved1:4; + uint32_t fragment:1; + uint32_t reserved2:7; + uint32_t length:16; + //------------------------// + uint32_t bounce_src; + uint32_t bounce_dst; + uint32_t bounce_length; + uint64_t padding[5]; +}; + +enum qspi_mode { + SDR_1BIT = 1, + SDR_2BIT = 2, + SDR_4BIT = 3, + DDR_1BIT = 5, + DDR_2BIT = 6, + DDR_4BIT = 7, +}; + +enum cs_state { + CS_DEASSERT, + CS_ASSERT +}; + +struct xfer_cfg { + enum qspi_mode mode; +}; + +enum bus_xfer_direction { + MASTER_READ = 0, + MASTER_WRITE = 1, +}; + +struct { + struct cmd_desc descriptors[3]; + uint8_t buffers[3][CACHE_LINE_SIZE]; +} *dma = (void *)_dma_coherent; + +static void dma_transfer_chain(struct cmd_desc *chain) +{ + uint32_t mstr_int_status; + + write32(&sc7280_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7280_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + + while (1) { + mstr_int_status = read32(&sc7280_qspi->mstr_int_sts); + if (mstr_int_status & DMA_CHAIN_DONE) + break; + } +} + +static void flush_chain(void) +{ + struct cmd_desc *desc = &dma->descriptors[0]; + uint8_t *src; + uint8_t *dst; + + dma_transfer_chain(desc); + + while (desc) { + if (desc->direction == MASTER_READ) { + if (desc->bounce_length == 0) + dcache_invalidate_by_mva( + (void *)(uintptr_t) desc->data_address, + desc->length); + else { + src = (void *)(uintptr_t) desc->bounce_src; + dst = (void *)(uintptr_t) desc->bounce_dst; + memcpy(dst, src, desc->bounce_length); + } + } + desc = (void *)(uintptr_t) desc->next_descriptor; + } + curr_desc_idx = -1; +} + +static struct cmd_desc *allocate_descriptor(void) +{ + struct cmd_desc *current; + struct cmd_desc *next; + uint8_t index; + + current = (curr_desc_idx == -1) ? + NULL : &dma->descriptors[curr_desc_idx]; + + index = ++curr_desc_idx; + next = &dma->descriptors[index]; + + next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + + next->next_descriptor = 0; + next->direction = MASTER_READ; + next->multi_io_mode = 0; + next->reserved1 = 0; + /* + * QSPI controller doesn't support transfer starts with read segment. + * So to support read transfers that are not preceded by write, set + * transfer fragment bit = 1 + */ + next->fragment = 1; + next->reserved2 = 0; + next->length = 0; + next->bounce_src = 0; + next->bounce_dst = 0; + next->bounce_length = 0; + + if (current) + current->next_descriptor = (uint32_t)(uintptr_t) next; + + return next; +} + +static void cs_change(enum cs_state state) +{ + gpio_set(GPIO(15), state == CS_DEASSERT); +} + +static void configure_gpios(void) +{ + gpio_output(GPIO(15), 1); + + gpio_configure(GPIO(12), GPIO12_FUNC_QSPI_DATA_0, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + + gpio_configure(GPIO(13), GPIO13_FUNC_QSPI_DATA_1, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + + gpio_configure(GPIO(14), GPIO14_FUNC_QSPI_CLK, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); +} + +static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + uint8_t *ptr; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + ptr = (void *)(uintptr_t) desc->data_address; + + if (write) { + memcpy(ptr, data, data_bytes); + } else { + desc->bounce_src = (uint32_t)(uintptr_t) ptr; + desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_length = data_bytes; + } + + desc->length = data_bytes; +} + +static void queue_direct_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + desc->data_address = (uint32_t)(uintptr_t) data; + desc->length = data_bytes; + + if (write) + dcache_clean_by_mva(data, data_bytes); + else + dcache_invalidate_by_mva(data, data_bytes); +} + +static void queue_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + uint8_t *aligned_ptr; + uint8_t *epilog_ptr; + uint32_t prolog_bytes, aligned_bytes, epilog_bytes; + + if (data_bytes == 0) + return; + + aligned_ptr = + (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); + + prolog_bytes = MIN(data_bytes, aligned_ptr - data); + aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); + epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; + + epilog_ptr = data + prolog_bytes + aligned_bytes; + + if (prolog_bytes) + queue_bounce_data(data, prolog_bytes, data_mode, write); + if (aligned_bytes) + queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); + if (epilog_bytes) + queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); +} + +static void reg_init(void) +{ + uint32_t spi_mode; + uint32_t tx_data_oe_delay, tx_data_delay; + uint32_t mstr_config; + + spi_mode = 0; + + tx_data_oe_delay = 0; + tx_data_delay = 0; + + mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (spi_mode << SPI_MODE_SHIFT) | + (PIN_HOLDN) | + (FB_CLK_EN) | + (DMA_ENABLE) | + (FULL_CYCLE_MODE); + + write32(&sc7280_qspi->mstr_cfg, mstr_config); + write32(&sc7280_qspi->ahb_mstr_cfg, 0xA42); + write32(&sc7280_qspi->mstr_int_en, 0x0); + write32(&sc7280_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7280_qspi->rd_fifo_cfg, 0x0); + write32(&sc7280_qspi->rd_fifo_rst, RESET_FIFO); +} + +void quadspi_init(uint32_t hz) +{ + assert(dcache_line_bytes() == CACHE_LINE_SIZE); + clock_configure_qspi(hz * 4); + configure_gpios(); + reg_init(); +} + +int sc7280_claim_bus(const struct spi_slave *slave) +{ + cs_change(CS_ASSERT); + return 0; +} + +void sc7280_release_bus(const struct spi_slave *slave) +{ + cs_change(CS_DEASSERT); +} + +static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, + void *din, size_t in_bytes) +{ + if ((out_bytes && !dout) || (in_bytes && !din) || + (in_bytes && out_bytes)) { + return -1; + } + + queue_data((uint8_t *) (out_bytes ? dout : din), + in_bytes | out_bytes, mode, !!out_bytes); + + flush_chain(); + + return 0; +} + +int sc7280_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); +} + +int sc7280_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); +} diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c index 50aa395..61ccd86 100644 --- a/src/soc/qualcomm/sc7280/spi.c +++ b/src/soc/qualcomm/sc7280/spi.c @@ -2,12 +2,19 @@ #include <spi-generic.h> #include <spi_flash.h> +#include <soc/qspi.h> -static const struct spi_ctrlr spi_ctrlr; +static const struct spi_ctrlr qspi_ctrlr = { + .claim_bus = sc7280_claim_bus, + .release_bus = sc7280_release_bus, + .xfer = sc7280_xfer, + .xfer_dual = sc7280_xfer_dual, + .max_xfer_size = QSPI_MAX_PACKET_COUNT, +}; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { - .ctrlr = &spi_ctrlr, + .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/47075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d4159939a57648c54dcb06aea3645f1dfe10903 Gerrit-Change-Number: 47075 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: herobrine: SoC makefile blob support
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47074 ) Change subject: herobrine: SoC makefile blob support ...................................................................... herobrine: SoC makefile blob support Following blobs will includes with SoC makefile: * QCSEC * QUPV3FW Change-Id: Ic76af29440a6ef3a458381d63a819f5a1843e111 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47074/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 6d07629..d6f8d29 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -44,4 +44,28 @@ @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ $(objcbfs)/bootblock.bin +################################################################################ +UART_FW_FILE := $(SC7280_BLOB)/qup_fw/uart_fw.bin +UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw +$(UART_FW_CBFS)-file := $(UART_FW_FILE) +$(UART_FW_CBFS)-type := raw +$(UART_FW_CBFS)-compression := none +cbfs-files-y += $(UART_FW_CBFS) + +################################################################################ +SPI_FW_FILE := $(SC7280_BLOB)/qup_fw/spi_fw.bin +SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw +$(SPI_FW_CBFS)-file := $(SPI_FW_FILE) +$(SPI_FW_CBFS)-type := raw +$(SPI_FW_CBFS)-compression := none +cbfs-files-y += $(SPI_FW_CBFS) + +################################################################################ +I2C_FW_FILE := $(SC7280_BLOB)/qup_fw/i2c_fw.bin +I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw +$(I2C_FW_CBFS)-file := $(I2C_FW_FILE) +$(I2C_FW_CBFS)-type := raw +$(I2C_FW_CBFS)-compression := none +cbfs-files-y += $(I2C_FW_CBFS) + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76af29440a6ef3a458381d63a819f5a1843e111 Gerrit-Change-Number: 47074 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: SC7280: Add GPIO driver in coreboot
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47077 ) Change subject: SC7280: Add GPIO driver in coreboot ...................................................................... SC7280: Add GPIO driver in coreboot Add support for gpio driver for SC7280 Change-Id: Ibefa2fc04db09f1837f65f5a6d4b8534df040785 --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/gpio.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h M src/soc/qualcomm/sc7280/include/soc/gpio.h 4 files changed, 378 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47077/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index f94a425..a6112b3 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -8,12 +8,14 @@ bootblock-y += spi.c bootblock-$(CONFIG_SC7280_QSPI) += qspi.c bootblock-y += clock.c +bootblock-y += gpio.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-$(CONFIG_SC7280_QSPI) += qspi.c verstage-y += clock.c +verstage-y += gpio.c ################################################################################ romstage-y += cbmem.c @@ -25,6 +27,7 @@ romstage-y += spi.c romstage-$(CONFIG_SC7280_QSPI) += qspi.c romstage-y += clock.c +romstage-y += gpio.c ################################################################################ ramstage-y += soc.c @@ -33,6 +36,7 @@ ramstage-y += spi.c ramstage-$(CONFIG_SC7280_QSPI) += qspi.c ramstage-y += clock.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/gpio.c b/src/soc/qualcomm/sc7280/gpio.c new file mode 100644 index 0000000..67204e8 --- /dev/null +++ b/src/soc/qualcomm/sc7280/gpio.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <types.h> + +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ + assert(pull <= GPIO_PULL_UP); + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_OUTPUT_DISABLE); + + clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); + clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) + return 0; + + write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); + return 1; +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index ae31b1c..d2e50f2 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -8,5 +8,6 @@ #define AOSS_CC_BASE 0x0C2A0000 #define GCC_BASE 0x00100000 #define QSPI_BASE 0x088DC000 +#define TLMM_TILE_BASE 0x0F100000 #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h index 82a0c39..744ba49 100644 --- a/src/soc/qualcomm/sc7280/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -4,9 +4,293 @@ #define _SOC_QUALCOMM_SC7280_GPIO_H_ #include <types.h> +#include <soc/addressmap.h> typedef struct { u32 addr; } gpio_t; +#define TLMM_TILE_SIZE 0x00300000 +#define TLMM_GPIO_OFF_DELTA 0x1000 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +#define GPIO_FUNC_GPIO 0 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_OUTPUT_DISABLE 0 +#define GPIO_OUTPUT_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 174 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +#define PIN(index, func1, func2, func3, func4) \ +GPIO##index##_ADDR = TLMM_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4 + +enum { + PIN(0, QUP0_L0, RES_2, RES_3, RES_4), + PIN(1, QUP0_L1, RES_2, RES_3, RES_4), + PIN(2, QUP0_L2, QUP0_L4, RES_3, RES_4), + PIN(3, QUP0_L3, QUP0_L5, RES_3, RES_4), + PIN(4, QUP0_L0, RES_2, RES_3, RES_4), + PIN(5, QUP0_L1, RES_2, RES_3, RES_4), + PIN(6, QUP0_L2, QUP0_L6, RES_3, RES_4), + PIN(7, USB_AUDIO_INT_N__SBU_SW_OE, QUP0_L3, RES_3, RES_4), + PIN(8, QUP0_L0, RES_2, RES_3, RES_4), + PIN(9, QUP0_L1, RES_2, RES_3, RES_4), + PIN(10, GNSS_ELNA_EN0, QUP0_L2, RES_3, RES_4), + PIN(11, GNSS_ELNA_EN1, QUP0_L3, RES_3, RES_4), + PIN(12, QUP0_L0, QSPI_DATA_0, RES_3, RES_4), + PIN(13, QUP0_L1, QSPI_DATA_1, RES_3, RES_4), + PIN(14, QUP0_L2, QSPI_CLK, RES_3, RES_4), + PIN(15, QUP0_L3, QSPI_CS_N_0, RES_3, RES_4), + PIN(16, QUP0_L0, QSPI_DATA_2, RES_3, RES_4), + PIN(17, QUP0_L1, QSPI_DATA_3, RES_3, RES_4), + PIN(18, QUP0_L2, RES_2, RES_3, RES_4), + PIN(19, QUP0_L3, QSPI_CS_N_1, RES_3, RES_4), + PIN(20, QUP0_L0, CCI_TIMER_0, RES_3, RES_4), + PIN(21, QUP0_L1, CCI_TIMER_1, RES_3, RES_4), + PIN(22, QUP0_L2, RES_2, RES_3, RES_4), + PIN(23, QUP0_L3, RES_2, RES_3, RES_4), + PIN(24, QUP0_L0, RES_2, RES_3, RES_4), + PIN(25, QUP0_L1, RES_2, RES_3, RES_4), + PIN(26, QUP0_L2, RES_2, RES_3, RES_4), + PIN(27, QUP0_L3, RES_2, RES_3, RES_4), + PIN(28, QUP0_L0, RES_2, RES_3, RES_4), + PIN(29, QUP0_L1, RES_2, RES_3, RES_4), + PIN(30, QUP0_L2, RES_2, RES_3, RES_4), + PIN(31, QUP0_L3, RES_2, RES_3, RES_4), + PIN(32, QUP1_L0, RES_2, RES_3, RES_4), + PIN(33, QUP1_L1, RES_2, RES_3, RES_4), + PIN(34, QUP1_L2, RES_2, RES_3, RES_4), + PIN(35, QUP1_L3, RES_2, RES_3, RES_4), + PIN(36, QUP1_L0, RES_2, RES_3, RES_4), + PIN(37, QUP1_L1, RES_2, RES_3, RES_4), + PIN(38, QUP1_L2, QUP1_L6, RES_3, RES_4), + PIN(39, QUP1_L3, RES_2, RES_3, RES_4), + PIN(40, QUP1_L0, RES_2, RES_3, RES_4), + PIN(41, QUP1_L1, RES_2, RES_3, RES_4), + PIN(42, QUP1_L2, RES_2, RES_3, RES_4), + PIN(43, QUP1_L3, RES_2, RES_3, RES_4), + PIN(44, QUP1_L0, RES_2, RES_3, RES_4), + PIN(45, QUP1_L1, RES_2, RES_3, RES_4), + PIN(46, QUP1_L2, RES_2, RES_3, RES_4), + PIN(47, QUP1_L3, DP_HOT_PLUG_DETECT, RES_3, RES_4), + PIN(48, QUP1_L0, RES_2, RES_3, RES_4), + PIN(49, QUP1_L1, RES_2, RES_3, RES_4), + PIN(50, QUP1_L2, QUP1_L6, RES_3, RES_4), + PIN(51, QUP1_L3, RES_2, RES_3, RES_4), + PIN(52, QUP1_L0, RES_2, RES_3, RES_4), + PIN(53, QUP1_L1, RES_2, RES_3, RES_4), + PIN(54, QUP1_L2, QUP1_L5, RES_3, RES_4), + PIN(55, QUP1_L3, QUP1_L4, RES_3, RES_4), + PIN(56, QUP1_L0, RES_2, RES_3, RES_4), + PIN(57, QUP1_L1, RES_2, RES_3, RES_4), + PIN(58, QUP1_L2, RES_2, RES_3, RES_4), + PIN(59, QUP1_L3, RES_2, RES_3, RES_4), + PIN(60, QUP1_L0, EDP_HOT_PLUG_DETECT, RES_3, RES_4), + PIN(61, QUP1_L1, SD_WRITE_PROTECT, RES_3, RES_4), + PIN(62, QUP1_L2, QUP1_L4, RES_3, RES_4), + PIN(63, QUP1_L3, QUP1_L5, RES_3, RES_4), + PIN(64, CAM_MCLK0, RES_2, RES_3, RES_4), + PIN(65, CAM_MCLK1, RES_2, RES_3, RES_4), + PIN(66, CAM_MCLK2, RES_2, RES_3, RES_4), + PIN(67, CAM_MCLK3, RES_2, RES_3, RES_4), + PIN(68, CAM_MCLK4, RES_2, RES_3, RES_4), + PIN(69, CCI_I2C_SDA0, RES_2, RES_3, RES_4), + PIN(70, CCI_I2C_SCL0, RES_2, RES_3, RES_4), + PIN(71, CCI_I2C_SDA1, RES_2, RES_3, RES_4), + PIN(72, CCI_I2C_SCL1, RES_2, RES_3, RES_4), + PIN(73, CCI_I2C_SDA2, RES_2, RES_3, RES_4), + PIN(74, CCI_I2C_SCL2, RES_2, RES_3, RES_4), + PIN(75, CCI_I2C_SDA3, RES_2, RES_3, RES_4), + PIN(76, CCI_I2C_SCL3, GCC_GP1_CLK_MIRB, RES_3, RES_4), + PIN(77, CCI_TIMER2, GCC_GP2_CLK_MIRB, RES_3, RES_4), + PIN(78, CCI_TIMER3, CCI_ASYNC_IN1, GCC_GP3_CLK_MIRB, RES_4), + PIN(79, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4), + PIN(80, RES_1, RES_2, RES_3, RES_4), + PIN(81, RES_1, RES_2, RES_3, RES_4), + PIN(82, RES_1, RES_2, RES_3, RES_4), + PIN(83, RES_1, RES_2, RES_3, RES_4), + PIN(84, USB2PHY_AC_EN0, RES_2, RES_3, RES_4), + PIN(85, USB2PHY_AC_EN1, RES_2, RES_3, RES_4), + PIN(86, RES_1, RES_2, RES_3, RES_4), + PIN(87, RES_1, RES_2, RES_3, RES_4), + PIN(88, RES_1, RES_2, RES_3, RES_4), + PIN(89, RES_1, RES_2, RES_3, RES_4), + PIN(90, RES_1, RES_2, RES_3, RES_4), + PIN(91, RES_1, RES_2, RES_3, RES_4), + PIN(92, RES_1, RES_2, RES_3, RES_4), + PIN(93, CAM_MCLK5, CCI_ASYNC_IN0, RES_3, RES_4), + PIN(94, LPASS_SLIMBUS_CLK, RES_2, RES_3, RES_4), + PIN(95, LPASS_SLIMBUS_DATA0, RES_2, RES_3, RES_4), + PIN(96, PRI_MI2S_MCLK, RES_2, RES_3, RES_4), + PIN(97, MI2S0_SCK, RES_2, RES_3, RES_4), + PIN(98, MI2S0_DATA0, RES_2, RES_3, RES_4), + PIN(99, MI2S0_DATA1, RES_2, RES_3, RES_4), + PIN(100, MI2S0_WS, RES_2, RES_3, RES_4), + PIN(101, MI2S2_SCK, RES_2, RES_3, RES_4), + PIN(102, MI2S2_DATA0, RES_2, RES_3, RES_4), + PIN(103, MI2S2_WS, RES_2, RES_3, RES_4), + PIN(104, MI2S2_DATA1, RES_2, RES_3, RES_4), + PIN(105, SEC_MI2S_MCLK, MI2S1_DATA1, RES_3, GCC_GP1_CLK_MIRA), + PIN(106, MI2S1_SCK, GCC_GP2_CLK_MIRA, RES_3, RES_4), + PIN(107, MI2S1_DATA0, GCC_GP3_CLK_MIRA, RES_3, RES_4), + PIN(108, MI2S1_WS, RES_2, RES_3, RES_4), + PIN(109, RES_1, RES_2, RES_3, RES_4), + PIN(110, RES_1, RES_2, RES_3, RES_4), + PIN(111, RES_1, RES_2, RES_3, RES_4), + PIN(112, RES_1, RES_2, RES_3, RES_4), + PIN(113, RES_1, RES_2, RES_3, RES_4), + PIN(114, RES_1, RES_2, RES_3, RES_4), + PIN(115, RES_1, RES_2, RES_3, RES_4), + PIN(116, RES_1, RES_2, RES_3, RES_4), + PIN(117, RES_1, RES_2, RES_3, RES_4), + PIN(118, RES_1, RES_2, RES_3, RES_4), + PIN(119, RES_1, RES_2, RES_3, RES_4), + PIN(120, RES_1, RES_2, RES_3, RES_4), + PIN(121, RES_1, RES_2, RES_3, RES_4), + PIN(122, RES_1, RES_2, RES_3, RES_4), + PIN(123, RES_1, RES_2, RES_3, RES_4), + PIN(124, RES_1, RES_2, RES_3, RES_4), + PIN(125, RES_1, RES_2, RES_3, RES_4), + PIN(126, RES_1, RES_2, RES_3, RES_4), + PIN(127, RES_1, RES_2, RES_3, RES_4), + PIN(128, RES_1, RES_2, RES_3, RES_4), + PIN(129, RES_1, RES_2, RES_3, RES_4), + PIN(130, RES_1, RES_2, RES_3, RES_4), + PIN(131, RES_1, RES_2, RES_3, RES_4), + PIN(132, RES_1, RES_2, RES_3, RES_4), + PIN(133, RES_1, RES_2, RES_3, RES_4), + PIN(134, RES_1, RES_2, RES_3, RES_4), + PIN(135, RES_1, RES_2, RES_3, RES_4), + PIN(136, RES_1, RES_2, RES_3, RES_4), + PIN(137, RES_1, RES_2, RES_3, RES_4), + PIN(138, RES_1, RES_2, RES_3, RES_4), + PIN(139, RES_1, RES_2, RES_3, RES_4), + PIN(140, USB_PHY_PS, RES_2, RES_3, RES_4), + PIN(141, RES_1, RES_2, RES_3, RES_4), + PIN(142, RES_1, RES_2, RES_3, RES_4), + PIN(143, RES_1, RES_2, RES_3, RES_4), + PIN(144, RES_1, RES_2, RES_3, RES_4), + PIN(145, RES_1, RES_2, RES_3, RES_4), + PIN(146, RES_1, RES_2, RES_3, RES_4), + PIN(147, RES_1, RES_2, RES_3, RES_4), + PIN(148, RES_1, RES_2, RES_3, RES_4), + PIN(149, RES_1, RES_2, RES_3, RES_4), + PIN(150, RES_1, RES_2, RES_3, RES_4), + PIN(151, RES_1, RES_2, RES_3, RES_4), + PIN(152, RES_1, RES_2, RES_3, RES_4), + PIN(153, RES_1, RES_2, RES_3, RES_4), + PIN(154, RES_1, RES_2, RES_3, RES_4), + PIN(155, RES_1, RES_2, RES_3, RES_4), + PIN(156, RES_1, RES_2, RES_3, RES_4), + PIN(157, RES_1, RES_2, RES_3, RES_4), + PIN(158, RES_1, RES_2, RES_3, RES_4), + PIN(159, RES_1, RES_2, RES_3, RES_4), + PIN(160, RES_1, RES_2, RES_3, RES_4), + PIN(161, RES_1, RES_2, RES_3, RES_4), + PIN(162, RES_1, RES_2, RES_3, RES_4), + PIN(163, RES_1, RES_2, RES_3, RES_4), + PIN(164, RES_1, RES_2, RES_3, RES_4), + PIN(165, RES_1, RES_2, RES_3, RES_4), + PIN(166, RES_1, RES_2, RES_3, RES_4), + PIN(167, RES_1, RES_2, RES_3, RES_4), + PIN(168, RES_1, RES_2, RES_3, RES_4), + PIN(169, RES_1, RES_2, RES_3, RES_4), + PIN(170, RES_1, RES_2, RES_3, RES_4), + PIN(171, RES_1, RES_2, RES_3, RES_4), + PIN(172, RES_1, RES_2, RES_3, RES_4), + PIN(173, RES_1, RES_2, RES_3, RES_4), + PIN(174, RES_1, RES_2, RES_3, RES_4), +}; + +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + #endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibefa2fc04db09f1837f65f5a6d4b8534df040785 Gerrit-Change-Number: 47077 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 58

Change in coreboot[master]: HACK herobrine: prevent system from building bl31 HACK
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47905 ) Change subject: HACK herobrine: prevent system from building bl31 HACK ...................................................................... HACK herobrine: prevent system from building bl31 HACK Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I3fe63b8cc1afe3ad8cf334b74f0847369f32c8db --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/sc7280/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47905/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 44517cb..146d104 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -140,6 +140,7 @@ # Build ARM Trusted Firmware (BL31) ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifneq ($(CONFIG_SOC_QUALCOMM_SC7280),y) ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") @@ -216,6 +217,8 @@ endif # CONFIG_ARM64_USE_SECURE_OS +endif #CONFIG_SOC_QUALCOMM_SC7280 + endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index acbb36d..399d6ef 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -69,6 +69,14 @@ $(objcbfs)/bootblock.bin ################################################################################ +BL31_FILE := $(SC7280_BLOB)/qtiseclib/bl31.elf +BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 +$(BL31_CBFS)-file := $(BL31_FILE) +$(BL31_CBFS)-type := payload +$(BL31_CBFS)-compression := none +cbfs-files-y += $(BL31_CBFS) + +################################################################################ UART_FW_FILE := $(SC7280_BLOB)/qup_fw/uart_fw.bin UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw $(UART_FW_CBFS)-file := $(UART_FW_FILE) -- To view, visit https://review.coreboot.org/c/coreboot/+/47905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fe63b8cc1afe3ad8cf334b74f0847369f32c8db Gerrit-Change-Number: 47905 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020