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Change in coreboot[master]: sc7280: Add clock driver
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47076 ) Change subject: sc7280: Add clock driver ...................................................................... sc7280: Add clock driver Add support for clock driver for SC7280 Change-Id: I73661f709091da0a6bada43d20fb3bf4fe20b81c --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 5 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47076/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 33f6def..f94a425 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -7,11 +7,13 @@ bootblock-y += timer.c bootblock-y += spi.c bootblock-$(CONFIG_SC7280_QSPI) += qspi.c +bootblock-y += clock.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-$(CONFIG_SC7280_QSPI) += qspi.c +verstage-y += clock.c ################################################################################ romstage-y += cbmem.c @@ -22,6 +24,7 @@ romstage-y += mmu.c romstage-y += spi.c romstage-$(CONFIG_SC7280_QSPI) += qspi.c +romstage-y += clock.c ################################################################################ ramstage-y += soc.c @@ -29,6 +32,7 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-$(CONFIG_SC7280_QSPI) += qspi.c +ramstage-y += clock.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 9e04351..49c9e18 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/clock.h> #include <soc/mmu.h> #include <soc/qspi.h> @@ -8,4 +9,5 @@ { sc7280_mmu_init(); quadspi_init(37500 * KHz); + clock_init(); } diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c new file mode 100644 index 0000000..f8285ba --- /dev/null +++ b/src/soc/qualcomm/sc7280/clock.c @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/clock.h> +#include <timer.h> +#include <types.h> + +#define DIV(div) (2 * div - 1) + +struct clock_config qup_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + } +}; + +struct clock_config qspi_core_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(6), + }, + { + .hz = 200 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(3), + }, + { + .hz = 400 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(1.5), + }, +}; + +struct clock_config qup_wrap_cfg[] = { + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = 32 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 75, + .d_2 = 75, + }, + { + .hz = 48 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 4, + .n = 25, + .d_2 = 25, + }, + { + .hz = 64 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 16, + .n = 75, + .d_2 = 75, + }, + { + .hz = 96 * MHz, + .src = SRC_GPLL0_EVEN_300MHZ, + .div = DIV(1), + .m = 8, + .n = 25, + .d_2 = 25, + }, + { + .hz = 100 * MHz, + .src = SRC_GPLL0_MAIN_600MHZ, + .div = DIV(6), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, + { + .hz = SRC_XO_HZ, /* 19.2KHz */ + .src = SRC_XO_19_2MHZ, + .div = DIV(1), + }, +}; + +static int clock_configure_gpll0(void) +{ + clrbits32(&gcc->gpll0.config_ctl_u1, + BIT(CLK_CTL_GPLL_BB_CAL_CORR_INDEX_SHFT)); + setbits32(&gcc->gpll0.config_ctl_u1, + BIT(CLK_CTL_GPLL_PCODE_OFFET_28) | + BIT(CLK_CTL_GPLL_PCODE_OFFET_29)); + + /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ + setbits32(&gcc->gpll0.user_ctl, + 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | + 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); + + return CB_SUCCESS; +} + +static int clock_configure_mnd(struct sc7280_clock *clk, uint32_t m, uint32_t n, + uint32_t d_2) +{ + struct sc7280_mnd_clock *mnd = (struct sc7280_mnd_clock *)clk; + setbits32(&clk->rcg_cfg, + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); + write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); + + return CB_SUCCESS; +} + +static int clock_configure(struct sc7280_clock *clk, + struct clock_config *clk_cfg, + uint32_t hz, uint32_t num_perfs) +{ + uint32_t reg_val; + uint32_t idx; + + for (idx = 0; idx < num_perfs; idx++) + if (hz <= clk_cfg[idx].hz) + break; + + assert(hz == clk_cfg[idx].hz); + + reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + /* Set clock config */ + write32(&clk->rcg_cfg, reg_val); + + if (clk_cfg[idx].m != 0) + clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, + clk_cfg[idx].d_2); + + /* Commit config to RCG*/ + setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + + return CB_SUCCESS; +} + +static bool clock_is_off(u32 *cbcr_addr) +{ + return (read32(cbcr_addr) & CLK_CTL_CBC_CLK_OFF_BMSK); +} + +static int clock_enable_vote(void *cbcr_addr, void *vote_addr, + uint32_t vote_bit) +{ + int count = 200; + + /* Set clock vote bit */ + setbits32(vote_addr, BIT(vote_bit)); + + /* Ensure clock is enabled */ + while (count-- > 0) { + if (!clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + return CB_ERR; +} + +static int clock_enable(void *cbcr_addr) +{ + int count = 200; + + /* Set clock enable bit */ + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + + /* Ensure clock is enabled */ + while (count-- > 0) { + if (!clock_is_off(cbcr_addr)) + return CB_SUCCESS; + udelay(1); + } + return CB_ERR; +} + +void clock_reset_aop(void) +{ + /* Bring AOP out of RESET */ + clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT)); +} + +void clock_configure_qspi(uint32_t hz) +{ + clock_configure(&gcc->qspi_core, + qspi_core_cfg, hz, + ARRAY_SIZE(qspi_core_cfg)); + clock_enable(&gcc->qspi_cnoc_ahb_cbcr); + clock_enable(&gcc->qspi_core_cbcr); +} + +int clock_reset_bcr(void *bcr_addr, bool reset) +{ + struct sc7280_bcr *bcr = bcr_addr; + + if (reset) + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_SHFT)); + else + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_SHFT)); + + return CB_SUCCESS; +} + +void clock_configure_dfsr(int qup) +{ + int idx; + int s = qup % QUP_WRAP1_S0; + uint32_t reg_val; + struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, + BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), + BIT(CLK_CTL_CMD_DFSR_SHFT)); + + for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { + reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | + (qup_wrap_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); + + write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); + + if (qup_wrap_cfg[idx].m == 0) + continue; + + setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], + RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); + + reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].n - qup_wrap_cfg[idx].m) + & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); + + reg_val = ~(qup_wrap_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; + write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); + } +} + +void clock_configure_qup(int qup, uint32_t hz) +{ + int s = qup % QUP_WRAP1_S0; + struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + clock_configure(&qup_clk->mnd_clk.clock, qup_cfg, hz, + ARRAY_SIZE(qup_cfg)); +} + +void clock_enable_qup(int qup) +{ + int s = qup % QUP_WRAP1_S0; + int clk_en_off = qup < QUP_WRAP1_S0 ? + QUPV3_WRAP0_CLK_ENA_S(s) : QUPV3_WRAP1_CLK_ENA_S(s); + struct sc7280_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? + &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; + + if(qup == 14 || qup == 15) + clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en, + (qup-1)); + else + clock_enable_vote(&qup_clk->mnd_clk, &gcc->apcs_clk_br_en1, + clk_en_off); +} + +void clock_init(void) +{ + clock_configure_gpll0(); + + clock_enable_vote(&gcc->qup_wrap0_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP0_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap0_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_0_S_AHB_CLK_ENA); + + clock_enable_vote(&gcc->qup_wrap1_core_2x_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_2X_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_core_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP1_CORE_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_m_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_M_AHB_CLK_ENA); + clock_enable_vote(&gcc->qup_wrap1_s_ahb_cbcr, + &gcc->apcs_clk_br_en1, + QUPV3_WRAP_1_S_AHB_CLK_ENA); +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 70d17be..ae31b1c 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -5,4 +5,8 @@ #include <stdint.h> +#define AOSS_CC_BASE 0x0C2A0000 +#define GCC_BASE 0x00100000 +#define QSPI_BASE 0x088DC000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h new file mode 100644 index 0000000..947f262 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/clock.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <types.h> + +#ifndef __SOC_QUALCOMM_SC7280_CLOCK_H__ +#define __SOC_QUALCOMM_SC7280_CLOCK_H__ + +#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6 +#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7 +#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9 +#define QUPV3_WRAP0_CORE_CLK_ENA 8 +#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18 +#define QUPV3_WRAP1_CORE_CLK_ENA 19 +#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20 +#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21 +#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx) +#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx) + +#define SRC_XO_HZ (19200 * KHz) +#define GPLL0_EVEN_HZ (300 * MHz) +#define GPLL0_MAIN_HZ (600 * MHz) + +#define SRC_XO_19_2MHZ 0 +#define SRC_GPLL0_MAIN_600MHZ 1 +#define SRC_GPLL0_EVEN_300MHZ 6 + +#define AOP_RESET_SHFT 0 +#define RCG_MODE_DUAL_EDGE 2 + +#define SCALE_FREQ_SHFT 11 + +struct sc7280_clock { + u32 rcg_cmd; + u32 rcg_cfg; +}; + +struct sc7280_mnd_clock { + struct sc7280_clock clock; + u32 m; + u32 n; + u32 d_2; +}; + +struct sc7280_dfsr_clock { + u32 cmd_dfsr; + u8 _res0[0x20 - 0x1c]; + u32 perf_dfsr[8]; + u8 _res1[0x60 - 0x40]; + u32 perf_m_dfsr[8]; + u8 _res2[0xa0 - 0x80]; + u32 perf_n_dfsr[8]; + u8 _res3[0xe0 - 0xc0]; + u32 perf_d_dfsr[8]; + u8 _res4[0x130 - 0x100]; +}; + +struct sc7280_qupv3_clock { + u32 cbcr; + struct sc7280_mnd_clock mnd_clk; + struct sc7280_dfsr_clock dfsr_clk; +}; + +struct sc7280_gpll { + u32 mode; + u32 l_val; + u32 cal_l_val; + u32 user_ctl; + u32 user_ctl_u; + u32 user_Ctl_u1; + u32 config_ctl; + u32 config_ctl_u; + u32 config_ctl_u1; + u32 test_ctl; + u32 test_ctl_u; + u32 test_ctl_u1; + u8 _res[0x1000 - 0x30]; +}; + +struct sc7280_gcc { + struct sc7280_gpll gpll0; + u8 _res1[0x17000 - 0x1000]; + u32 qup_wrap0_bcr; + u32 qup_wrap0_m_ahb_cbcr; + u32 qup_wrap0_s_ahb_cbcr; + struct sc7280_qupv3_clock qup_wrap0_s[8]; + u8 _res3[0x18000 - 0x1798c]; + u32 qup_wrap1_bcr; + u32 qup_wrap1_m_ahb_cbcr; + u32 qup_wrap1_s_ahb_cbcr; + struct sc7280_qupv3_clock qup_wrap1_s[8]; + u8 _res4[0x23000 - 0x1898c]; + u32 qup_wrap0_core_cbcr; + u32 qup_wrap0_core_cdivr; + u32 qup_wrap0_core_2x_cbcr; + struct sc7280_clock qup_wrap0_core_2x; + u8 _res5[0x23138 - 0x23014]; + u32 qup_wrap1_core_cbcr; + u32 qup_wrap1_core_cdivr; + u32 qup_wrap1_core_2x_cbcr; + struct sc7280_clock qup_wrap1_core_2x; + u8 _res6[0x4b000 - 0x2314c]; + u32 qspi_bcr; + u32 qspi_cnoc_ahb_cbcr; + u32 qspi_core_cbcr; + struct sc7280_clock qspi_core; + u8 _res7[0x52000 - 0x4b014]; + u32 apcs_clk_br_en; + u8 _res8[0x52008 - 0x52004]; + u32 apcs_clk_br_en1; + u8 _res9[0x1000000 - 0x5200c]; +}; +check_member(sc7280_gcc, qup_wrap0_bcr, 0x17000); +check_member(sc7280_gcc, qup_wrap1_bcr, 0x18000); +check_member(sc7280_gcc, qup_wrap1_core_cbcr, 0x23138); +check_member(sc7280_gcc, apcs_clk_br_en1, 0x52008); + +struct sc7280_aoss { + u8 _res0[0x50020]; + u32 aoss_cc_reset_status; + u8 _res1[0x5002C - 0x50024]; + u32 aoss_cc_apcs_misc; +}; +check_member(sc7280_aoss, aoss_cc_reset_status, 0x50020); +check_member(sc7280_aoss, aoss_cc_apcs_misc, 0x5002C); + +enum clk_ctl_gpll_user_ctl { + CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2, + CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, + CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1, + CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2 +}; + +enum clk_ctl_gpll_config_ctl { + CLK_CTL_GPLL_BB_CAL_CORR_INDEX_SHFT = 14, + CLK_CTL_GPLL_PCODE_OFFET_28 = 28, + CLK_CTL_GPLL_PCODE_OFFET_29 = 29, +}; + +enum clk_ctl_cfg_rcgr { + CLK_CTL_CFG_HW_CTL_BMSK = 0x100000, + CLK_CTL_CFG_HW_CTL_SHFT = 20, + CLK_CTL_CFG_MODE_BMSK = 0x3000, + CLK_CTL_CFG_MODE_SHFT = 12, + CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, + CLK_CTL_CFG_SRC_SEL_SHFT = 8, + CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, + CLK_CTL_CFG_SRC_DIV_SHFT = 0 +}; + +enum clk_ctl_cmd_rcgr { + CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, + CLK_CTL_CMD_ROOT_OFF_SHFT = 31, + CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, + CLK_CTL_CMD_ROOT_EN_SHFT = 1, + CLK_CTL_CMD_UPDATE_BMSK = 0x1, + CLK_CTL_CMD_UPDATE_SHFT = 0 +}; + +enum clk_ctl_cbcr { + CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, + CLK_CTL_CBC_CLK_OFF_SHFT = 31, + CLK_CTL_CBC_CLK_EN_BMSK = 0x1, + CLK_CTL_CBC_CLK_EN_SHFT = 0 +}; + +enum clk_ctl_rcg_mnd { + CLK_CTL_RCG_MND_BMSK = 0xFFFF, + CLK_CTL_RCG_MND_SHFT = 0, +}; + +enum clk_ctl_bcr { + CLK_CTL_BCR_BLK_BMSK = 0x1, + CLK_CTL_BCR_BLK_SHFT = 0, +}; + +enum clk_ctl_dfsr { + CLK_CTL_CMD_DFSR_BMSK = 0x1, + CLK_CTL_CMD_DFSR_SHFT = 0, + CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, +}; + +enum clk_qup { + QUP_WRAP0_S0, + QUP_WRAP0_S1, + QUP_WRAP0_S2, + QUP_WRAP0_S3, + QUP_WRAP0_S4, + QUP_WRAP0_S5, + QUP_WRAP0_S6, + QUP_WRAP0_S7, + QUP_WRAP1_S0, + QUP_WRAP1_S1, + QUP_WRAP1_S2, + QUP_WRAP1_S3, + QUP_WRAP1_S4, + QUP_WRAP1_S5, + QUP_WRAP1_S6, + QUP_WRAP1_S7, +}; + +struct clock_config { + uint32_t hz; + uint8_t src; + uint8_t div; + uint16_t m; + uint16_t n; + uint16_t d_2; +}; + +static struct sc7280_gcc *const gcc = (void *)GCC_BASE; +static struct sc7280_aoss *const aoss = (void *)AOSS_CC_BASE; + +void clock_init(void); +void clock_reset_aop(void); +void clock_configure_qspi(uint32_t hz); +int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_configure_qup(int qup, uint32_t hz); +void clock_enable_qup(int qup); +void clock_configure_dfsr(int qup); +void clock_last_reset_was_watchdog(void); + +#endif // __SOC_QUALCOMM_SC7280_CLOCK_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/47076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73661f709091da0a6bada43d20fb3bf4fe20b81c Gerrit-Change-Number: 47076 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: sc7280: Limit SPI-NOR size
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Hello Sajida Bhanu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47145 to review the following change. Change subject: sc7280: Limit SPI-NOR size ...................................................................... sc7280: Limit SPI-NOR size Limit SPI-NOR size to 8MB. Change-Id: I31f788b5280636aca3e7e557db3e9ee53320d50d Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/drivers/spi/stmicro.c M src/mainboard/google/herobrine/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47145/1 diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4cd8c1b..b02edf6 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -189,7 +189,7 @@ { /* N25Q256..1E */ .id[0] = STM_ID_N25Q256__1E, - .nr_sectors_shift = 13, + .nr_sectors_shift = 11, }, }; diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 92f77db..b92136d 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -14,7 +14,7 @@ select RTC select SOC_QUALCOMM_SC7280 select SPI_FLASH - select SPI_FLASH_WINBOND + select SPI_FLASH_STMICRO select MAINBOARD_HAS_CHROMEOS config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/47145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f788b5280636aca3e7e557db3e9ee53320d50d Gerrit-Change-Number: 47145 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/{apl,glk}: add options to configure GPU
by Maxim Polyakov (Code Review) 17 Mar '22

17 Mar '22

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39374 ) Change subject: soc/intel/{apl,glk}: add options to configure GPU ...................................................................... soc/intel/{apl,glk}: add options to configure GPU Adds options to select the primary GPU device and configure IGD, which allows to override the appropriate FSP options in the SoC code. These changes do not affect the configuration of the boards with the Apollo Lake and Gemini Lake processors, because if these parameters are not defined in the devicetree, they will be set to the default values. Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/romstage.c 2 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/39374/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 40cd39b..0375cec 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,46 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size */ + enum { + DVMT_64MB = 2, /* Default */ + DVMT_96MB, + DVMT_128MB, + DVMT_160MB, + DVMT_192MB, + DVMT_224MB, + DVMT_256MB, + DVMT_288MB, + DVMT_320MB, + DVMT_352MB, + DVMT_384MB, + DVMT_416MB, + DVMT_448MB, + DVMT_480MB, + DVMT_512MB, + } igd_dvmt_50_pre_alloc_size; + + /* Select the Aperture Size for GPU device */ + enum { + APERTURE_128MB = 1, /* Default */ + APERTURE_256MB, + APERTURE_512MB, + } igd_aperture_size; + + /* Select the GTT Size for GPU device */ + enum { + GTT_2MB = 1, + GTT_4MB, + GTT_8MB, /* Default */ + } igd_gtt_size; + + /* Select primary GPU device */ + enum { + PRIMARY_AUTO = 0, /* Default */ + PRIMARY_IGD = 2, + PRIMARY_PCI = 3, + } primary_gpu; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 05cd0db..1576802 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -264,12 +264,34 @@ } } +static void soc_gpu_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct soc_intel_apollolake_config *soc_cfg = config_of_soc(); + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + + m_cfg->PrimaryVideoAdaptor = soc_cfg->primary_gpu; + if (dev && dev->enabled && (soc_cfg->primary_gpu != PRIMARY_PCI)) { + /* + * Override FSP settings for IGD only if they are set in the devicetree. + * Otherwise, the default values from UPD will be used for them + */ + if (soc_cfg->igd_dvmt_50_pre_alloc_size) + m_cfg->IgdDvmt50PreAlloc = soc_cfg->igd_dvmt_50_pre_alloc_size; + + if (soc_cfg->igd_aperture_size) + m_cfg->IgdApertureSize = soc_cfg->igd_aperture_size; + + if (soc_cfg->igd_gtt_size) + m_cfg->GttSize = soc_cfg->igd_gtt_size; + } +} + static void soc_memory_init_params(FSPM_UPD *mupd) { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); /* @@ -307,6 +329,7 @@ check_full_retrain(mupd); fill_console_params(mupd); + soc_gpu_init_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); -- To view, visit https://review.coreboot.org/c/coreboot/+/39374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcd117217cf412ee0722aff52db4b3c8ec2a226c Gerrit-Change-Number: 39374 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 51

Change in coreboot[master]: src/*: Make PCI ID macro names shorter
by Felix Singer (Code Review) 07 Mar '22

07 Mar '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39331 ) Change subject: src/*: Make PCI ID macro names shorter ...................................................................... src/*: Make PCI ID macro names shorter This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_. Used commands: find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/' {} \; find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} \; Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 --- M src/device/pci_rom.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/dec/21143/21143.c M src/drivers/generic/bayhub/bh720.c M src/drivers/intel/gma/opregion.c M src/drivers/intel/i210/i210.c M src/drivers/intel/ish/ish.c M src/drivers/intel/wifi/wifi.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/xgi/common/XGI_main.h M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/z9s/z9s.c M src/include/device/pci_ids.h M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/iommu.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/iommu.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/iommu.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/gma.c M src/soc/amd/common/block/hda/hda.c M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/sata/sata.c M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/usb.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/usb.c M src/soc/cavium/common/pci/uart.c M src/soc/intel/apollolake/report_platform.c M src/soc/intel/baytrail/ehci.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/baytrail/pcie.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/sd.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/xhci.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/xhci.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smbus.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/vr_config.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/mmc.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/pmc.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/quark/ehci.c M src/soc/intel/quark/gpio_i2c.c M src/soc/intel/quark/lpc.c M src/soc/intel/quark/northcluster.c M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi.c M src/soc/intel/quark/uart.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/vr_config.c M src/soc/intel/tigerlake/bootblock/report_platform.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/ide.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/pci.c M src/southbridge/amd/agesa/hudson/pcie.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/ide.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/pci.c M src/southbridge/amd/pi/hudson/pcie.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/ide.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/usb.c M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/ide.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/pci.c M src/southbridge/intel/i82801dx/usb.c M src/southbridge/intel/i82801dx/usb2.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/ide.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/nic.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/sata.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/pci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801ix/usb_ehci.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/pci.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/i82801jx/usb_ehci.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h 228 files changed, 4,921 insertions(+), 4,921 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/39331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Gerrit-Change-Number: 39331 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

12 47

Change in coreboot[master]: drivers/system76/dgpu: Add driver for System76 switchable graphics
by Jeremy Soller (Code Review) 03 Mar '22

03 Mar '22

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43615 ) Change subject: drivers/system76/dgpu: Add driver for System76 switchable graphics ...................................................................... drivers/system76/dgpu: Add driver for System76 switchable graphics This adds a driver for System76 systems with switchable NVIDIA graphics. The driver provides ACPI support for dynamically powering on and off the GPU, a function for enabling the GPU power in the bootblock, and a hook in ramstage for moving GPU prefetch resources above 4 GiB. Tested on system76/addw2, system76/gaze15, and system76/oryp6, which will be submitted in future patches. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I05833e88457bfc3612cc9a8cbf1eec68dcfc5566 --- A src/drivers/system76/dgpu/Kconfig A src/drivers/system76/dgpu/Makefile.inc A src/drivers/system76/dgpu/acpi/dgpu.asl A src/drivers/system76/dgpu/bootblock.c A src/drivers/system76/dgpu/ramstage.c 5 files changed, 313 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43615/1 diff --git a/src/drivers/system76/dgpu/Kconfig b/src/drivers/system76/dgpu/Kconfig new file mode 100644 index 0000000..5096671 --- /dev/null +++ b/src/drivers/system76/dgpu/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_SYSTEM76_DGPU + bool + default n + help + System76 switchable graphics support diff --git a/src/drivers/system76/dgpu/Makefile.inc b/src/drivers/system76/dgpu/Makefile.inc new file mode 100644 index 0000000..a230f97 --- /dev/null +++ b/src/drivers/system76/dgpu/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_SYSTEM76_DGPU) += ramstage.c diff --git a/src/drivers/system76/dgpu/acpi/dgpu.asl b/src/drivers/system76/dgpu/acpi/dgpu.asl new file mode 100644 index 0000000..a721934 --- /dev/null +++ b/src/drivers/system76/dgpu/acpi/dgpu.asl @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (\_SB.PCI0.PEGP) { + Name (_ADR, 0x00010000) + + PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON) { + Debug = "PEGP.PWRR._ON" + If (_STA != 1) { + \_SB.PCI0.PEGP.DEV0._ON () + _STA = 1 + } + } + + Method (_OFF) { + Debug = "PEGP.PWRR._OFF" + If (_STA != 0) { + \_SB.PCI0.PEGP.DEV0._OFF () + _STA = 0 + } + } + } + + Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR }) + Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR }) + Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR }) +} + +Device (\_SB.PCI0.PEGP.DEV0) { + Name(_ADR, 0x00000000) + Name (_STA, 0xF) + Name (LTRE, 0) + + // Memory mapped PCI express registers + // Not sure what this stuff is, but it is used to get into GC6 + OperationRegion (RPCX, SystemMemory, 0xE0008000, 0x1000) + Field (RPCX, ByteAcc, NoLock, Preserve) { + PVID, 16, + PDID, 16, + CMDR, 8, + Offset (0x19), + PRBN, 8, + Offset (0x84), + D0ST, 2, + Offset (0xAA), + CEDR, 1, + Offset (0xAC), + , 4, + CMLW, 6, + Offset (0xB0), + ASPM, 2, + , 2, + P0LD, 1, + RTLK, 1, + Offset (0xC9), + , 2, + LREN, 1, + Offset (0x11A), + , 1, + VCNP, 1, + Offset (0x214), + Offset (0x216), + P0LS, 4, + Offset (0x248), + , 7, + Q0L2, 1, + Q0L0, 1, + Offset (0x504), + Offset (0x506), + PCFG, 2, + Offset (0x508), + TREN, 1, + Offset (0xC20), + , 4, + P0AP, 2, + Offset (0xC38), + , 3, + P0RM, 1, + Offset (0xC74), + P0LT, 4, + Offset (0xD0C), + , 20, + LREV, 1 + } + + Method (_ON) { + Debug = "PEGP.DEV0._ON" + + If (_STA != 0xF) { + Debug = " If DGPU_PWR_EN low" + If (! GTXS (DGPU_PWR_EN)) { + Debug = " DGPU_PWR_EN high" + STXS (DGPU_PWR_EN) + + Debug = " Sleep 16" + Sleep (16) + } + + Debug = " DGPU_RST_N high" + STXS(DGPU_RST_N) + + Debug = " Sleep 10" + Sleep (10) + + Debug = " Q0L0 = 1" + Q0L0 = 1 + + Debug = " Sleep 16" + Sleep (16) + + Debug = " While Q0L0" + Local0 = 0 + While (Q0L0) { + If ((Local0 > 4)) { + Debug = " While Q0L0 timeout" + Break + } + + Sleep (16) + Local0++ + } + + Debug = " P0RM = 0" + P0RM = 0 + + Debug = " P0AP = 0" + P0AP = 0 + + Debug = Concatenate(" LREN = ", ToHexString(LTRE)) + LREN = LTRE + + Debug = " CEDR = 1" + CEDR = 1 + + Debug = " CMDR |= 7" + CMDR |= 7 + + Debug = " _STA = 0xF" + _STA = 0xF + } + } + + Method (_OFF) { + Debug = "PEGP.DEV0._OFF" + + If (_STA != 0x5) { + Debug = Concatenate(" LTRE = ", ToHexString(LREN)) + LTRE = LREN + + Debug = " Q0L2 = 1" + Q0L2 = 1 + + Debug = " Sleep 16" + Sleep (16) + + Debug = " While Q0L2" + Local0 = Zero + While (Q0L2) { + If ((Local0 > 4)) { + Debug = " While Q0L2 timeout" + Break + } + + Sleep (16) + Local0++ + } + + Debug = " P0RM = 1" + P0RM = 1 + + Debug = " P0AP = 3" + P0AP = 3 + + Debug = " Sleep 10" + Sleep (10) + + Debug = " DGPU_RST_N low" + CTXS(DGPU_RST_N) + + Debug = " While DGPU_GC6 low" + Local0 = Zero + While (! GRXS(DGPU_GC6)) { + If ((Local0 > 4)) { + Debug = " While DGPU_GC6 low timeout" + + Debug = " DGPU_PWR_EN low" + CTXS (DGPU_PWR_EN) + Break + } + + Sleep (16) + Local0++ + } + + Debug = " _STA = 0x5" + _STA = 0x5 + } + } +} diff --git a/src/drivers/system76/dgpu/bootblock.c b/src/drivers/system76/dgpu/bootblock.c new file mode 100644 index 0000000..61f7fbf --- /dev/null +++ b/src/drivers/system76/dgpu/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO: do not require this to be included in mainboard bootblock.c + +#include <console/console.h> +#include <delay.h> +#include <gpio.h> + +static void dgpu_power_enable(int onoff) { + printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff); + if (onoff) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + mdelay(4); + gpio_set(DGPU_RST_N, 1); + } else { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} diff --git a/src/drivers/system76/dgpu/ramstage.c b/src/drivers/system76/dgpu/ramstage.c new file mode 100644 index 0000000..eeb1607 --- /dev/null +++ b/src/drivers/system76/dgpu/ramstage.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci.h> + +static void dgpu_read_resources(struct device *dev) { + printk(BIOS_INFO, "system76: dgpu_read_resources %s\n", dev_path(dev)); + + pci_dev_read_resources(dev); + + int bar; + // Find all BARs on DGPU, mark them above 4g if prefetchable + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { + printk(BIOS_INFO, " BAR at 0x%02x\n", bar); + + struct resource *res; + res = probe_resource(dev, bar); + if (res) { + if (res->flags & IORESOURCE_PREFETCH) { + printk(BIOS_INFO, " marked above 4g\n"); + res->flags |= IORESOURCE_ABOVE_4G; + } else { + printk(BIOS_INFO, " not prefetch\n"); + } + } else { + printk(BIOS_INFO, " not found\n"); + } + } +} + +static void dgpu_enable_resources(struct device *dev) { + printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev)); + + dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID; + dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID; + printk(BIOS_INFO, " subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device); + pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff)); + + pci_dev_enable_resources(dev); +} + +static struct device_operations dgpu_pci_ops_dev = { + .read_resources = dgpu_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = dgpu_enable_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt = pci_rom_ssdt, +#endif + .init = pci_dev_init, + .ops_pci = &pci_dev_ops_pci, +}; + +static void dgpu_above_4g(void *unused) { + struct device *pdev; + + // Find PEG0 + pdev = pcidev_on_root(1, 0); + if (!pdev) { + printk(BIOS_ERR, "system76: failed to find PEG0\n"); + return; + } + printk(BIOS_INFO, "system76: PEG0 at %p, %04x:%04x\n", pdev, pdev->vendor, pdev->device); + + int fn; + for (fn = 0; fn < 8; fn++) { + struct device *dev; + + // Find DGPU functions + dev = pcidev_path_behind(pdev->link_list, PCI_DEVFN(0, fn)); + if (dev) { + printk(BIOS_INFO, "system76: DGPU fn %d at %p, %04x:%04x\n", fn, dev, dev->vendor, dev->device); + dev->ops = &dgpu_pci_ops_dev; + } else { + printk(BIOS_ERR, "system76: failed to find DGPU fn %d\n", fn); + } + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, dgpu_above_4g, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/43615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05833e88457bfc3612cc9a8cbf1eec68dcfc5566 Gerrit-Change-Number: 43615 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: drivers/intel/fsp2_0 - Change boot state notification Change boot sta...
by Rocky Phagura (Code Review) 16 Feb '22

16 Feb '22

Rocky Phagura has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43979 ) Change subject: drivers/intel/fsp2_0 - Change boot state notification Change boot state notification of FSP to before payload is loaded into memory. Currently the flow is as follows: 1. Load payload into memory 2. Notify FSP of boot state init 3. Jump to payload code ...................................................................... drivers/intel/fsp2_0 - Change boot state notification Change boot state notification of FSP to before payload is loaded into memory. Currently the flow is as follows: 1. Load payload into memory 2. Notify FSP of boot state init 3. Jump to payload code This patch changes the flow to: 1. Notify FSP of boot state 2. Load payload into memory 3. Jump to payload code This prevents code corruption of payload. At this stage of boot, there is no concept of memory management, therefore FSP can use any memory it needs. After making these changes, Tianocore payload is able to load properly where previously its memory was getting corrupted. TEST=build for Tiogapass platform under OCP mainboard and select Tianocore payload. Boot the system and ensure target OS loads. Change-Id: I122edc12abf992cb3e5ec53747a7cef9c94aee8e Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/43979/1 diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..ba8ef9e 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -68,7 +68,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy, (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, fsp_notify_dummy, (void *) READY_TO_BOOT); BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, (void *) READY_TO_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/43979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I122edc12abf992cb3e5ec53747a7cef9c94aee8e Gerrit-Change-Number: 43979 Gerrit-PatchSet: 1 Gerrit-Owner: Rocky Phagura Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: disable emi bw threshold monitor
by Xi Chen (Code Review) 16 Feb '22

16 Feb '22

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47383 ) Change subject: TEST-ONLY: soc/mediatek/mt8192: disable emi bw threshold monitor ...................................................................... TEST-ONLY: soc/mediatek/mt8192: disable emi bw threshold monitor Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I6053da10a1f41836cb455d30fd2bcd7a84047121 --- M src/soc/mediatek/mt8192/emi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47383/1 diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c old mode 100644 new mode 100755 index d485131..4b971d0 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -346,9 +346,11 @@ setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); setbits32(&emi_mpu->mpu_ctrl_d[7], BIT(4)); +#ifdef ENABLE_EMI_BW_THRESHOLD write32(&emi_reg->bwct0, 0x05008305); write32(&emi_reg->bwct0_6th, 0x08ff8705); write32(&emi_reg->bwct0_3rd, 0x0dff8a05); +#endif setbits32(&emi_reg->thro_ctrl1, 0x3 << 8); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6053da10a1f41836cb455d30fd2bcd7a84047121 Gerrit-Change-Number: 47383 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: TEST-ONLY: soc/mediatek/mt8192: add dram full scan
by Xi Chen (Code Review) 16 Feb '22

16 Feb '22

Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48071 ) Change subject: TEST-ONLY: soc/mediatek/mt8192: add dram full scan ...................................................................... TEST-ONLY: soc/mediatek/mt8192: add dram full scan Used to check all dram address read/write is ok or not. Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com> Change-Id: I4d1c7adfd49910287ceccf08d667acdc41b209d5 --- M src/soc/mediatek/common/memory_test.c M src/soc/mediatek/mt8192/include/soc/emi.h M src/soc/mediatek/mt8192/memory.c 3 files changed, 64 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48071/1 diff --git a/src/soc/mediatek/common/memory_test.c b/src/soc/mediatek/common/memory_test.c index 51f3b23..b917341 100644 --- a/src/soc/mediatek/common/memory_test.c +++ b/src/soc/mediatek/common/memory_test.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/emi.h> +#include <console/console.h> + +#define LOGH printk(BIOS_ERR, "%s@%d\n", __func__, __LINE__); enum { /* test patterns */ @@ -22,6 +25,37 @@ PATTERNF = 0xFFFFFFFF }; +int mem_test_fullscan(u8 *start, unsigned long long len) +{ + unsigned int *mem32_base = (unsigned int *)start; + unsigned long long i, size; + + printk(BIOS_INFO, "Test length: 0x%llx\n", len); + LOGH; + size = len >> 2; + + /* verify the tied bits (tied high) */ + for (i = 0; i < size; i++) { + mem32_base[i] = (unsigned int)i; + if (i % 100000 == 0) + printk(BIOS_INFO, "mem write: pos: %llx\n", i); + } + + LOGH; + for (i = 0; i < size; i++) { + if (mem32_base[i] != (unsigned int)i) { + printk(BIOS_ERR, "%s failed at %llx, value: 0x%x, expected: 0x%x\n", + __func__, i, (unsigned int)i, mem32_base[i]); + return -1; + } + if (i % 100000 == 0) + printk(BIOS_INFO, "mem compare: pos: %llx\n", i); + } + + return 0; +} + + int complex_mem_test(u8 *start, unsigned int len) { unsigned char *mem8_base = (unsigned char *)start; @@ -34,12 +68,14 @@ unsigned int value; uintptr_t p; + LOGH; size = len >> 2; /* verify the tied bits (tied high) */ for (i = 0; i < size; i++) mem32_base[i] = PATTERN0; + LOGH; for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN0) return -1; @@ -47,6 +83,7 @@ mem32_base[i] = PATTERNF; } + LOGH; /* verify the tied bits (tied low) */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERNF) @@ -58,11 +95,14 @@ pattern8 = PATTERN0; for (i = 0; i < len; i++) mem8_base[i] = pattern8++; + + LOGH; pattern8 = PATTERN0; for (i = 0; i < len; i++) { if (mem8_base[i] != pattern8++) return -3; } + LOGH; /* verify pattern 2 (0x00~0xff) */ pattern8 = PATTERN0; @@ -74,7 +114,8 @@ pattern8 += 2; } - + LOGH; + /* verify pattern 3 (0x00~0xffff) */ pattern16 = PATTERN0; for (i = 0; i < (len >> 1); i++) @@ -84,7 +125,7 @@ if (mem16_base[i] != pattern16++) return -5; } - + LOGH; /* verify pattern 4 (0x00~0xffffffff) */ pattern32 = PATTERN0; for (i = 0; i < (len >> 2); i++) @@ -94,7 +135,7 @@ if (mem32_base[i] != pattern32++) return -6; } - + LOGH; /* pattern 5: filling memory range with 0x12345678 */ for (i = 0; i < size; i++) mem32_base[i] = PATTERNE; @@ -106,7 +147,7 @@ mem32_base[i] = PATTERN2; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 0h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN2) @@ -114,7 +155,7 @@ mem8_base[i * 4] = PATTERN0; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 2h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN3) @@ -122,7 +163,7 @@ mem8_base[i * 4 + 2] = PATTERN0; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 1h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN4) @@ -130,7 +171,7 @@ mem8_base[i * 4 + 1] = PATTERN0; } - + LOGH; /* read check then fill memory with 00 byte pattern at offset 3h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN5) @@ -138,7 +179,7 @@ mem8_base[i * 4 + 3] = PATTERN0; } - + LOGH; /* read check then fill memory with ffff word pattern at offset 1h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN0) @@ -146,7 +187,7 @@ mem16_base[i * 2 + 1] = PATTERN7; } - + LOGH; /* read check then fill memory with ffff word pattern at offset 0h */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERN6) @@ -154,13 +195,13 @@ mem16_base[i * 2] = PATTERN7; } - + LOGH; /* read check */ for (i = 0; i < size; i++) { if (mem32_base[i] != PATTERNF) return -14; } - + LOGH; /* stage 1 => write 0 */ for (i = 0; i < size; i++) mem_base[i] = PATTERN1; @@ -174,7 +215,7 @@ mem_base[i] = PATTERN2; } - + LOGH; /* stage 3 => read 0xf, write 0 */ for (i = 0; i < size; i++) { value = mem_base[i]; @@ -183,7 +224,7 @@ mem_base[i] = PATTERN1; } - + LOGH; /* stage 4 => read 0, write 0xf */ for (i = 0; i < size; i++) { value = mem_base[i]; @@ -192,7 +233,7 @@ mem_base[i] = PATTERN2; } - + LOGH; /* stage 5 => read 0xf, write 0 */ for (i = 0; i < size; i++) { value = mem_base[i]; @@ -201,14 +242,14 @@ mem_base[i] = PATTERN1; } - + LOGH; /* stage 6 => read 0 */ for (i = 0; i < size; i++) { value = mem_base[i]; if (value != PATTERN1) return -19; } - + LOGH; /* 1/2/4-byte combination test */ p = (uintptr_t)mem_base; @@ -246,13 +287,13 @@ *((unsigned int *)p) = PATTERNE; p += 4; } - + LOGH; for (i = 0; i < size; i++) { value = mem_base[i]; if (value != PATTERNE) return -20; } - + LOGH; /* verify pattern 1 (0x00~0xff) */ pattern8 = PATTERN0; mem8_base[0] = pattern8; @@ -268,7 +309,7 @@ pattern8++; } - + LOGH; /* verify pattern 2 (0x00~0xffff) */ pattern16 = PATTERN0; mem16_base[0] = pattern16; @@ -280,7 +321,7 @@ pattern16++; } - + LOGH; /* verify pattern 3 (0x00~0xffffffff) */ pattern32 = PATTERN0; mem32_base[0] = pattern32; @@ -292,6 +333,6 @@ pattern32++; } - + LOGH; return 0; } diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h old mode 100644 new mode 100755 index 02a90be..fee49ed --- a/src/soc/mediatek/mt8192/include/soc/emi.h +++ b/src/soc/mediatek/mt8192/include/soc/emi.h @@ -9,5 +9,6 @@ void mt_set_emi(const struct dramc_data *dparam); void mt_mem_init(struct dramc_param_ops *dparam_ops); int complex_mem_test(u8 *start, unsigned int len); +int mem_test_fullscan(u8 *start, unsigned long long len); #endif /* SOC_MEDIATEK_MT8192_EMI_H */ diff --git a/src/soc/mediatek/mt8192/memory.c b/src/soc/mediatek/mt8192/memory.c old mode 100644 new mode 100755 index 549dede..3f90d30 --- a/src/soc/mediatek/mt8192/memory.c +++ b/src/soc/mediatek/mt8192/memory.c @@ -16,7 +16,7 @@ const struct ddr_base_info *ddr_info = &dparam->ddr_info; for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { - int result = complex_mem_test(addr, 0x2000); + int result = mem_test_fullscan(addr, (unsigned long long)sdram_size()); if (result != 0) { printk(BIOS_ERR, -- To view, visit https://review.coreboot.org/c/coreboot/+/48071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d1c7adfd49910287ceccf08d667acdc41b209d5 Gerrit-Change-Number: 48071 Gerrit-PatchSet: 1 Gerrit-Owner: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/dedede/var/drawcia: Enable microcode in-field update
by Sugnan Prabhu S (Code Review) 14 Feb '22

14 Feb '22

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47199 ) Change subject: mb/google/dedede/var/drawcia: Enable microcode in-field update ...................................................................... mb/google/dedede/var/drawcia: Enable microcode in-field update This enables the top swap based microcode in-field update. BUG=b:149547271 TEST=Build and boot drawcia to OS. Check ucode staging area is updated with microcode in FW_MAIN_A/B and the top swap is enabled. Change-Id: I40f2a628d6408930d698756e2cb6f8c535623cf9 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/google/dedede/Kconfig.name 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47199/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 31495a1..238b4ca 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -22,6 +22,8 @@ select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select DRIVERS_INTEL_MIPI_CAMERA + select INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_DRAWCIA_LEGACY -- To view, visit https://review.coreboot.org/c/coreboot/+/47199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f2a628d6408930d698756e2cb6f8c535623cf9 Gerrit-Change-Number: 47199 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/p2b: list all unused Super I/O resources
by Keith Hui (Code Review) 03 Feb '22

03 Feb '22

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41459 ) Change subject: mb/asus/p2b: list all unused Super I/O resources ...................................................................... mb/asus/p2b: list all unused Super I/O resources Some Super I/O resources were unused and not listed, causing warnings during resource allocation. Suppress these warnings by setting them to zero. Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41459/1 diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 9f7f63e..7ee69e4 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -18,6 +18,7 @@ device pnp 3f0.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 0 end device pnp 3f0.2 on # COM1 io 0x60 = 0x3f8 @@ -34,6 +35,9 @@ irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 3f0.7 on # GPIO 1 + io 0x60 = 0 + io 0x62 = 0 + irq 0x70 = 0 end device pnp 3f0.8 on # GPIO 2 end -- To view, visit https://review.coreboot.org/c/coreboot/+/41459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e Gerrit-Change-Number: 41459 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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