coreboot-gerrit November 2020

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Change in coreboot[master]: Documentation/contributing/project_ideas.md: add resource allocation ...
by Jeremy Soller (Code Review) 10 Jun '23

10 Jun '23

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39455 ) Change subject: Documentation/contributing/project_ideas.md: add resource allocation project ...................................................................... Documentation/contributing/project_ideas.md: add resource allocation project Change-Id: I278ee622be2ab4a3d26bd5a180e7471236a828b8 --- M Documentation/contributing/project_ideas.md 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/39455/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 2c621f4..4198501 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -184,3 +184,15 @@ ### Mentors * TODO + +## Implement 64-bit resource allocation +Currently the coreboot allocator is limited to 32-bit allocation, which can be +problematic for systems with a large number of memory-mapped devices, or +devices with large memory regions, or hot-pluggable buses. + +### Requirements +* Understand the basics of PCI resource allocation, and be willing to learn + more about coreboot's resource allocation. + +### Mentors +* Jeremy Soller <jeremy(a)system76.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/39455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278ee622be2ab4a3d26bd5a180e7471236a828b8 Gerrit-Change-Number: 39455 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/ifdtool: modify IFD regions
by Marcello Sylvester Bauer (Code Review) 10 Jun '23

10 Jun '23

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38832 ) Change subject: Documentation/ifdtool: modify IFD regions ...................................................................... Documentation/ifdtool: modify IFD regions Add documentation about using ifdtool to modify the region rangers, with examples. Change-Id: I862bd851fc68365ca11aa0477ae4e4002f1eeea7 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M Documentation/ifdtool/layout.md 1 file changed, 53 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38832/1 diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md index 950db6f..c09cfaa 100644 --- a/Documentation/ifdtool/layout.md +++ b/Documentation/ifdtool/layout.md @@ -4,7 +4,7 @@ layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md). -The FMAP should define all of the of the regions defined by the IFD to ensure +The FMAP should define all offsets of the regions defined by the IFD to ensure that those regions are accounted for by coreboot and will not be accidentally modified. @@ -23,7 +23,7 @@ |4|Platform Data|SI_PDR|| |8|EC Firmware|SI_EC|Most Chrome OS devices do not use this region; EC firmware is stored BIOS region of flash| -## Validation +## Modification The ifdtool can be used to manipulate a firmware image with a IFD. This tool will not take into account the FMAP while modifying the image which can lead to @@ -32,6 +32,56 @@ ME, then when the ME is added by the ifdtool 6 MB will be written which could overwrite 2 MB of the BIOS. +### Manual Modification + +It is possible to adjust the IFD regions on a firmware image or on a Flash Descriptor file directly. +In the case of modifying a complete firmware image, it will also move the data content of each region. + +The process consists of three steps: + 1) dump the ifd layout file out of the firmware/descriptor image + 2) modify the ifd region defined on the layout file + 3) update the firmware/descriptor image using the new layout + +#### Example - Reduce the ME Region size + +##### Step 1 - Dump IFD regions into a flashrom layout file + $ ifdtool -f ifd_old.layout descriptor.bin + Wrote layout to ifd-old.layout + + $ cat ifd_old.layout + 00000000:00000fff fd + 00500000:007fffff bios + 00003000:004fffff me + 00001000:00002fff gbe + +##### Step 2 - Modify the layout file + $ diff ifd_old.layout ifd_new.layout + 2,3c2,3 + < 00500000:007fffff bios + < 00003000:004fffff me + --- + > 00020000:007fffff bios + > 00003000:0001ffff me + +##### Step 3 - Update the IFD regions + $ ifdtool -n ifd_new.layout descriptor.bin + [...] + Writing new image to descriptor.bin.new + +### build-time Modification + +Instead of using the the ifdtool directly, it is possible to define a flashrom layout file in the +coreboot configuration, so that it will be modified at build-time. + + $ make menuconfig + Chipset ---> + [*] Add Intel descriptor.bin file + (path/to/descriptor.bin) Path and filename of the descriptor.bin file + [*] update regions using a flashrom layout file + (path/to/ifd.layout) Path and filename flashrom layout file + +## Validation + In order to validate that the FMAP and the IFD are compatible the ifdtool provides --validate (-t) option. `ifdtool -t` will read both the IFD and the FMAP in the image and for every non empty region in the IFD if that region is @@ -63,4 +113,4 @@ FMAP area SI_PDR: offset: 0x007fc000 length: 0x00004000 -``` \ No newline at end of file +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/38832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862bd851fc68365ca11aa0477ae4e4002f1eeea7 Gerrit-Change-Number: 38832 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/d945gclf: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40205 ) Change subject: mb/intel/d945gclf: Remove ACPI generic sleep button SLPB ...................................................................... mb/intel/d945gclf: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 6.429967] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input2 [ 6.437520] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device. Fixes: 1a08f582 ("preliminary Intel D945GCLF Atom+i945 support.") Change-Id: I0174bffe53bcc9f86db793e2a05f6e95d86dbd10 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/intel/d945gclf/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40205/1 diff --git a/src/mainboard/intel/d945gclf/acpi/mainboard.asl b/src/mainboard/intel/d945gclf/acpi/mainboard.asl index 5187b2a..bb86c6c 100644 --- a/src/mainboard/intel/d945gclf/acpi/mainboard.asl +++ b/src/mainboard/intel/d945gclf/acpi/mainboard.asl @@ -12,14 +12,6 @@ * GNU General Public License for more details. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0174bffe53bcc9f86db793e2a05f6e95d86dbd10 Gerrit-Change-Number: 40205 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Felix Singer (Code Review) 10 Jun '23

10 Jun '23

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39830 to review the following change. Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... libpayload/x86: Try to discover invariant TSC rate We can skip the PIT-based TSC calibration if we can derive the invariant TSC rate from platform data. This is also necessary if the PIT is dis- abled, which is the default, for instance, on Coffee Lake CPUs. Change-Id: I34eed1cbf14a8bf3fe6d58f51a4be139f4d30759 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/arch/x86/timer.c 1 file changed, 58 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39830/1 diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index bf0c30a..6b07e17 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -34,6 +34,10 @@ #include <libpayload.h> #include <arch/rdtsc.h> +#include <arch/cpuid.h> +#include <arch/msr.h> + +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch @@ -46,7 +50,7 @@ * * @return The CPU speed in kHz. */ -unsigned int get_cpu_speed(void) +static unsigned int calibrate_pit(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -72,7 +76,59 @@ * clock_rate / (interval * 1000). Multiply that by the number of * measured clocks to get the kHz value. */ - cpu_khz = (end - start) * clock_rate / (1000 * interval); + return (end - start) * clock_rate / (1000 * interval); +} + +/** + * @brief Returns three times the bus clock in MHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ +static int get_bus_khz_x3(void) +{ + uint32_t eax, ebx, ecx, edx; + cpuid(1, eax, ebx, ecx, edx); + + /* Check for family 6 */ + if (((eax & 0xff00000) >> (20 - 4)) | ((eax & 0xf00) >> 8 != 6)) + return -1; + + switch (((eax & 0xf0000) >> (16 - 4)) | ((eax & 0xf0) >> 4)) { + case 0x25: /* Nehalem */ + return 400 * 1000; /* 133 MHz */ + case 0x2a: /* SandyBridge */ + case 0x3a: /* IvyBridge */ + case 0x3c: /* Haswell */ + case 0x45: /* Haswell-ULT */ + case 0x9e: /* Coffee Lake H */ + return 300 * 1000; /* 100 MHz */ + default: + return -1; + } +} + +/* + * Systems with an invariant TSC report the multiplier (maximum + * non-turbo ratio) in MSR_PLATFORM_INFO[15:8]. + */ +static int get_cpu_khz_fast(void) +{ + const int bus_x3 = get_bus_khz_x3(); + if (bus_x3 <= 0) + return -1; + + const unsigned int mult = _rdmsr(MSR_PLATFORM_INFO) >> 8 & 0xff; + return (bus_x3 * mult) / 3; +} + +unsigned int get_cpu_speed(void) +{ + const int cpu_khz_fast = get_cpu_khz_fast(); + if (cpu_khz_fast > 0) + cpu_khz = (unsigned int)cpu_khz_fast; + else + cpu_khz = calibrate_pit(); return cpu_khz; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34eed1cbf14a8bf3fe6d58f51a4be139f4d30759 Gerrit-Change-Number: 39830 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gigabyte/ga-945gcm-s2l: Remove ACPI generic sleep button SLPB
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40204 ) Change subject: mb/gigabyte/ga-945gcm-s2l: Remove ACPI generic sleep button SLPB ...................................................................... mb/gigabyte/ga-945gcm-s2l: Remove ACPI generic sleep button SLPB Currently, Linux detects the ACPI generic sleep button SLPB defined by coreboot. [ 5.162651] input: Sleep Button as /devices/LNXSYSTM:00/PNP0C0E:00/input/input1 [ 5.163192] ACPI: Sleep Button [SLPB] But, this is a desktop board, and doesn’t have a sleep button. So, remove that probably copy-pasted ACPI device (intel/d945gclf). Fixes: be913983 ("mb/gigabyte/ga-945gcm-s2l: add mainboard") Change-Id: I36803d0f437e6556c5bdc82f2fd0ceb0562bc935 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/40204/1 diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl index 1e31c06..4c37212 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl @@ -1,14 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -Device (SLPB) -{ - Name(_HID, EisaId("PNP0C0E")) - - // Wake - Name(_PRW, Package(){0x1d, 0x04}) -} - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) -- To view, visit https://review.coreboot.org/c/coreboot/+/40204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36803d0f437e6556c5bdc82f2fd0ceb0562bc935 Gerrit-Change-Number: 40204 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: Device tree for Microtech etabpro Platform Intel GLK Tablet with the ...
by Miroslaw Kocur (Code Review) 10 Jun '23

10 Jun '23

Miroslaw Kocur has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40353 ) Change subject: Device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard ...................................................................... Device tree for Microtech etabpro Platform Intel GLK Tablet with the stylus and attachable keyboard Not working so far Fixed: - finally trying to start but not working yet Changes: - not much yet Change-Id: I154cb9abeba3e27cbb16acfd35012a996f099a92 Signed-off-by: Miroslaw Kocur <mirek190(a)gmail.com> --- M src/mainboard/microtech/etabpro/Kconfig M src/mainboard/microtech/etabpro/bootblock.c M src/mainboard/microtech/etabpro/etab.fmd M src/mainboard/microtech/etabpro/gpio.c M src/mainboard/microtech/etabpro/memory.c 5 files changed, 253 insertions(+), 220 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/40353/1 diff --git a/src/mainboard/microtech/etabpro/Kconfig b/src/mainboard/microtech/etabpro/Kconfig index aa7c106..716aadb 100644 --- a/src/mainboard/microtech/etabpro/Kconfig +++ b/src/mainboard/microtech/etabpro/Kconfig @@ -10,14 +10,29 @@ select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_LPC_TPM + select USE_BLOBS + select NEED_LBP2 + select LBP2_FROM_IFWI + select CONSOLE_SPI_FLASH # Blobs -# select NEED_IFWI -# select HAVE_IFD_BIN + select ADD_FSP_BINARIES +# select FSP_M_XIP +# select FSP_USE_REPO + select NEED_IFWI + select HAVE_IFD_BIN # config for GLK INTEL_EC # Not sure is VBOOT_NO_BOARD_SUPPORT is needed to work coreboot on GLK. Without it we got error if I choose GLK INTEL_EC... select EC_ACPI # select VBOOT_NO_BOARD_SUPPORT +config FSP_M_FILE + string + default "3rdparty/blobs/mainboard/microtech/etabpro/fspm.bin" + +config FSP_S_FILE + string + default "3rdparty/blobs/mainboard/microtech/etabpro/fsps.bin" + config IFWI_FILE string default "3rdparty/blobs/mainboard/microtech/etabpro/ifwi.bin" diff --git a/src/mainboard/microtech/etabpro/bootblock.c b/src/mainboard/microtech/etabpro/bootblock.c index 8f6f563..d17d0c3 100644 --- a/src/mainboard/microtech/etabpro/bootblock.c +++ b/src/mainboard/microtech/etabpro/bootblock.c @@ -26,5 +26,5 @@ lpc_configure_pads(); pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - full_reset(); +// full_reset(); } diff --git a/src/mainboard/microtech/etabpro/etab.fmd b/src/mainboard/microtech/etabpro/etab.fmd index c71088a..c350ab2 100644 --- a/src/mainboard/microtech/etabpro/etab.fmd +++ b/src/mainboard/microtech/etabpro/etab.fmd @@ -1,7 +1,7 @@ FLASH 8M { SI_DESC 0x1000 SI_BIOS { - IFWI 0x2ff000 + IFWI 0x300000 OBBP { FMAP 0x1000 RO_FRID 0x40 diff --git a/src/mainboard/microtech/etabpro/gpio.c b/src/mainboard/microtech/etabpro/gpio.c index 71c0d16..19c17a1 100644 --- a/src/mainboard/microtech/etabpro/gpio.c +++ b/src/mainboard/microtech/etabpro/gpio.c @@ -22,222 +22,228 @@ * the table so those were moved for more logical grouping. */ static const struct pad_config gpio_table[] = { -/* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 1, DEEP, UP_20K, TxDRxE, SAME),/*Ec-to-SOC CS Wake */ - PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Touch Pad Interrupt */ - PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, SAME),/*PMIC Interrupt*/ - PAD_CFG_GPI_APIC_IOS(GPIO_20, UP_20K, DEEP, LEVEL, INVERT, IGNORE, SAME),/* Audio Codec Interrupt*/ - PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ - PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_CFG_GPO_GPIO_DRIVER(GPIO_24, 1, DEEP, DN_20K), - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, SAME),/*WWAN /RF_KILL_GPS*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/* NFC Interrupt */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD),/* RF_KILL_WiFi/WiFi_Disable */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, DISPUPD),/* RF_KILL_BT/BT_Disable */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx0, DISPUPD),/* Codec Power Down: Output/ISH_GPIO_3*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_30, DN_20K, DEEP, NF1), /* ISH_GPIO_4 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_31, DN_20K, DEEP, NF1), /* ISH_GPIO_5 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_32, DN_20K, DEEP, NF1), /* ISH_GPIO_6 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_33, DN_20K, DEEP, NF1), /* ISH_GPIO_7 */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_34, DN_20K, DEEP, NF1), /* ISH_GPIO_8/SUSCLK2 (1.8V) */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_35, UP_20K, DEEP, NF6), /* BSSB_CLK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_36, UP_20K, DEEP, NF6), /* BSSB_DI */ - PAD_CFG_GPI_SCI_IOS(GPIO_37, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Runtime SCI */ - PAD_CFG_GPI_SCI_IOS(GPIO_38, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/*Wake SCI */ - PAD_CFG_GPI_APIC_IOS(GPIO_39, DN_20K, DEEP, LEVEL, NONE, IGNORE, SAME),/* Finger Print Sensor Interrupt (DRDY) */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_40, UP_20K, DEEP, NF6),/*IERR (USB Camera Power Enable)*/ - PAD_CFG_GPI_SMI_IOS(GPIO_41, UP_20K, DEEP, EDGE_SINGLE, NONE, IGNORE, SAME),/*SOC_EXTSMI_N */ - PAD_CFG_NF(GPIO_42, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE1 */ - PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */ - PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */ - PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* DSI_I2C_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SDA - Audio Codec*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_2K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C0_SCL - Audio Codec */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SDA - NFC */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_I2C1_SCL - NFC */ - PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_54, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SDA*/ - PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_55, UP_20K, DEEP, HIZCRx1, ENPU),/*LPSS_I2C2_SCL*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* I2C3-SDA - DBG (PSS, SINAI2, MIPI) */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C3-SCL - DBG (PSS, SINAI2, MIPI) */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SDA - Touch Pad*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*I2C4-SCL - Touch Pad*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RXD - M.2dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-TXD - M.2dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-RTS_B - M.2 dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/* UART0-CTS_B - M.2 dGNSS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */ -#if CONFIG(TPM_ON_FAST_SPI) - PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */ -#endif - PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/ - PAD_CFG_GPI_APIC(GPIO_69, DN_20K, DEEP, EDGE_SINGLE, NONE),/*SIM Detect*/ - PAD_CFG_NF(GPIO_70, DN_20K, DEEP, NF1),/*PMC_SPI_FS2*/ - PAD_CFG_NF(GPIO_71, DN_20K, DEEP, NF1),/*PMC_SPI_RXD*/ - PAD_CFG_NF(GPIO_72, DN_20K, DEEP, NF1),/*PMC_SPI_TXD*/ - PAD_CFG_NF(GPIO_73, DN_20K, DEEP, NF1),/*PMC_SPI_CLK*/ - PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/*THERMTRIP_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_75, UP_20K, DEEP, NF1, HIZCRx1),/*PROCHOT_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/ - PAD_CFG_GPI_GPIO_DRIVER(GPIO_212, UP_20K, DEEP),/*Touch Panel Int*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, NONE, HIZCRx0, SAME),/*DNX LED - CSE owned*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, HIZCRx0, SAME),/*LAN Isolate*/ -/* NORTH COMMUNITY GPIOS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, UP_20K, DEEP, NF1),/*SVID Alert*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, UP_20K, DEEP, NF1),/* SVID Data */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, UP_20K, DEEP, NF1),/* SVID Clk */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_79, NATIVE, DEEP, NF1),/* Finger Print Sensor */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_80, NATIVE, DEEP, NF1),/* Finger Print Sensor CS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3),/* FST_SPI_CS2_B - TPM */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_82, NATIVE, DEEP, NF1),/* Finger Print Sensor */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_83, NATIVE, DEEP, NF1),/* Finger Print Sensor */ - PAD_CFG_NF_IOSSTATE(GPIO_84, NONE, DEEP, NF3, HIZCRx1),/* SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_85, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch CS*/ - PAD_CFG_NF_IOSSTATE(GPIO_86, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_87, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_88, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSSTATE(GPIO_89, DN_20K, DEEP, NF3, HIZCRx1),/*Function 3: SPI iTouch*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_90, NATIVE, DEEP, NF1),/*Function 1: FST SPI Boot Flash CS*/ - PAD_CFG_GPIO_HI_Z(GPIO_91, NATIVE, DEEP, IGNORE, SAME),/*FST_SPI_CS1_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_92, DN_20K, DEEP, NF1),/*FST_SPI_MOSI_IO0*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_93, NATIVE, DEEP, NF1),/*FST_SPI_MISO_IO1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_94, NATIVE, DEEP, NF1),/*FST_SPI_IO2*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_95, NATIVE, DEEP, NF1),/*FST_SPI_IO3*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_96, NATIVE, DEEP, NF1),/*FST_SPI_CLK*/ - PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1),/*FST_SPI_CLK_FB*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/*PMU_PLTRST_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_99, UP_20K, DEEP, NF1),/*PMU_PWRBTN_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/*PMU_SLP_S0_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/*PMU_SLP_S3_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx0RxDCRx0, SAME),/*x4 Slot-2 Reset*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1),/*SUS_STAT_B*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SDA*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C5_SCL*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SDA*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_20K, DEEP, NF2, HIZCRx1, ENPU),/*LPSS_I2C6_SCL*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SDA*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/*LPSS_I2C7_SCL*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_116, UP_20K, DEEP, NF1),/*PCIE_WAKE0_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/ - PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* unused */ - PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/ - PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/ - PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/ - PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/ - PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/ - PAD_CFG_NF_IOSSTATE(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ - PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/ - PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/ - PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*DGPU Power Select*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/ - PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/ - PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/ - PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/ - PAD_CFG_GPI_APIC_IOS(GPIO_143, NONE, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ - PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*NFC reset*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, UP_20K, IGNORE, SAME),/*SD_MODE for spk*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_BCLK*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_WS_SYNC*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*Touch Panel Power Enable*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_SDO*/ - -/* AUDIO COMMUNITY GPIOS*/ - - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_BCLK*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_WS_SYNC*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, DN_20K, DEEP, NF2, HIZCRx1, SAME),/* AVS_I2S2_SDI*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S2_SD0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx1, SAME),/*AVS_I2S1_MCLK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1),/*AVS_M_CLK_A1*/ - PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_B1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1),/*AVS_M_DATA_1*/ - PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1),/*AVS_M_CLK_AB2*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD),/*AVS_M_DATA_2*/ - -/* SCC COMMUNITY GPIOS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_176, UP_20K, DEEP, NF1),/*SMB_ALERTB*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1),/*SMB_CLK*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1),/*SMB_DATA*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, DN_20K, DEEP, NF1),/*SDCARD_LVL_WP*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD),/*SDCARD_CLK*/ - PAD_CFG_NF(GPIO_180, DN_20K, DEEP, NF1),/*SDCARD_CLK_FB*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D1*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D2*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_D3*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*SDCARD_CMD*/ - PAD_CFG_NF(GPIO_186, NONE, DEEP, NF1),/*SDCARD_CD_B*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, NONE, TxDRxE, SAME),/*SD Card*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), - PAD_CFG_NF_IOSSTATE(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_0*/ - PAD_CFG_NF_IOSSTATE(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0),/*OSC_CLK_OUT_1*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1),/*CNV_BRI_DT*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1),/*CNV_BRI_RSP*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1),/*CNV_RGI_DT*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1),/*CNV_RGI_RSP*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1),/*CNV_RF_RESET_B*/ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NONE, DEEP, NF1),/*XTAL_CLKREQ*/ - PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1),/*SDIO_CLK_FB*/ - PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/ - PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/ - PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/ - PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/ - PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/ - PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/ - PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/ - PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/ - PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/ - PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/ - PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/ - PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_STROBE*/ + /* NORTHWEST COMMUNITY GPIOS */ + _PAD_CFG_STRUCT(GPIO_0, 0x44000700, 0x00c01000), // JTAG_TCK + _PAD_CFG_STRUCT(GPIO_1, 0x44000700, 0x00c01000), // JTAG_TRST_N + _PAD_CFG_STRUCT(GPIO_2, 0x44000700, 0x00c03000), // JTAG_TMS + _PAD_CFG_STRUCT(GPIO_3, 0x44000700, 0x00c03000), // JTAG_TDI + _PAD_CFG_STRUCT(GPIO_4, 0x44000700, 0x00c03000), // JTAG_TDO + _PAD_CFG_STRUCT(GPIO_5, 0x44000300, 0x00c3c000), // GPIO + _PAD_CFG_STRUCT(GPIO_6, 0x44000402, 0x00c3f300), // JTAG_PREQ_N + _PAD_CFG_STRUCT(GPIO_7, 0x44000402, 0x00c3f300), // JTAG_PRDY_N + _PAD_CFG_STRUCT(GPIO_8, 0x04000300, 0x0003c032), // GPIO + _PAD_CFG_STRUCT(GPIO_9, 0x04000300, 0x0003c033), // GPIO + _PAD_CFG_STRUCT(GPIO_10, 0x04000300, 0x0003c034), // GPIO + _PAD_CFG_STRUCT(GPIO_11, 0x04000300, 0x0003c035), // GPIO + _PAD_CFG_STRUCT(GPIO_12, 0x04000300, 0x0003c036), // GPIO + _PAD_CFG_STRUCT(GPIO_13, 0x44000300, 0x0003c037), // GPIO + _PAD_CFG_STRUCT(GPIO_14, 0x44000300, 0x0003c038), // GPIO + _PAD_CFG_STRUCT(GPIO_15, 0x44000300, 0x0003c039), // GPIO + _PAD_CFG_STRUCT(GPIO_16, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_17, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_18, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_19, 0x42100102, 0x0002733d), // GPIO + _PAD_CFG_STRUCT(GPIO_20, 0x44000300, 0x0003c03e), // GPIO + _PAD_CFG_STRUCT(GPIO_21, 0x44000802, 0x0000303f), // CNV_MFUART2_RXD + _PAD_CFG_STRUCT(GPIO_22, 0x44000800, 0x00027040), // CNV_MFUART2_TXD + _PAD_CFG_STRUCT(GPIO_23, 0x44000802, 0x00003041), // CNV_GNSS_PA_BLANKING + _PAD_CFG_STRUCT(GPIO_24, 0x44000300, 0x0003c042), // GPIO + _PAD_CFG_STRUCT(GPIO_25, 0x44000300, 0x0003c043), // GPIO + _PAD_CFG_STRUCT(GPIO_26, 0x42800102, 0x00027044), // GPIO + _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00003045), // GPIO + _PAD_CFG_STRUCT(GPIO_28, 0x44000201, 0x00003246), // GPIO + _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00023147), // GPIO + _PAD_CFG_STRUCT(GPIO_30, 0x40900102, 0x0003f048), // GPIO + _PAD_CFG_STRUCT(GPIO_31, 0x40800100, 0x0003f049), // GPIO + _PAD_CFG_STRUCT(GPIO_32, 0x44000100, 0x0003d24a), // GPIO + _PAD_CFG_STRUCT(GPIO_33, 0x40900102, 0x0003f04b), // GPIO + _PAD_CFG_STRUCT(GPIO_34, 0x44000201, 0x0003f34c), // GPIO + _PAD_CFG_STRUCT(GPIO_35, 0x44000201, 0x0003f34d), // GPIO + _PAD_CFG_STRUCT(GPIO_36, 0x44000300, 0x0003c34e), // GPIO + _PAD_CFG_STRUCT(GPIO_37, 0x44000300, 0x0003c04f), // GPIO + _PAD_CFG_STRUCT(GPIO_38, 0x42880102, 0x0003f350), // GPIO + _PAD_CFG_STRUCT(GPIO_39, 0x44000201, 0x0003f351), // GPIO + _PAD_CFG_STRUCT(GPIO_40, 0x44000201, 0x0003f352), // GPIO + _PAD_CFG_STRUCT(GPIO_41, 0x44000300, 0x0003c053), // GPIO + _PAD_CFG_STRUCT(GPIO_42, 0x44000700, 0x00001054), // MDSI_A_TE + _PAD_CFG_STRUCT(GPIO_43, 0x44000702, 0x00001055), // MDSI_C_TE + _PAD_CFG_STRUCT(GPIO_44, 0x44000402, 0x00003356), // USB2_OC0_N + _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x00003357), // USB2_OC1_N + _PAD_CFG_STRUCT(GPIO_46, 0x44000300, 0x0003c058), // GPIO + _PAD_CFG_STRUCT(GPIO_47, 0x44000300, 0x0003c059), // GPIO + _PAD_CFG_STRUCT(GPIO_48, 0x44000402, 0x0003e75a), // PMC_I2C_SDA + _PAD_CFG_STRUCT(GPIO_49, 0x44000402, 0x0003e75b), // PMC_I2C_SCL + _PAD_CFG_STRUCT(GPIO_50, 0x44000402, 0x0002275c), // SIO_I2C0_SDA + _PAD_CFG_STRUCT(GPIO_51, 0x44000402, 0x0002275d), // SIO_I2C0_SCL + _PAD_CFG_STRUCT(GPIO_52, 0x44000300, 0x0003c05e), // GPIO + _PAD_CFG_STRUCT(GPIO_53, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_54, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_55, 0x44000300, 0x0003c061), // GPIO + _PAD_CFG_STRUCT(GPIO_56, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_57, 0x44000300, 0x0003c063), // GPIO + _PAD_CFG_STRUCT(GPIO_58, 0x44000402, 0x00022764), // SIO_I2C4_SDA + _PAD_CFG_STRUCT(GPIO_59, 0x44000402, 0x00022765), // SIO_I2C4_SCL + _PAD_CFG_STRUCT(GPIO_60, 0x44000300, 0x0003c066), // GPIO + _PAD_CFG_STRUCT(GPIO_61, 0x44000300, 0x00003067), // GPIO + _PAD_CFG_STRUCT(GPIO_62, 0x46880100, 0x0003c068), // GPIO + _PAD_CFG_STRUCT(GPIO_63, 0x44000300, 0x0003c069), // GPIO + _PAD_CFG_STRUCT(GPIO_64, 0x44000402, 0x0002336a), // SIO_UART2_RXD + _PAD_CFG_STRUCT(GPIO_65, 0x44000400, 0x0002336b), // SIO_UART2_TXD + _PAD_CFG_STRUCT(GPIO_66, 0x44000201, 0x0000336c), // GPIO + _PAD_CFG_STRUCT(GPIO_67, 0x44840102, 0x0002036d), // GPIO + _PAD_CFG_STRUCT(GPIO_68, 0x44000300, 0x0003c06e), // GPIO + _PAD_CFG_STRUCT(GPIO_69, 0x44000300, 0x0003c06f), // GPIO + _PAD_CFG_STRUCT(GPIO_70, 0x44000300, 0x0003c070), // GPIO + _PAD_CFG_STRUCT(GPIO_71, 0x44000300, 0x0003c071), // GPIO + _PAD_CFG_STRUCT(GPIO_72, 0x44000300, 0x0003c072), // GPIO + _PAD_CFG_STRUCT(GPIO_73, 0x44000201, 0x0003f373), // GPIO + _PAD_CFG_STRUCT(GPIO_74, 0x44000400, 0x0003f300), // THERMTRIP_N + _PAD_CFG_STRUCT(GPIO_75, 0x44000702, 0x00003000), // PROCHOT_N +// _PAD_CFG_STRUCT(GPIO_211, 0xffffffff, 0xffffffff), RESERVED + _PAD_CFG_STRUCT(GPIO_212, 0x44000102, 0x0001f375), // GPIO + _PAD_CFG_STRUCT(GPIO_213, 0x44000102, 0x0001d376), // GPIO + _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x0001d377), // GPIO + /* NORTH COMMUNITY GPIOS */ + _PAD_CFG_STRUCT(GPIO_76, 0x44000400, 0x0003c000), // SVID0_ALERT_N + _PAD_CFG_STRUCT(GPIO_77, 0x44000400, 0x0003c000), // SVID0_DATA + _PAD_CFG_STRUCT(GPIO_78, 0x44000400, 0x0003c000), // SVID0_CLK + _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d232), // SIO_SPI_0_CLK + _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d233), // SIO_SPI_0_FS0 + _PAD_CFG_STRUCT(GPIO_81, 0x44000c02, 0x0003d034), // FST_SPI_CS2_N + _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d235), // SIO_SPI_0_RXD + _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x0003d236), // SIO_SPI_0_TXD + _PAD_CFG_STRUCT(GPIO_84, 0x44000100, 0x00001037), // GPIO + _PAD_CFG_STRUCT(GPIO_85, 0x44000300, 0x00001038), // GPIO + _PAD_CFG_STRUCT(GPIO_86, 0x44000300, 0x00001039), // GPIO + _PAD_CFG_STRUCT(GPIO_87, 0x44000300, 0x0003c03a), // GPIO + _PAD_CFG_STRUCT(GPIO_88, 0x44000300, 0x0003c03b), // GPIO + _PAD_CFG_STRUCT(GPIO_89, 0x44000300, 0x0003c03c), // GPIO + _PAD_CFG_STRUCT(GPIO_90, 0x44000502, 0x00003c3d), // FST_SPI_CS0_N + _PAD_CFG_STRUCT(GPIO_91, 0x44000300, 0x0003fc3e), // GPIO + _PAD_CFG_STRUCT(GPIO_92, 0x44000500, 0x00003c3f), // FST_SPI_MOSI_IO + _PAD_CFG_STRUCT(GPIO_93, 0x44000502, 0x00003c40), // FST_SPI_MISO_IO + _PAD_CFG_STRUCT(GPIO_94, 0x44000502, 0x00003c41), // FST_SPI_IO2 + _PAD_CFG_STRUCT(GPIO_95, 0x44000502, 0x00003c42), // FST_SPI_IO3 + _PAD_CFG_STRUCT(GPIO_96, 0x44000500, 0x00003c43), // FST_SPI_CLK + _PAD_CFG_STRUCT(GPIO_97, 0x44000500, 0x00003c00), // FST_SPI_CLK_FB + _PAD_CFG_STRUCT(GPIO_98, 0x44000400, 0x0003c000), // PMU_PLTRST_N + _PAD_CFG_STRUCT(GPIO_99, 0x44000402, 0x0003f300), // PMU_PWRBTN_N + _PAD_CFG_STRUCT(GPIO_100, 0x44000400, 0x0003c000), // PMU_SLP_S0_N + _PAD_CFG_STRUCT(GPIO_101, 0x44000400, 0x0003c000), // PMU_SLP_S3_N + _PAD_CFG_STRUCT(GPIO_102, 0x44000400, 0x0003c000), // PMU_SLP_S4_N + _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003c000), // SUSPWRDNACK + _PAD_CFG_STRUCT(GPIO_104, 0x44000700, 0x00003000), // EMMC_PWR_EN_N + _PAD_CFG_STRUCT(GPIO_105, 0x44000300, 0x0003c344), // GPIO + _PAD_CFG_STRUCT(GPIO_106, 0x44000402, 0x0003f300), // PMU_BATLOW_N + _PAD_CFG_STRUCT(GPIO_107, 0x44000400, 0x0003f300), // PMU_RSTBTN_N + _PAD_CFG_STRUCT(GPIO_108, 0x44000400, 0x0003c000), // PMU_SUSCLK + _PAD_CFG_STRUCT(GPIO_109, 0x44000400, 0x0003c000), // SUS_STAT_N + _PAD_CFG_STRUCT(GPIO_110, 0x44000402, 0x0003e745), // SIO_I2C5_SDA + _PAD_CFG_STRUCT(GPIO_111, 0x44000402, 0x0003e746), // SIO_I2C5_SCL + _PAD_CFG_STRUCT(GPIO_112, 0x44000300, 0x0003c047), // GPIO + _PAD_CFG_STRUCT(GPIO_113, 0x44000300, 0x0003c048), // GPIO + _PAD_CFG_STRUCT(GPIO_114, 0x44000402, 0x00022749), // SIO_I2C7_SDA + _PAD_CFG_STRUCT(GPIO_115, 0x44000402, 0x0002274a), // SIO_I2C7_SCL + _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0003f34b), // PCIE_WAKE0_N + _PAD_CFG_STRUCT(GPIO_117, 0x44000402, 0x0003f34c), // PCIE_WAKE1_N + _PAD_CFG_STRUCT(GPIO_118, 0x44000402, 0x0003f34d), // PCIE_WAKE2_N + _PAD_CFG_STRUCT(GPIO_119, 0x44000300, 0x0003c04e), // GPIO + _PAD_CFG_STRUCT(GPIO_120, 0x44000402, 0x0002334f), // PCIE_CLKREQ0_N + _PAD_CFG_STRUCT(GPIO_121, 0x44000402, 0x00023350), // PCIE_CLKREQ1_N + _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00023351), // PCIE_CLKREQ2_N + _PAD_CFG_STRUCT(GPIO_123, 0x44000300, 0x00020352), // GPIO + _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x0001c353), // DDI0_DDC_SDA + _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x0001c354), // DDI0_DDC_SCL + _PAD_CFG_STRUCT(GPIO_126, 0x44000300, 0x0003c055), // GPIO + _PAD_CFG_STRUCT(GPIO_127, 0x44000300, 0x0003c056), // GPIO + _PAD_CFG_STRUCT(GPIO_128, 0x44000400, 0x00005257), // PNL0_VDDEN + _PAD_CFG_STRUCT(GPIO_129, 0x44000400, 0x00005258), // PNL0_BKLTEN + _PAD_CFG_STRUCT(GPIO_130, 0x44000400, 0x00005259), // PNL0_BKLCTL + _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x0002735a), // DDI0_HPD + _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x0002735b), // DDI1_HPD + _PAD_CFG_STRUCT(GPIO_133, 0x44000400, 0x0002435c), // DDI2_HPD + _PAD_CFG_STRUCT(GPIO_134, 0x44000201, 0x0003f35d), // GPIO + _PAD_CFG_STRUCT(GPIO_135, 0x44000201, 0x0000325e), // GPIO + _PAD_CFG_STRUCT(GPIO_136, 0x44000300, 0x0003c05f), // GPIO + _PAD_CFG_STRUCT(GPIO_137, 0x44000300, 0x0003c060), // GPIO + _PAD_CFG_STRUCT(GPIO_138, 0x44000102, 0x00000061), // GPIO + _PAD_CFG_STRUCT(GPIO_139, 0x44000300, 0x0003c062), // GPIO + _PAD_CFG_STRUCT(GPIO_140, 0x44000100, 0x00001063), // GPIO + _PAD_CFG_STRUCT(GPIO_141, 0x44001400, 0x00020364), // SATA_DEVSLP1 + _PAD_CFG_STRUCT(GPIO_142, 0x44900102, 0x00023365), // GPIO + _PAD_CFG_STRUCT(GPIO_143, 0x44900102, 0x00020066), // GPIO + _PAD_CFG_STRUCT(GPIO_144, 0x44000201, 0x00001067), // GPIO + _PAD_CFG_STRUCT(GPIO_145, 0x44000201, 0x00001068), // GPIO + _PAD_CFG_STRUCT(GPIO_146, 0x44001400, 0x00001069), // n/a + _PAD_CFG_STRUCT(GPIO_147, 0x44000702, 0x0000336a), // LPC_SERIRQ + _PAD_CFG_STRUCT(GPIO_148, 0x44000700, 0x0002006b), // LPC_CLKOUT0 + _PAD_CFG_STRUCT(GPIO_149, 0x44000700, 0x0002006c), // LPC_CLKOUT1 + _PAD_CFG_STRUCT(GPIO_150, 0x44000702, 0x0002336d), // LPC_AD0 + _PAD_CFG_STRUCT(GPIO_151, 0x44000702, 0x0002336e), // LPC_AD1 + _PAD_CFG_STRUCT(GPIO_152, 0x44000702, 0x0002336f), // LPC_AD2 + _PAD_CFG_STRUCT(GPIO_153, 0x44000702, 0x00023370), // LPC_AD3 + _PAD_CFG_STRUCT(GPIO_154, 0x44000702, 0x00003071), // LPC_CLKRUN_N + _PAD_CFG_STRUCT(GPIO_155, 0x44000700, 0x00023372), // LPC_FRAME_N + /* Group Audio GPIOS */ + _PAD_CFG_STRUCT(GPIO_156, 0x42000100, 0x0003d200), // GPIO + _PAD_CFG_STRUCT(GPIO_157, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_158, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_159, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_160, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_161, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_162, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_163, 0x44000201, 0x0003f300), // GPIO + _PAD_CFG_STRUCT(GPIO_164, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_165, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_166, 0x44000400, 0x00021200), // AVS_HDA_BCLK + _PAD_CFG_STRUCT(GPIO_167, 0x44000400, 0x00021200), // AVS_HDA_WS_SYNC + _PAD_CFG_STRUCT(GPIO_168, 0x44000400, 0x00020000), // AVS_HDA_SDI + _PAD_CFG_STRUCT(GPIO_169, 0x44000400, 0x00021200), // AVS_HDA_SDO + _PAD_CFG_STRUCT(GPIO_170, 0x44000402, 0x00021200), // AVS_HDA_RST_N + _PAD_CFG_STRUCT(GPIO_171, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_172, 0x44000100, 0x00001000), // GPIO + _PAD_CFG_STRUCT(GPIO_173, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_174, 0x44000201, 0x00003300), // GPIO + _PAD_CFG_STRUCT(GPIO_175, 0x44000100, 0x00001000), // GPIO + /* Group SCC GPIOS */ + _PAD_CFG_STRUCT(GPIO_176, 0x40800102, 0x0003f000), // GPIO + _PAD_CFG_STRUCT(GPIO_177, 0x44000102, 0x0003c000), // SMB_CLK + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), // SMB_DATA + _PAD_CFG_STRUCT(GPIO_187, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_179, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_180, 0x44000400, 0x00001200), // SDCARD_CLK_FB + _PAD_CFG_STRUCT(GPIO_181, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_182, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_183, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_184, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_185, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_186, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_188, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_210, 0x44000200, 0x0001f200), // GPIO + _PAD_CFG_STRUCT(GPIO_189, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_190, 0x44000300, 0x0003c000), // GPIO + _PAD_CFG_STRUCT(GPIO_191, 0x44000400, 0x0003c000), // CNV_BRI_DT + _PAD_CFG_STRUCT(GPIO_192, 0x44000402, 0x0003f300), // CNV_BRI_RST + _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x0003c000), // CNV_RGI_DT + _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x0003f300), // CNV_RGI_RST + _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x0003c000), // CNV_RF_RESET_N + _PAD_CFG_STRUCT(GPIO_196, 0x44000400, 0x0003c000), // XTAL_CLKREQ + _PAD_CFG_STRUCT(GPIO_197, 0x44000b00, 0x00001200), // n/a + _PAD_CFG_STRUCT(GPIO_198, 0x44000400, 0x0001d200), // EMMC_CLK + _PAD_CFG_STRUCT(GPIO_199, 0x44000500, 0x00001200), // EMMC_D0 + _PAD_CFG_STRUCT(GPIO_200, 0x44000402, 0x00023300), // EMMC_D1 + _PAD_CFG_STRUCT(GPIO_201, 0x44000402, 0x00023300), // EMMC_D2 + _PAD_CFG_STRUCT(GPIO_202, 0x44000402, 0x00023300), // EMMC_D3 + _PAD_CFG_STRUCT(GPIO_203, 0x44000402, 0x00023300), // EMMC_D4 + _PAD_CFG_STRUCT(GPIO_204, 0x44000402, 0x00023300), // EMMC_D5 + _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00023300), // EMMC_D6 + _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00023300), // EMMC_D7 + _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00023300), // EMMC_CMD + _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00023300), // EMMC_RCLK + _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x0001d200), // EMMC_RST_N} }; + const struct pad_config * __weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); @@ -246,8 +252,8 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_177, UP_20K, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_178, UP_20K, DEEP, NF1), /* SMB_DATA */ + _PAD_CFG_STRUCT(GPIO_177, 0x44000102, 0x0003c000), /* SMB_CLK */ + _PAD_CFG_STRUCT(GPIO_178, 0x44000300, 0x0003c000), /* SMB_DATA */ }; const struct pad_config * __weak diff --git a/src/mainboard/microtech/etabpro/memory.c b/src/mainboard/microtech/etabpro/memory.c index 2a4c43e..f74b29f 100644 --- a/src/mainboard/microtech/etabpro/memory.c +++ b/src/mainboard/microtech/etabpro/memory.c @@ -124,6 +124,18 @@ .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "H9HCNNN8KUMLHR", }, + /* 123456789012345678 - both logical channels */ + [6] = { + .speed = LP4_SPEED_2133, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "123456789012345678", + }, + [7] = { + .speed = LP4_SPEED_2133, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + }, }; static const struct lpddr4_cfg lp4cfg = { -- To view, visit https://review.coreboot.org/c/coreboot/+/40353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I154cb9abeba3e27cbb16acfd35012a996f099a92 Gerrit-Change-Number: 40353 Gerrit-PatchSet: 1 Gerrit-Owner: Miroslaw Kocur <mirek190(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x/elog.c: add missing power button events
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40346 ) Change subject: sb/intel/bd82x6x/elog.c: add missing power button events ...................................................................... sb/intel/bd82x6x/elog.c: add missing power button events Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I233575751c375172ac9dced10b6c13acc33e0445 --- M src/southbridge/intel/bd82x6x/elog.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/40346/1 diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index dc5da79..99e3d9c 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -52,6 +52,10 @@ if (pm1_sts & (1 << 11)) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + /* Power Button */ + if (pm1_sts & (1 << 8)) + elog_add_event(ELOG_TYPE_POWER_BUTTON); + /* System Reset Status (reset button pushed) */ if (gen_pmcon_2 & (1 << 4)) elog_add_event(ELOG_TYPE_RESET_BUTTON); @@ -69,6 +73,9 @@ * Wake sources */ + /* Power Button */ + if (pm1_sts & (1 << 8)) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); /* RTC */ if (pm1_sts & (1 << 10)) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/40346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I233575751c375172ac9dced10b6c13acc33e0445 Gerrit-Change-Number: 40346 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/mb/asus: Add H110M-E/M.2 Documentation
by Pavel Sayekat (Code Review) 10 Jun '23

10 Jun '23

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35011 ) Change subject: Doc/mb/asus: Add H110M-E/M.2 Documentation ...................................................................... Doc/mb/asus: Add H110M-E/M.2 Documentation Followed and adapted from the ASRock H110M-DVS Documentation Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b --- A Documentation/mainboard/asus/h110m-e_m2.md 1 file changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35011/1 diff --git a/Documentation/mainboard/asus/h110m-e_m2.md b/Documentation/mainboard/asus/h110m-e_m2.md new file mode 100644 index 0000000..134dca8 --- /dev/null +++ b/Documentation/mainboard/asus/h110m-e_m2.md @@ -0,0 +1,136 @@ +# ASUS H110M-E/M.2 + +This page describes how to run coreboot on the [ASUS H110M-E/M.2]. + +## Required proprietary blobs + +Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. +Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md) +(intel FSP 2.0) to initialize this generation silicon. Please see this +[document](../../soc/intel/code_development_model/code_development_model.md). + +FSP Information: + +```eval_rst ++-----------------------------+-------------------+-------------------+ +| FSP Project Name | Directory | Specification | ++-----------------------------+-------------------+-------------------+ +| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 | +| processors and chipsets | | | +| (formerly Kaby Lake) | | | ++-----------------------------+-------------------+-------------------+ +``` + +## Building coreboot + +The following steps set the default parameters for this board to build a +fully working image: + +```bash +make distclean +touch .config +./util/scripts/config --enable VENDOR_ASUS +./util/scripts/config --enable BOARD_ASUS_H110M_E_M2 +./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES +./util/scripts/config --enable CONFIG_FSP_USE_REPO +./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" +make olddefconfig +``` + +However, it is strongly advised to use `make menuconfig` afterwards +(or instead), so that you can see all of the settings. + +Use the following command to disable the serial console if debugging +output is not required: + +```bash +./util/scripts/config --disable CONSOLE_SERIAL +``` + +However, a more flexible method is to change the console log level from +within an OS using `util/nvramtool`, or with the `nvramcui` payload. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region, such as the Management Engine or firmware descriptor, then +an external programmer is required (unless you find a clever way around +the flash protection). More information about this [here](../../flash_tutorial/index.md). + +### External programming + +The flash chip is a 16 MiB socketed DIP-8 chip. Specifically, it's a +GIgaDevice GD25B128CPIG, whose datasheet can be found [here][GD25B128CPIG]. +The chip is located to the bottom right-hand side of the board. For +a precise location, refer to section 1.3 (Motherboard Layout) of the +[H110M-E/M.2 manual], where the chip is labelled "128Mb BIOS". Take note of +the chip's orientation, remove it from its socket, and flash it with +an external programmer. For reference, the notch in the chip should be +facing towards the bottom of the board. + +## Known issues + +- The VGA port doesn't work. Discrete graphic card is used as primary + device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not + set). Dynamic switching between iGPU and PEG is not yet supported. + +- SuperIO GPIO pin is used to reset Realtek chip. However, since the + Logical Device 7 (GPIO7, GPIO8) is not initialized, the network + chip is in a reset state all the time. + +## Untested + +- parallel port +- PS/2 keyboard +- PS/2 mouse +- EHCI debug +- TPM +- infrared module +- chassis intrusion header +- chassis speaker header + +## Working + +- integrated graphics init with libgfxinit (see [Known issues](#known-issues)) +- PCIe x1 +- PEG x16 Gen3 +- SATA +- USB +- serial port +- onboard audio +- using `me_cleaner` +- using `flashrom` + +## TODO + +- NCT5539D GPIOs +- onboard network (see [Known issues](#known-issues)) +- S3 suspend/resume +- Wake-on-LAN +- hardware monitor + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Skylake/Kaby Lake (LGA1151) | ++------------------+--------------------------------------------------+ +| PCH | Intel Sunrise Point H110 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT5539D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[ASUS H110M-E/M.2]: https://www.asus.com/Motherboards/H110M-E-M-2/overview/ +[GD25B128CPIG]: https://www.gigadevice.com/datasheet/gd25b127d/ [The closest match found] +[flashrom]: https://flashrom.org/Flashrom +[ASUS H110M-E/M.2 manual]: https://dlcdnets.asus.com/pub/ASUS/mb/LGA1151/H110M-E_M2/E11622_H110M-E_M2_… -- To view, visit https://review.coreboot.org/c/coreboot/+/35011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c5aad50b513935eab70b502df1d95fb3413fa6b Gerrit-Change-Number: 35011 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

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Change in coreboot[master]: include/elog.h: add intruder detection event codes
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40342 ) Change subject: include/elog.h: add intruder detection event codes ...................................................................... include/elog.h: add intruder detection event codes Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I3a1cd17bb7e12271adef0ef3d505509f25d4c87a --- M src/include/elog.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40342/1 diff --git a/src/include/elog.h b/src/include/elog.h index 68a4842..5a7632d 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -195,6 +195,11 @@ /* Cr50 reset to enable TPM */ #define ELOG_TYPE_CR50_NEED_RESET 0xb2 +/* Intruder detection */ +#define ELOG_TYPE_INTRUDER_DETECTION 0xb3 +#define ELOG_CASE_OPENED 0x01 +#define ELOG_CASE_CLOSED 0x02 + struct elog_event_extended_event { u8 event_type; u32 event_complement; -- To view, visit https://review.coreboot.org/c/coreboot/+/40342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a1cd17bb7e12271adef0ef3d505509f25d4c87a Gerrit-Change-Number: 40342 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: commonlib/elog: Add missing PCI Express PME sources
by Michał Żygowski (Code Review) 10 Jun '23

10 Jun '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40417 ) Change subject: commonlib/elog: Add missing PCI Express PME sources ...................................................................... commonlib/elog: Add missing PCI Express PME sources Intel Skylake SoC defines more than 12 PCI Express wake sources. However, these wake sources are not defined anywhere. Without these definitions the coreboot build for Skylake or Kaby Lake board fails when event log is enabled. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc --- M src/commonlib/include/commonlib/elog.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/40417/1 diff --git a/src/commonlib/include/commonlib/elog.h b/src/commonlib/include/commonlib/elog.h index 3b84242..c9b0c3e 100644 --- a/src/commonlib/include/commonlib/elog.h +++ b/src/commonlib/include/commonlib/elog.h @@ -166,6 +166,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b struct elog_event_data_wake { uint8_t source; @@ -383,6 +395,18 @@ { ELOG_WAKE_SOURCE_PME_PCIE10, "PCI Express 10 PME" }, { ELOG_WAKE_SOURCE_PME_PCIE11, "PCI Express 11 PME" }, { ELOG_WAKE_SOURCE_PME_PCIE12, "PCI Express 12 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE13, "PCI Express 13 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE14, "PCI Express 14 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE15, "PCI Express 15 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE16, "PCI Express 16 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE17, "PCI Express 17 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE18, "PCI Express 18 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE19, "PCI Express 19 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE20, "PCI Express 20 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE21, "PCI Express 21 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE22, "PCI Express 22 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE23, "PCI Express 23 PME" }, + { ELOG_WAKE_SOURCE_PME_PCIE24, "PCI Express 24 PME" }, { ELOG_WAKE_SOURCE_PME_SATA, "SATA PME" }, { ELOG_WAKE_SOURCE_PME_CSE, "CSE PME" }, { ELOG_WAKE_SOURCE_PME_CSE2, "CSE 2 PME" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/40417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie60a232104d8947d86de5add150f12ba7c03b0cc Gerrit-Change-Number: 40417 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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