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Change in coreboot[master]: mb/asrock/e350m1: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46154 ) Change subject: mb/asrock/e350m1: Convert to ASL 2.0 syntax ...................................................................... mb/asrock/e350m1: Convert to ASL 2.0 syntax Change-Id: Ief7ea77f8081cd6b7fb18fbf1d25c7394daca07d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/e350m1/acpi/mainboard.asl M src/mainboard/asrock/e350m1/acpi/sata.asl M src/mainboard/asrock/e350m1/acpi/sleep.asl M src/mainboard/asrock/e350m1/acpi/usb_oc.asl 4 files changed, 75 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46154/1 diff --git a/src/mainboard/asrock/e350m1/acpi/mainboard.asl b/src/mainboard/asrock/e350m1/acpi/mainboard.asl index 9283191..5c0929a 100644 --- a/src/mainboard/asrock/e350m1/acpi/mainboard.asl +++ b/src/mainboard/asrock/e350m1/acpi/mainboard.asl @@ -18,20 +18,20 @@ Scope(\_SB) { Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if(CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } Return(OSVR) diff --git a/src/mainboard/asrock/e350m1/acpi/sata.asl b/src/mainboard/asrock/e350m1/acpi/sata.asl index 7f305fb..6d9ff03 100644 --- a/src/mainboard/asrock/e350m1/acpi/sata.asl +++ b/src/mainboard/asrock/e350m1/acpi/sata.asl @@ -35,7 +35,7 @@ Device(PMST) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P0IS,0)) { + if (P0IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -48,7 +48,7 @@ { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P1IS,0)) { + if (P1IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -71,7 +71,7 @@ { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P2IS,0)) { + if (P2IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -84,7 +84,7 @@ { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P3IS,0)) { + if (P3IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -98,35 +98,35 @@ Scope(\_GPE) { Method(_L1F,0x0,NotSerialized) { if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { + if (\_SB.P0IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) + \_SB.P0PR = 1 } if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { + if (\_SB.P1IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) + \_SB.P1PR = 1 } if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { + if (\_SB.P2IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) + \_SB.P2PR = 1 } if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { + if (\_SB.P3IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) + \_SB.P3PR = 1 } } } diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl index 76b5f9e..3b6fd02 100644 --- a/src/mainboard/asrock/e350m1/acpi/sleep.asl +++ b/src/mainboard/asrock/e350m1/acpi/sleep.asl @@ -26,23 +26,23 @@ /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) + if (Arg0 == 3){ + URRE = 0 } /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 } /* End Method(\_PTS) */ /* @@ -67,21 +67,21 @@ /* DBGO(" to S0\n") */ /* Re-enable HPET */ - Store(1,HPDE) + HPDE = 1 /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) + if (Arg0 == 3){ + URRE = 1 } /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) + Local1 = PWST + PWST = Local1 - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) + /* if (DeRefOf(WKST [0])) { + * WKST [1] = 0 * } else { - * Store(Arg0, Index(WKST,1)) + * WKST [1] = Arg0 * } */ Return(WKST) diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl index 4ecc52a..e4ed275 100644 --- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl +++ b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl @@ -14,134 +14,134 @@ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) + CMTI = 0x13 + GPSL = 0 } /* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { +If (UOM0 <= 9) { Scope (\_GPE) { Method (_L13) { UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + if (GPB0 == PLC0) { + PLC0 = ~PLC0 + \_SB.PT0D = PLC0 } } } } /* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { +If (UOM1 <= 9) { Scope (\_GPE) { Method (_L14) { UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + if (GPB1 == PLC1) { + PLC1 = ~PLC1 + \_SB.PT1D = PLC1 } } } } /* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { +If (UOM2 <= 9) { Scope (\_GPE) { Method (_L15) { UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + if (GPB2 == PLC2) { + PLC2 = ~PLC2 + \_SB.PT2D = PLC2 } } } } /* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { +If (UOM3 <= 9) { Scope (\_GPE) { Method (_L16) { UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + if (GPB3 == PLC3) { + PLC3 = ~PLC3 + \_SB.PT3D = PLC3 } } } } /* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { +If (UOM4 <= 9) { Scope (\_GPE) { Method (_L19) { UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + if (GPB4 == PLC4) { + PLC4 = ~PLC4 + \_SB.PT4D = PLC4 } } } } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { +If (UOM5 <= 9) { Scope (\_GPE) { Method (_L1A) { UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + if (GPB5 == PLC5) { + PLC5 = ~PLC5 + \_SB.PT5D = PLC5 } } } } /* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { +If (UOM6 <= 9) { Scope (\_GPE) { /* Method (_L1C) { */ Method (_L06) { UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + if (GPB6 == PLC6) { + PLC6 = ~PLC6 + \_SB.PT6D = PLC6 } } } } /* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { +If (UOM7 <= 9) { Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + if (GPB7 == PLC7) { + PLC7 = ~PLC7 + \_SB.PT7D = PLC7 } } } } /* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { +If (UOM8 <= 9) { Scope (\_GPE) { Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + if (G8IS == PLC8) { + PLC8 = ~PLC8 + \_SB.PT8D = PLC8 } } } } /* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { +If (UOM9 <= 9) { Scope (\_GPE) { Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + if (G9IS == 0) { + \_SB.PT9D = 1 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7ea77f8081cd6b7fb18fbf1d25c7394daca07d Gerrit-Change-Number: 46154 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp/abm: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46164 ) Change subject: mb/hp/abm: Convert to ASL 2.0 syntax ...................................................................... mb/hp/abm: Convert to ASL 2.0 syntax Change-Id: Ie93dd1f6de1357cb3f448ed79a33b688abd91731 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/abm/acpi/sleep.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46164/1 diff --git a/src/mainboard/hp/abm/acpi/sleep.asl b/src/mainboard/hp/abm/acpi/sleep.asl index 47dd146..fc26c30 100644 --- a/src/mainboard/hp/abm/acpi/sleep.asl +++ b/src/mainboard/hp/abm/acpi/sleep.asl @@ -30,9 +30,9 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -56,7 +56,7 @@ /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ - Store(1,USBS) + USBS = 1 \_SB.AWAK(Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93dd1f6de1357cb3f448ed79a33b688abd91731 Gerrit-Change-Number: 46164 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/imb-a180: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46155 ) Change subject: mb/asrock/imb-a180: Convert to ASL 2.0 syntax ...................................................................... mb/asrock/imb-a180: Convert to ASL 2.0 syntax Change-Id: I100b6c596d8a1dd74f096f71675026618da32e6f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/imb-a180/acpi/sleep.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46155/1 diff --git a/src/mainboard/asrock/imb-a180/acpi/sleep.asl b/src/mainboard/asrock/imb-a180/acpi/sleep.asl index 47dd146..fc26c30 100644 --- a/src/mainboard/asrock/imb-a180/acpi/sleep.asl +++ b/src/mainboard/asrock/imb-a180/acpi/sleep.asl @@ -30,9 +30,9 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 \_SB.APTS(Arg0) } /* End Method(\_PTS) */ @@ -56,7 +56,7 @@ /* DBGO("From S") */ /* DBGO(Arg0) */ /* DBGO(" to S0\n") */ - Store(1,USBS) + USBS = 1 \_SB.AWAK(Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/46155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I100b6c596d8a1dd74f096f71675026618da32e6f Gerrit-Change-Number: 46155 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/thatcher: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46152 ) Change subject: mb/amd/thatcher: Convert to ASL 2.0 syntax ...................................................................... mb/amd/thatcher: Convert to ASL 2.0 syntax Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/thatcher/acpi/sleep.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46152/1 diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl index af87ce6..e09a638 100644 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ b/src/mainboard/amd/thatcher/acpi/sleep.asl @@ -26,20 +26,20 @@ /* DBGO("\n") */ /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 - Store (0x07, UPWS) + UPWS = 0x07 } /* End Method(\_PTS) */ /* @@ -64,6 +64,6 @@ /* DBGO(" to S0\n") */ /* clear USB wake up signal */ - Store(1, USBS) + USBS = 1 Return(WKST) } /* End Method(\_WAK) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8 Gerrit-Change-Number: 46152 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/parmer: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46149 ) Change subject: mb/amd/parmer: Convert to ASL 2.0 syntax ...................................................................... mb/amd/parmer: Convert to ASL 2.0 syntax Change-Id: I563cd549858429049223677ebc503f9c9304baa0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/parmer/acpi/sleep.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46149/1 diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl index dde9c37..cd714ce 100644 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ b/src/mainboard/amd/parmer/acpi/sleep.asl @@ -26,20 +26,20 @@ /* DBGO("\n") */ /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 - Store (0x07, UPWS) + UPWS = 0x07 } /* End Method(\_PTS) */ /* @@ -64,7 +64,7 @@ /* DBGO(" to S0\n") */ /* Re-enable HPET */ - Store(1,USBS) + USBS = 1 Return(WKST) } /* End Method(\_WAK) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I563cd549858429049223677ebc503f9c9304baa0 Gerrit-Change-Number: 46149 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/padmelon: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46148 ) Change subject: mb/amd/padmelon: Convert to ASL 2.0 syntax ...................................................................... mb/amd/padmelon: Convert to ASL 2.0 syntax Change-Id: I88c1c907916c3de51f6b3b72f7a49e90a1b1a383 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/padmelon/acpi/sleep.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/46148/1 diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl index 89c6fa1..0cbf8e3 100644 --- a/src/mainboard/amd/padmelon/acpi/sleep.asl +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -26,10 +26,10 @@ /* DBGO("\n") */ /* Clear wake status structure. */ - Store(0, PEWD) - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - Store(7, UPWS) + PEWD = 0 + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 } /* End Method(\_PTS) */ /* -- To view, visit https://review.coreboot.org/c/coreboot/+/46148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c1c907916c3de51f6b3b72f7a49e90a1b1a383 Gerrit-Change-Number: 46148 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/biostar: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46076 ) Change subject: mb/biostar: Convert to ASL 2.0 syntax ...................................................................... mb/biostar: Convert to ASL 2.0 syntax Change-Id: I122f27bf7e7b809802efdbd443694b3d6e715108 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl M src/mainboard/biostar/am1ml/acpi/sio.asl 2 files changed, 56 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46076/1 diff --git a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl index a04e298..5ac667d 100644 --- a/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl +++ b/src/mainboard/biostar/a68n_5200/acpi/AmdImc.asl @@ -19,9 +19,9 @@ Method(WACK, 0) { - Store(0, Local0) - While (LNotEqual(Local0, 0xFA)) { - Store(MRG0, Local0) + Local0 = 0 + While (Local0 != 0xFA) { + Local0 = MRG0 Sleep(10) } } @@ -29,69 +29,69 @@ //Init Method (ITZE, 0) { - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) + MRG0 = 0 + MRG1 = 0xB5 + MRG2 = 0 + MSTI = 0x96 WACK() - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 WACK() - Or(MRG2, 0x01, Local0) + Local0 = MRG2 | 0x01 - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 WACK() } //Sleep Method (IMSP, 0) { - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) + MRG0 = 0 + MRG1 = 0xB5 + MRG2 = 0 + MSTI = 0x96 WACK() - Store(0, MRG0) - Store(1, MRG1) - Store(0, MRG2) - Store(0x98, MSTI) + MRG0 = 0 + MRG1 = 1 + MRG2 = 0 + MSTI = 0x98 WACK() - Store(0, MRG0) - Store(0xB4, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) + MRG0 = 0 + MRG1 = 0xB4 + MRG2 = 0 + MSTI = 0x96 WACK() } //Wake Method (IMWK, 0) { - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) + MRG0 = 0 + MRG1 = 0xB5 + MRG2 = 0 + MSTI = 0x96 WACK() - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 WACK() - Or(MRG2, 0x01, Local0) + Local0 = MRG2 | 0x01 - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 WACK() } diff --git a/src/mainboard/biostar/am1ml/acpi/sio.asl b/src/mainboard/biostar/am1ml/acpi/sio.asl index ef0bca5..bf4ff3d 100644 --- a/src/mainboard/biostar/am1ml/acpi/sio.asl +++ b/src/mainboard/biostar/am1ml/acpi/sio.asl @@ -26,17 +26,17 @@ /* Enter the 8728 Config */ Method (EPNP) { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) + SIOI = 0x87 + SIOI = 0x01 + SIOI = 0x55 + SIOI = 0x55 } /* Exit the 8728 Config */ Method (XPNP) { - Store (0x02, SIOI) - Store (0x02, SIOD) + SIOI = 0x02 + SIOD = 0x02 } /* @@ -46,20 +46,20 @@ Method (SIOS, 1) { /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) + If (Arg0 < 0x05) { EPNP() /* DBGO("8728F\n") */ - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ + LDN = 0x4 + ACTR = 1 /* Enable EC */ /* - Store (0x4, LDN) - Store (0x04, APC4) + LDN = 0x4 + APC4 = 0x04 */ /* falling edge. which mode? Not sure. */ - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + LDN = 0x4 + APC1 = 0x08 /* clear PME status, Use 0x18 for mouse & KBD */ + LDN = 0x4 + APC0 = 0x08 /* enable PME, Use 0x18 for mouse & KBD */ XPNP() } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I122f27bf7e7b809802efdbd443694b3d6e715108 Gerrit-Change-Number: 46076 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 10

Change in coreboot[master]: mb/elmex/pcm205400: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 28 Jan '21

28 Jan '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46162 ) Change subject: mb/elmex/pcm205400: Convert to ASL 2.0 syntax ...................................................................... mb/elmex/pcm205400: Convert to ASL 2.0 syntax Change-Id: I1cec4049adac74270641736709774156628b2539 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/elmex/pcm205400/acpi/ide.asl M src/mainboard/elmex/pcm205400/acpi/mainboard.asl M src/mainboard/elmex/pcm205400/acpi/sata.asl M src/mainboard/elmex/pcm205400/acpi/sleep.asl M src/mainboard/elmex/pcm205400/acpi/usb_oc.asl 5 files changed, 130 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46162/1 diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl index 663b36a..e3a1bec 100644 --- a/src/mainboard/elmex/pcm205400/acpi/ide.asl +++ b/src/mainboard/elmex/pcm205400/acpi/ide.asl @@ -50,11 +50,11 @@ Method(GTTM, 1) /* get total time*/ { - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) + Local0 = Arg0 & 0x0F /* Recovery Width */ + Local0++ + Local1 = Arg0 >> 4 /* Command Width */ + Local1++ + Return(30 * (Local0 + Local1)) } Device(PRID) @@ -76,30 +76,30 @@ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ + If (PPCR & 0x01) { /* primary PIO control */ Return(OTBF) } /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) + BFFG |= 0x1A - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing to PIO spd0 */ + PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing to PIO spd1 */ - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) + If (PDCR & 0x01) { /* It's under UDMA mode */ + BFFG |= 0x01 + DSD0 = DerefOf(UDTT [PDMM]) } Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing, DmaSpd0 */ } - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) + If (PDCR & 0x02) { /* It's under UDMA mode */ + BFFG |= 0x04 + DSD1 = DerefOf(UDTT [PDSM]) } Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing, DmaSpd0 */ } Return(OTBF) /* out buffer */ @@ -120,35 +120,35 @@ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0) + PPMM = Local0 % 5 /* Primary PIO master Mode */ + Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0) + PPSM = Local1 % 5 /* Primary PIO slave Mode */ - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */ + PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */ - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) + If (BFFG & 0x01) { /* Drive 0 is under UDMA mode */ + Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0) + PDMM = Local0 % 7 + PDCR |= 0x01 } Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) + If (DSD0 != 0xFFFFFFFF) { + Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0) + PMTM = DerefOf(MDRT [Local0]) } } - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) + If (BFFG & 0x04) { /* Drive 1 is under UDMA mode */ + Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0) + PDSM = Local0 % 7 + PDCR |= 0x02 } Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) + If (DSD1 != 0xFFFFFFFF) { + Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0) + PMTS = DerefOf(MDRT [Local0]) } } /* Return(INBF) */ @@ -168,21 +168,19 @@ CreateByteField(CMBF, 12, CMDB) CreateByteField(CMBF, 19, CMDC) - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) + CMDA = 0xA0 + CMDB = 0xA0 + CMDC = 0xA0 - Or(PPMM, 0x08, POMD) + POMD = PPMM | 0x08 - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) + If (PDCR & 0x01) { + DMMD = PDMM | 0x40 } Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) + Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0) + If (Local0 < 3) { + DMMD = Local0 | 0x20 } } Return(CMBF) @@ -204,21 +202,19 @@ CreateByteField(CMBF, 12, CMDB) CreateByteField(CMBF, 19, CMDC) - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) + CMDA = 0xB0 + CMDB = 0xB0 + CMDC = 0xB0 - Or(PPSM, 0x08, POMD) + POMD = PPSM | 0x08 - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) + If (PDCR & 0x02) { + DMMD = PDSM | 0x40 } Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) + Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0) + If (Local0 < 3) { + DMMD = Local0 | 0x20 } } Return(CMBF) diff --git a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl index 9283191..5c0929a 100644 --- a/src/mainboard/elmex/pcm205400/acpi/mainboard.asl +++ b/src/mainboard/elmex/pcm205400/acpi/mainboard.asl @@ -18,20 +18,20 @@ Scope(\_SB) { Method(OSFL, 0){ - if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */ if(CondRefOf(\_OSI)) { - Store(1, OSVR) /* Assume some form of XP */ + OSVR = 1 /* Assume some form of XP */ if (\_OSI("Windows 2006")) /* Vista */ { - Store(2, OSVR) + OSVR = 2 } } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSVR) /* Linux */ + If (WCMP(\_OS,"Linux")) { + OSVR = 3 /* Linux */ } Else { - Store(4, OSVR) /* Gotta be WinCE */ + OSVR = 4 /* Gotta be WinCE */ } } Return(OSVR) diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl index 7f305fb..6d9ff03 100644 --- a/src/mainboard/elmex/pcm205400/acpi/sata.asl +++ b/src/mainboard/elmex/pcm205400/acpi/sata.asl @@ -35,7 +35,7 @@ Device(PMST) { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P0IS,0)) { + if (P0IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -48,7 +48,7 @@ { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P1IS,0)) { + if (P1IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -71,7 +71,7 @@ { Name(_ADR, 0) Method(_STA,0) { - if (LGreater(P2IS,0)) { + if (P2IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -84,7 +84,7 @@ { Name(_ADR, 1) Method(_STA,0) { - if (LGreater(P3IS,0)) { + if (P3IS > 0) { return (0x0F) /* sata is visible */ } else { @@ -98,35 +98,35 @@ Scope(\_GPE) { Method(_L1F,0x0,NotSerialized) { if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { + if (\_SB.P0IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) + \_SB.P0PR = 1 } if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { + if (\_SB.P1IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) + \_SB.P1PR = 1 } if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { + if (\_SB.P2IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) + \_SB.P2PR = 1 } if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { + if (\_SB.P3IS > 0) { sleep(32) } Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) + \_SB.P3PR = 1 } } } diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl index 76b5f9e..3b6fd02 100644 --- a/src/mainboard/elmex/pcm205400/acpi/sleep.asl +++ b/src/mainboard/elmex/pcm205400/acpi/sleep.asl @@ -26,23 +26,23 @@ /* DBGO("\n") */ /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) + if (Arg0 == 3){ + URRE = 0 } /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ + /*CSSM = 1 + SSEN = 1*/ /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + /*if (\_SB.SBRI <= 0x13) { + * \_SB.PWDE = 0 *} */ /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) + WKST [0] = 0 + WKST [1] = 0 } /* End Method(\_PTS) */ /* @@ -67,21 +67,21 @@ /* DBGO(" to S0\n") */ /* Re-enable HPET */ - Store(1,HPDE) + HPDE = 1 /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) + if (Arg0 == 3){ + URRE = 1 } /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, Local1) - Store(Local1, PWST) + Local1 = PWST + PWST = Local1 - /* if (DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) + /* if (DeRefOf(WKST [0])) { + * WKST [1] = 0 * } else { - * Store(Arg0, Index(WKST,1)) + * WKST [1] = Arg0 * } */ Return(WKST) diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl index 4ecc52a..e4ed275 100644 --- a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl +++ b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl @@ -14,134 +14,134 @@ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) + CMTI = 0x13 + GPSL = 0 } /* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { +If (UOM0 <= 9) { Scope (\_GPE) { Method (_L13) { UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + if (GPB0 == PLC0) { + PLC0 = ~PLC0 + \_SB.PT0D = PLC0 } } } } /* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { +If (UOM1 <= 9) { Scope (\_GPE) { Method (_L14) { UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + if (GPB1 == PLC1) { + PLC1 = ~PLC1 + \_SB.PT1D = PLC1 } } } } /* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { +If (UOM2 <= 9) { Scope (\_GPE) { Method (_L15) { UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + if (GPB2 == PLC2) { + PLC2 = ~PLC2 + \_SB.PT2D = PLC2 } } } } /* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { +If (UOM3 <= 9) { Scope (\_GPE) { Method (_L16) { UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + if (GPB3 == PLC3) { + PLC3 = ~PLC3 + \_SB.PT3D = PLC3 } } } } /* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { +If (UOM4 <= 9) { Scope (\_GPE) { Method (_L19) { UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + if (GPB4 == PLC4) { + PLC4 = ~PLC4 + \_SB.PT4D = PLC4 } } } } /* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { +If (UOM5 <= 9) { Scope (\_GPE) { Method (_L1A) { UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + if (GPB5 == PLC5) { + PLC5 = ~PLC5 + \_SB.PT5D = PLC5 } } } } /* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { +If (UOM6 <= 9) { Scope (\_GPE) { /* Method (_L1C) { */ Method (_L06) { UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + if (GPB6 == PLC6) { + PLC6 = ~PLC6 + \_SB.PT6D = PLC6 } } } } /* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { +If (UOM7 <= 9) { Scope (\_GPE) { /* Method (_L1D) { */ Method (_L07) { UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + if (GPB7 == PLC7) { + PLC7 = ~PLC7 + \_SB.PT7D = PLC7 } } } } /* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { +If (UOM8 <= 9) { Scope (\_GPE) { Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + if (G8IS == PLC8) { + PLC8 = ~PLC8 + \_SB.PT8D = PLC8 } } } } /* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { +If (UOM9 <= 9) { Scope (\_GPE) { Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + if (G9IS == 0) { + \_SB.PT9D = 1 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cec4049adac74270641736709774156628b2539 Gerrit-Change-Number: 46162 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel/broadwell: Clean up cosmetics
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47024 ) Change subject: soc/intel/broadwell: Clean up cosmetics ...................................................................... soc/intel/broadwell: Clean up cosmetics To ease merging with Lynxpoint, define the port mask. Also simplify several register operations and drop outdated `Set timings` comment. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I6fd5516b33fe4c3d7099651ec452359030b8d509 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 16 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47024/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index f63d4ba..3ed136b 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -13,6 +13,8 @@ #include "rcba.h" #include "sata.h" +#define SATA_PORT_MASK 0x0f + static inline u32 sir_read(struct device *dev, int idx) { pci_write_config32(dev, SATA_SIRI, idx); @@ -43,13 +45,12 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); - /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0xf; + reg16 &= ~SATA_PORT_MASK; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); udelay(2); @@ -61,13 +62,12 @@ reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ pci_write_config32(dev, 0x98, reg32); - /* Setup register 9Ch */ - reg16 = (1 << 5); /* BWG step 12 */ - pci_write_config16(dev, 0x9c, reg16); + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5); /* SATA Initialization register */ reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0xf) << 24; + reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32); @@ -95,7 +95,7 @@ } else { /* Enable DEVSLP */ reg32 = read32(abar + 0x24); - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + reg32 |= (1 << 5) | (1 << 4)|(1 << 3)|(1 << 2); write32(abar + 0x24, reg32); for (port = 0; port < 4; port++) { @@ -112,10 +112,10 @@ */ reg32 = RCBA32(0x3a84); /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) + if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) reg32 |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) + if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) reg32 |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = reg32; @@ -239,29 +239,22 @@ reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); - reg32 = pci_read_config32(dev, 0x98); - reg32 |= 1 << 29; - pci_write_config32(dev, 0x98, reg32); + pci_or_config32(dev, 0x98, 1 << 29); /* Register Lock */ - reg32 = pci_read_config32(dev, 0x9c); - reg32 |= (1 << 31); - pci_write_config32(dev, 0x9c, reg32); + pci_or_config32(dev, 0x9c, 1 << 31); } -/* - * Set SATA controller mode early so the resource allocator can - * properly assign IO/Memory resources for the controller. - */ static void sata_enable(struct device *dev) { /* Get the chip configuration */ const struct soc_intel_broadwell_pch_config *config = config_of(dev); - u16 map = 0x0060; - map |= (config->sata_port_map ^ 0xf) << 8; - - pci_write_config16(dev, 0x90, map); + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8); } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd5516b33fe4c3d7099651ec452359030b8d509 Gerrit-Change-Number: 47024 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell: Align memmap.h with Haswell
by Angel Pons (Code Review) 28 Jan '21

28 Jan '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46956 ) Change subject: soc/intel/broadwell: Align memmap.h with Haswell ...................................................................... soc/intel/broadwell: Align memmap.h with Haswell This is merely to reduce cosmetic differences. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I473336a77179a3d1d26933f481abded49e9f0864 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/acpi/hostbridge.asl M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.h M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/acpi/gpio.asl M src/soc/intel/broadwell/pch/acpi/lpc.asl M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/broadwell/pch/gpio.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pm.h M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/rcba.h M src/soc/intel/broadwell/pch/smbus.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pei_data.c 21 files changed, 82 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46956/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index fc41259..db9aced 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -27,7 +27,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - MCFG_BASE_ADDRESS, 0, 0, 255); + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); return current; } diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index b18ec78..d4f6a1b 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,7 +9,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 607178c..8b63ec7 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -174,11 +174,11 @@ Name (_UID, 1) Name (PDRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE) - Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE) - Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE) - Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x4000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x8000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x1000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x1000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) }) diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c index af5ba14..31786f3 100644 --- a/src/soc/intel/broadwell/early_init.c +++ b/src/soc/intel/broadwell/early_init.c @@ -11,9 +11,9 @@ static void broadwell_setup_bars(void) { /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, MCHBAR, MCH_BASE_ADDRESS | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR, DMI_BASE_ADDRESS | 1); - pci_write_config32(HOST_BRIDGE, EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h index dfce0fd..df3a7550 100644 --- a/src/soc/intel/broadwell/haswell.h +++ b/src/soc/intel/broadwell/haswell.h @@ -85,9 +85,9 @@ /* MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + (x))) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + (x))) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + (x))) /* Memory controller characteristics */ #define NUM_CHANNELS 2 diff --git a/src/soc/intel/broadwell/memmap.h b/src/soc/intel/broadwell/memmap.h index 241569e..e69b88e 100644 --- a/src/soc/intel/broadwell/memmap.h +++ b/src/soc/intel/broadwell/memmap.h @@ -3,17 +3,9 @@ #ifndef _BROADWELL_IOMAP_H_ #define _BROADWELL_IOMAP_H_ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - -#define MCH_BASE_ADDRESS 0xfed10000 -#define MCH_BASE_SIZE 0x8000 - -#define DMI_BASE_ADDRESS 0xfed18000 -#define DMI_BASE_SIZE 0x1000 - -#define EP_BASE_ADDRESS 0xfed19000 -#define EP_BASE_SIZE 0x1000 +#define DEFAULT_MCHBAR 0xfed10000 +#define DEFAULT_DMIBAR 0xfed18000 +#define DEFAULT_EPBAR 0xfed19000 #define EDRAM_BASE_ADDRESS 0xfed80000 #define EDRAM_BASE_SIZE 0x4000 @@ -21,10 +13,7 @@ #define GDXC_BASE_ADDRESS 0xfed84000 #define GDXC_BASE_SIZE 0x1000 -#define RCBA_BASE_ADDRESS 0xfed1c000 -#define RCBA_BASE_SIZE 0x4000 - -#define HPET_BASE_ADDRESS 0xfed00000 +#define DEFAULT_RCBA 0xfed1c000 #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -32,14 +21,10 @@ #define VTVC0_BASE_ADDRESS 0xfed91000ULL #define VTVC0_BASE_SIZE 0x1000 -#define ACPI_BASE_ADDRESS 0x1000 -#define ACPI_BASE_SIZE 0x100 +#define DEFAULT_PMBASE 0x1000 -#define GPIO_BASE_ADDRESS 0x1400 -#define GPIO_BASE_SIZE 0x400 - -#define SMBUS_BASE_ADDRESS 0x0400 -#define SMBUS_BASE_SIZE 0x10 +#define DEFAULT_GPIOBASE 0x1400 +#define DEFAULT_GPIOSIZE 0x400 /* Temporary addresses used in romstage */ #define EARLY_GTT_BAR 0xe0000000 diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 33293a4..1319a02 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -115,9 +115,9 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { MCHBAR, 0x8000, get_bar, "MCHBAR" }, + { DMIBAR, 0x1000, get_bar, "DMIBAR" }, + { EPBAR, 0x1000, get_bar, "EPBAR" }, { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, }; diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl index 6b20f27..afbd4d6 100644 --- a/src/soc/intel/broadwell/pch/acpi/gpio.asl +++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl @@ -41,9 +41,9 @@ CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - BLEN = GPIO_BASE_SIZE - BMIN = GPIO_BASE_ADDRESS - BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1 + BLEN = DEFAULT_GPIOSIZE + BMIN = DEFAULT_GPIOBASE + BMAX = DEFAULT_GPIOBASE + DEFAULT_GPIOSIZE - 1 Return (RBUF) } diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index ae54ce3..5f69d7c 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -155,7 +155,7 @@ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, 0x1, 0xff) + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff) }) Method (_CRS, 0, NotSerialized) diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index c7c6207..b10c62d 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -15,7 +15,7 @@ } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 79cfe90..fa6ff95 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -14,7 +14,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) @@ -49,13 +49,13 @@ static void pch_enable_bars(void) { /* Set up southbridge BARs */ - pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); - pci_write_config32(PCH_LPC_DEV, PMBASE, ACPI_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, GPIO_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); /* Enable GPIO functionality. */ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, GPIO_EN); @@ -89,15 +89,15 @@ (void)RCBA32(HPTC); /* Enable HPET to start counter */ - setbits32((void *)HPET_BASE_ADDRESS + 0x10, 1 << 0); + setbits32((void *)CONFIG_HPET_ADDRESS + 0x10, 1 << 0); /* Disable reset */ RCBA32_OR(GCS, 1 << 5); /* TCO timer halt */ - u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT); + u16 reg16 = inb(DEFAULT_PMBASE + TCO1_CNT); reg16 |= TCO_TMR_HLT; - outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT); + outb(reg16, DEFAULT_PMBASE + TCO1_CNT); /* Enable upper 128 bytes of CMOS */ RCBA32_OR(RC, 1 << 2); diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 5679541..39e3508 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -8,7 +8,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = DEFAULT_PMBASE; fadt->sci_int = 9; diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/soc/intel/broadwell/pch/gpio.c index eac484c..d61670d 100644 --- a/src/soc/intel/broadwell/pch/gpio.c +++ b/src/soc/intel/broadwell/pch/gpio.c @@ -53,8 +53,8 @@ break; /* Setup Configuration registers 1 and 2 */ - outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio)); - outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio)); + outl(entry->conf0, DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio)); + outl(entry->conf1, DEFAULT_GPIOBASE + GPIO_CONFIG1(gpio)); /* Determine set and bit based on GPIO number */ set = gpio >> 5; @@ -78,14 +78,14 @@ } for (set = 0; set <= 2; set++) { - outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set)); - outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); - outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); - outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set)); + outl(owner[set], DEFAULT_GPIOBASE + GPIO_OWNER(set)); + outl(route[set], DEFAULT_GPIOBASE + GPIO_ROUTE(set)); + outl(irqen[set], DEFAULT_GPIOBASE + GPIO_IRQ_IE(set)); + outl(reset[set], DEFAULT_GPIOBASE + GPIO_RESET(set)); } - outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); - outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); + outl(blink, DEFAULT_GPIOBASE + GPIO_BLINK); + outl(pirq2apic, DEFAULT_GPIOBASE + GPIO_PIRQ_APIC_EN); } int get_gpio(int gpio_num) @@ -93,7 +93,7 @@ if (gpio_num > MAX_GPIO_NUMBER) return 0; - return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); + return !!(inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); } /* @@ -122,13 +122,13 @@ if (gpio_num > MAX_GPIO_NUMBER) return; - conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); + conf0 = inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)); conf0 &= ~GPO_LEVEL_MASK; conf0 |= value << GPO_LEVEL_SHIFT; - outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); + outl(conf0, DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)); } int gpio_is_native(int gpio_num) { - return !(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & 1); + return !(inl(DEFAULT_GPIOBASE + GPIO_CONFIG0(gpio_num)) & 1); } diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 2114a84..d5ecdeb 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -194,10 +194,10 @@ pci_write_config16(dev, GEN_PMCON_3, reg16); /* Prepare sleep mode */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = inl(DEFAULT_PMBASE + PM1_CNT); reg32 &= ~SLP_TYP; reg32 |= SCI_EN; - outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + outl(reg32, DEFAULT_PMBASE + PM1_CNT); /* Set up NMI on errors */ reg8 = inb(0x61); @@ -499,9 +499,9 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if (default_decode_base > RCBA_BASE_ADDRESS) { + if (default_decode_base > DEFAULT_RCBA) { res = new_resource(dev, RCBA); - res->base = RCBA_BASE_ADDRESS; + res->base = DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; @@ -583,11 +583,11 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIOBASE */ - pch_lpc_add_io_resource(dev, GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE, GPIO_BASE); + pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, + DEFAULT_GPIOSIZE, GPIO_BASE); /* PMBASE */ - pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); + pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 0x100, PMBASE); /* LPC Generic IO Decode range. */ if (dev->chip_info) { diff --git a/src/soc/intel/broadwell/pch/pm.h b/src/soc/intel/broadwell/pch/pm.h index 40467ed..7e9e1a5 100644 --- a/src/soc/intel/broadwell/pch/pm.h +++ b/src/soc/intel/broadwell/pch/pm.h @@ -5,7 +5,7 @@ #include <acpi/acpi.h> -/* ACPI_BASE_ADDRESS / PMBASE */ +/* DEFAULT_PMBASE / PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index cc61715..e8af6cc 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -24,7 +24,7 @@ static inline uint16_t get_gpiobase(void) { - return GPIO_BASE_ADDRESS; + return DEFAULT_GPIOBASE; } /* Print status bits with descriptive names */ @@ -424,5 +424,5 @@ /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t) DEFAULT_PMBASE; } diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index bb80550..562b876 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -50,7 +50,7 @@ break; } /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + outl(ps->pm1_cnt & ~(SLP_TYP), DEFAULT_PMBASE + PM1_CNT); } if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR)) @@ -86,19 +86,19 @@ { struct chipset_power_state *ps = &power_state; - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); - ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS); - ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS); - ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); - ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1)); - ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2)); - ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3)); - ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); - ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1)); - ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); - ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3)); + ps->pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + ps->pm1_en = inw(DEFAULT_PMBASE + PM1_EN); + ps->pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + ps->tco1_sts = inw(DEFAULT_PMBASE + TCO1_STS); + ps->tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); + ps->gpe0_sts[0] = inl(DEFAULT_PMBASE + GPE0_STS(0)); + ps->gpe0_sts[1] = inl(DEFAULT_PMBASE + GPE0_STS(1)); + ps->gpe0_sts[2] = inl(DEFAULT_PMBASE + GPE0_STS(2)); + ps->gpe0_sts[3] = inl(DEFAULT_PMBASE + GPE0_STS(3)); + ps->gpe0_en[0] = inl(DEFAULT_PMBASE + GPE0_EN(0)); + ps->gpe0_en[1] = inl(DEFAULT_PMBASE + GPE0_EN(1)); + ps->gpe0_en[2] = inl(DEFAULT_PMBASE + GPE0_EN(2)); + ps->gpe0_en[3] = inl(DEFAULT_PMBASE + GPE0_EN(3)); ps->gen_pmcon1 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_1); ps->gen_pmcon2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2); diff --git a/src/soc/intel/broadwell/pch/rcba.h b/src/soc/intel/broadwell/pch/rcba.h index b514c6a..7293dff 100644 --- a/src/soc/intel/broadwell/pch/rcba.h +++ b/src/soc/intel/broadwell/pch/rcba.h @@ -5,9 +5,9 @@ #include <soc/intel/broadwell/memmap.h> -#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x)) -#define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x)) -#define RCBA32(x) *((volatile u32 *)(RCBA_BASE_ADDRESS + x)) +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) #define RCBA_AND_OR(bits, x, and, or) \ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) diff --git a/src/soc/intel/broadwell/pch/smbus.c b/src/soc/intel/broadwell/pch/smbus.c index 8985905..76562ce 100644 --- a/src/soc/intel/broadwell/pch/smbus.c +++ b/src/soc/intel/broadwell/pch/smbus.c @@ -61,7 +61,7 @@ static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_BASE_ADDRESS; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/soc/intel/broadwell/pch/smi.c index 21986e3..3231f2c 100644 --- a/src/soc/intel/broadwell/pch/smi.c +++ b/src/soc/intel/broadwell/pch/smi.c @@ -14,9 +14,9 @@ u32 smi_en; printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", DEFAULT_PMBASE); - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); + smi_en = inl(DEFAULT_PMBASE + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index d79082a..ec3f819 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -16,13 +16,13 @@ pei_data->pei_version = PEI_VERSION; pei_data->board_type = BOARD_TYPE_ULT; pei_data->usbdebug = CONFIG(USBDEBUG); - pei_data->pciexbar = MCFG_BASE_ADDRESS; - pei_data->smbusbar = SMBUS_BASE_ADDRESS; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; pei_data->ehcibar = EARLY_EHCI_BAR; pei_data->xhcibar = EARLY_XHCI_BAR; pei_data->gttbar = EARLY_GTT_BAR; - pei_data->pmbase = ACPI_BASE_ADDRESS; - pei_data->gpiobase = GPIO_BASE_ADDRESS; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; pei_data->temp_mmio_base = EARLY_TEMP_MMIO; pei_data->tx_byte = &send_to_console; -- To view, visit https://review.coreboot.org/c/coreboot/+/46956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I473336a77179a3d1d26933f481abded49e9f0864 Gerrit-Change-Number: 46956 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020