coreboot-gerrit October 2020

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Change in coreboot[master]: src/include: Clean up some includes
by HAOUAS Elyes (Code Review) 04 Feb '21

04 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44207 ) Change subject: src/include: Clean up some includes ...................................................................... src/include: Clean up some includes Change-Id: I69c4d21273c9fb400449fd39274f15c0be013402 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/bootblock_common.h M src/include/bootsplash.h M src/include/cpu/amd/amd64_save_state.h M src/include/cpu/intel/em64t100_save_state.h M src/include/cpu/intel/em64t101_save_state.h M src/include/cpu/x86/legacy_save_state.h M src/include/device/smbus_def.h M src/include/option.h M src/include/symbols.h M src/include/timer.h 10 files changed, 9 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/44207/1 diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 97ccf96..59eb83a 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -5,8 +5,8 @@ #include <arch/cpu.h> #include <main_decl.h> +#include <stdint.h> #include <timestamp.h> -#include <types.h> /* * These are defined as weak no-ops that can be overridden by mainboard/SoC. diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index d5aecf8..9ba730d 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -3,8 +3,6 @@ #ifndef __BOOTSPLASH_H__ #define __BOOTSPLASH_H__ -#include <types.h> - /** * Sets up the framebuffer with the bootsplash.jpg from cbfs. * Returns 0 on success diff --git a/src/include/cpu/amd/amd64_save_state.h b/src/include/cpu/amd/amd64_save_state.h index 08b700a..27b1ecf 100644 --- a/src/include/cpu/amd/amd64_save_state.h +++ b/src/include/cpu/amd/amd64_save_state.h @@ -4,8 +4,8 @@ #define __AMD64_SAVE_STATE_H__ #endif -#include <types.h> #include <cpu/x86/smm.h> +#include <stdint.h> /* AMD64 x86 SMM State-Save Area * starts @ 0x7e00 diff --git a/src/include/cpu/intel/em64t100_save_state.h b/src/include/cpu/intel/em64t100_save_state.h index 8596ce5..c510d4b 100644 --- a/src/include/cpu/intel/em64t100_save_state.h +++ b/src/include/cpu/intel/em64t100_save_state.h @@ -3,8 +3,8 @@ #ifndef __EM64T100_SAVE_STATE_H__ #define __EM64T100_SAVE_STATE_H__ -#include <types.h> #include <cpu/x86/smm.h> +#include <stdint.h> /* Intel Revision 30100 SMM State-Save Area */ diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 2e4e0d5..ce5a974 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -3,9 +3,8 @@ #ifndef __EM64T101_SAVE_STATE_H__ #define __EM64T101_SAVE_STATE_H__ -#include <types.h> #include <cpu/x86/smm.h> - +#include <stdint.h> /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: diff --git a/src/include/cpu/x86/legacy_save_state.h b/src/include/cpu/x86/legacy_save_state.h index 4c9923c..c557e28 100644 --- a/src/include/cpu/x86/legacy_save_state.h +++ b/src/include/cpu/x86/legacy_save_state.h @@ -3,7 +3,7 @@ #ifndef __X86_LEGACY_SAVE_STATE_H__ #define __X86_LEGACY_SAVE_STATE_H__ -#include <types.h> +#include <stdint.h> /* Legacy x86 SMM State-Save Area * starts @ 0x7e00 diff --git a/src/include/device/smbus_def.h b/src/include/device/smbus_def.h index 61d7861..ef9fb56 100644 --- a/src/include/device/smbus_def.h +++ b/src/include/device/smbus_def.h @@ -1,7 +1,7 @@ #ifndef DEVICE_SMBUS_DEF_H #define DEVICE_SMBUS_DEF_H -#include <types.h> +#include <commonlib/bsd/cb_err.h> /* Error results are negative success is >= 0 */ #define SMBUS_ERROR CB_ERR diff --git a/src/include/option.h b/src/include/option.h index 6b4e6a9..09a29f2 100644 --- a/src/include/option.h +++ b/src/include/option.h @@ -3,7 +3,7 @@ #ifndef _OPTION_H_ #define _OPTION_H_ -#include <types.h> +#include <commonlib/bsd/cb_err.h> void sanitize_cmos(void); diff --git a/src/include/symbols.h b/src/include/symbols.h index f84672e..c081efc 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -3,7 +3,8 @@ #ifndef __SYMBOLS_H #define __SYMBOLS_H -#include <types.h> +#include <rules.h> +#include <stdint.h> extern u8 _dram[]; diff --git a/src/include/timer.h b/src/include/timer.h index 9b7a05e..0bb8666 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -2,8 +2,6 @@ #ifndef TIMER_H #define TIMER_H -#include <types.h> - #define NSECS_PER_SEC 1000000000 #define USECS_PER_SEC 1000000 #define MSECS_PER_SEC 1000 -- To view, visit https://review.coreboot.org/c/coreboot/+/44207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69c4d21273c9fb400449fd39274f15c0be013402 Gerrit-Change-Number: 44207 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Create RMRR for iGPU
by Angel Pons (Code Review) 03 Feb '21

03 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46990 ) Change subject: nb/intel/haswell: Create RMRR for iGPU ...................................................................... nb/intel/haswell: Create RMRR for iGPU Taken from Broadwell. Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46990/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 0e7967f..f48ef61 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -63,6 +63,21 @@ acpi_dmar_drhd_fixup(tmp, current); } + /* Then, add RMRR entries after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + const struct device *sa_dev = pcidev_on_root(0, 0); + + /* Bit 0 is lock bit, not part of address */ + const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; + const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; + + current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I246fdc1473bf8949073377d03622026bd3e6aafa Gerrit-Change-Number: 46990 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/zork: C-state IO base address aligment
by chris wang (Code Review) 03 Feb '21

03 Feb '21

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44135 to review the following change. Change subject: mb/google/zork: C-state IO base address aligment ...................................................................... mb/google/zork: C-state IO base address aligment Align the C-state MSR value of BSP with AGESA. BUG=b:162705221 BRANCH=none TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ib98d34af518439d338326446c20601867ad31690 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/iomap.h 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44135/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..039e3c2 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -257,6 +257,12 @@ help Base address for the ACPI registers. +config PICASSO_CSTATE_IO_BASE_ADDR + hex + default 0x413 + help + Base address for the CC6 State. + config PICASSO_CONSOLE_UART bool "Use Picasso UART controller for console" default n diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 6b9ad2a..360b348 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -64,12 +64,12 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 #define PICASSO_ACPI_IO_BASE CONFIG_PICASSO_ACPI_IO_BASE +#define ACPI_CPU_CONTROL CONFIG_PICASSO_CSTATE_IO_BASE_ADDR #define ACPI_PM_EVT_BLK (PICASSO_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (PICASSO_ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (PICASSO_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (PICASSO_ACPI_IO_BASE + 0x0c) /* 6 bytes */ /* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ #define ACPI_GPE0_BLK (PICASSO_ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98d34af518439d338326446c20601867ad31690 Gerrit-Change-Number: 44135 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/hp/kbc1126: Wait a longer time after the first command
by Pablo Stebler (Code Review) 03 Feb '21

03 Feb '21

Pablo Stebler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44750 ) Change subject: ec/hp/kbc1126: Wait a longer time after the first command ...................................................................... ec/hp/kbc1126: Wait a longer time after the first command This prevents the fans from running at full speed on ProBook 6360b and EliteBook 8470p (because the fan control command was not sent). Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb --- M src/ec/hp/kbc1126/ec.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44750/1 diff --git a/src/ec/hp/kbc1126/ec.c b/src/ec/hp/kbc1126/ec.c index 5c11fed..ff47649 100644 --- a/src/ec/hp/kbc1126/ec.c +++ b/src/ec/hp/kbc1126/ec.c @@ -115,6 +115,13 @@ struct ec_hp_kbc1126_config *conf = dev->chip_info; ec_setports(conf->ec_data_port, conf->ec_cmd_port); kbc1126_kbdled(conf->ec_ctrl_reg, 0); + + /* The EC needs additional time to process the first command on a cold + boot. */ + int timeout = 0x17ff; + while ((inb(conf->ec_cmd_port) & KBD_IBF) && --timeout) + udelay(10); + if (kbc1126_thermalinit(conf->ec_ctrl_reg, conf->ec_fan_ctrl_value) < 0) printk(BIOS_DEBUG, "KBC1126: error when initializing fan control.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb Gerrit-Change-Number: 44750 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/ti/am335x/header.c: Add missing include
by HAOUAS Elyes (Code Review) 03 Feb '21

03 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44738 ) Change subject: soc/ti/am335x/header.c: Add missing include ...................................................................... soc/ti/am335x/header.c: Add missing include Use of 'offsetof' needs stddef. Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/ti/am335x/header.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44738/1 diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c index 9edfdd0..9ed9937 100644 --- a/src/soc/ti/am335x/header.c +++ b/src/soc/ti/am335x/header.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <stddef.h> #include <stdint.h> #include <symbols.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486 Gerrit-Change-Number: 44738 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/pcengines/apu2: Remove gpio1_ and gpio2_ references
by Kyösti Mälkki (Code Review) 01 Feb '21

01 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42521 ) Change subject: mb/pcengines/apu2: Remove gpio1_ and gpio2_ references ...................................................................... mb/pcengines/apu2: Remove gpio1_ and gpio2_ references The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL also takes advantage of this property. Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.c 1 file changed, 8 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42521/1 diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index c249c2d..03eddce 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -10,27 +10,20 @@ static u32 gpio_read_wrapper(u32 iomux_gpio) { u32 gpio = iomux_gpio << 2; + if (gpio >= 0x300) + die("Invalid GPIO"); - if (gpio < 0x100) - return gpio0_read32(gpio & 0xff); - else if (gpio >= 0x100 && gpio < 0x200) - return gpio1_read32(gpio & 0xff); - else if (gpio >= 0x200 && gpio < 0x300) - return gpio2_read32(gpio & 0xff); + return gpio0_read32(gpio & 0x3ff); - die("Invalid GPIO"); } static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) { u32 gpio = iomux_gpio << 2; + if (gpio >= 0x300) + die("Invalid GPIO"); - if (gpio < 0x100) - gpio0_write32(gpio & 0xff, setting); - else if (gpio >= 0x100 && gpio < 0x200) - gpio1_write32(gpio & 0xff, setting); - else if (gpio >= 0x200 && gpio < 0x300) - gpio2_write32(gpio & 0xff, setting); + gpio0_write32(gpio & 0x3ff, setting); } void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) @@ -70,9 +63,9 @@ * One SPD file contains all 4 options, determine which index to * read here, then call into the standard routines. */ - if (gpio1_read8(0x02) & BIT0) + if (read_gpio(GPIO_49)) index |= BIT0; - if (gpio1_read8(0x06) & BIT0) + if (read_gpio(GPIO_50)) index |= BIT1; return index; -- To view, visit https://review.coreboot.org/c/coreboot/+/42521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7 Gerrit-Change-Number: 42521 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/name/name.c: Clean up includes
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44315 ) Change subject: cpu/x86/name/name.c: Clean up includes ...................................................................... cpu/x86/name/name.c: Clean up includes Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/name/name.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44315/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index a7d2c70..d4f50b6 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -2,8 +2,8 @@ #include <string.h> #include <arch/cpu.h> -#include <device/device.h> #include <cpu/x86/name.h> +#include <stdint.h> void fill_processor_name(char *processor_name) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7 Gerrit-Change-Number: 44315 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h>
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45815 ) Change subject: mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> ...................................................................... mb/google/dedede/variants/drawcia/variant.c: Remove unused <bootstate.h> Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/dedede/variants/drawcia/variant.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/45815/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/variant.c b/src/mainboard/google/dedede/variants/drawcia/variant.c index 88e9de7..321d165 100644 --- a/src/mainboard/google/dedede/variants/drawcia/variant.c +++ b/src/mainboard/google/dedede/variants/drawcia/variant.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bootstate.h> #include <fw_config.h> #include <sar.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38d115f2c405128a8d80aec48d2d9d3f25867151 Gerrit-Change-Number: 45815 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include
by HAOUAS Elyes (Code Review) 01 Feb '21

01 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44737 ) Change subject: soc/samsung/exynos5250/include/soc/cpu.h: Add missing include ...................................................................... soc/samsung/exynos5250/include/soc/cpu.h: Add missing include Use of 'KiB' needs <commonlib/bsd/helpers.h> Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/samsung/exynos5250/include/soc/cpu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44737/1 diff --git a/src/soc/samsung/exynos5250/include/soc/cpu.h b/src/soc/samsung/exynos5250/include/soc/cpu.h index aa5a2e8..6d5c18a 100644 --- a/src/soc/samsung/exynos5250/include/soc/cpu.h +++ b/src/soc/samsung/exynos5250/include/soc/cpu.h @@ -3,6 +3,7 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_CPU_H #define CPU_SAMSUNG_EXYNOS5250_CPU_H +#include <commonlib/bsd/helpers.h> #include <symbols.h> /* Base address registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6ba36fd4b0364cc9984523f0add859869068727 Gerrit-Change-Number: 44737 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Calculate TSEG limit from registers
by Angel Pons (Code Review) 01 Feb '21

01 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46991 ) Change subject: nb/intel/haswell: Calculate TSEG limit from registers ...................................................................... nb/intel/haswell: Calculate TSEG limit from registers Done for consistency with other northbridges. Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/memmap.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46991/1 diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 02d120b..c19cfec 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,13 +4,13 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <cbmem.h> #include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt_register.h> +#include <types.h> #include "haswell.h" @@ -19,9 +19,9 @@ return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); } -static size_t northbridge_get_tseg_size(void) +static uintptr_t northbridge_get_tseg_limit(void) { - return CONFIG_SMM_TSEG_SIZE; + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB); } union dpr_register txt_get_chipset_dpr(void) @@ -62,7 +62,9 @@ void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_limit(); + + *size -= *start; } void fill_postcar_frame(struct postcar_frame *pcf) -- To view, visit https://review.coreboot.org/c/coreboot/+/46991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8 Gerrit-Change-Number: 46991 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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