coreboot-gerrit September 2019

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Change in coreboot[master]: mb/asus/p8h61-m_pro: Fix integrated network
by Angel Pons (Code Review) 03 May '20

03 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34124 ) Change subject: mb/asus/p8h61-m_pro: Fix integrated network ...................................................................... mb/asus/p8h61-m_pro: Fix integrated network Looks like this select makes the internal NIC not work. Not sure why, though. Change-Id: I92e603c86d9bfe9be9e53918e8f1477a9a1dcf99 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p8h61-m_pro/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34124/1 diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig index e8a6f64..d3d1c67 100644 --- a/src/mainboard/asus/p8h61-m_pro/Kconfig +++ b/src/mainboard/asus/p8h61-m_pro/Kconfig @@ -31,7 +31,6 @@ select HAVE_CMOS_DEFAULT select DRIVERS_ASMEDIA_ASPM_BLACKLIST select MAINBOARD_HAS_LPC_TPM - select REALTEK_8168_RESET select RT8168_SET_LED_MODE select INTEL_GMA_HAVE_VBT -- To view, visit https://review.coreboot.org/c/coreboot/+/34124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92e603c86d9bfe9be9e53918e8f1477a9a1dcf99 Gerrit-Change-Number: 34124 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/skylake: Do cosmetic fixes
by Angel Pons (Code Review) 03 May '20

03 May '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35172 ) Change subject: soc/intel/skylake: Do cosmetic fixes ...................................................................... soc/intel/skylake: Do cosmetic fixes This is mostly line reflowing to make use of the increased line length limit of 96 characters. Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/fspcar.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/gpio.h M src/soc/intel/skylake/include/soc/gpio_defs.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/nhlt/nau88l25.c M src/soc/intel/skylake/nhlt/rt5514.c M src/soc/intel/skylake/nhlt/rt5663.c M src/soc/intel/skylake/p2sb.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/vr_config.c 39 files changed, 561 insertions(+), 1,015 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35172/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index ccfc7b7..649220f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -191,8 +191,7 @@ /* Initialize Verified Boot data */ chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #if CONFIG(EC_GOOGLE_CHROMEEC) - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif @@ -225,8 +224,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); return acpi_madt_irq_overrides(current); } @@ -526,15 +524,13 @@ /* Generate processor \_PR.CPUx */ acpigen_write_processor( - cpu_id*cores_per_package+core_id, - pcontrol_blk, plen); + cpu_id*cores_per_package+core_id, pcontrol_blk, plen); /* Generate C-state tables */ generate_c_state_entries(is_s0ix_enable); if (config->eist_enable) { /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + generate_p_state_entries(core_id, cores_per_package); if (config->speed_shift_enable) acpigen_write_CPPC_method(); } @@ -569,8 +565,8 @@ /* Add RMRR entry */ tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_rmrr(current, 0, sa_get_gsm_base(), + sa_get_tolud_base() - 1); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_rmrr_fixup(tmp, current); } @@ -606,8 +602,7 @@ return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { const struct soc_intel_skylake_config *const config = config_of(dev); @@ -648,12 +643,10 @@ return current; } -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - current = acpi_write_dbg2_pci_uart(rsdp, current, - uart_get_device(), + current = acpi_write_dbg2_pci_uart(rsdp, current, uart_get_device(), ACPI_ACCESS_SIZE_DWORD_ACCESS); current = acpi_write_hpet(device, current, rsdp); return acpi_align_current(current); diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index e9ca2d8..2b788c6 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. + * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..1ec9f5d 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -93,19 +93,16 @@ pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); /* - * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] - * to the same value programmed in PMC PCI Offset 48h bit[31:16], - * this has an implication of making sure the PWRMBASE to be - * 64KB aligned. + * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value + * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure + * the PWRMBASE to be 64KB aligned. * - * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] - * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an - * implication of making sure the memory allocated to PWRMBASE to be - * 64KB in size. + * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value + * programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure + * the memory allocated to PWRMBASE to be 64KB in size. */ pcr_write32(PID_DMI, PCR_DMI_PMBASEA, - ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | - (PCH_PWRM_BASE_ADDRESS >> 16))); + ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | (PCH_PWRM_BASE_ADDRESS >> 16))); if (CONFIG(SKYLAKE_SOC_PCH_H)) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); else @@ -116,10 +113,7 @@ { uint32_t dmi_control; - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ + /* This cycle decoding is only allowed to set when DMICTL.SRLOCK is 0. */ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); if (dmi_control & PCR_DMI_DMICTL_SRLOCK) return -1; @@ -128,8 +122,7 @@ void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) @@ -152,19 +145,13 @@ void pch_early_init(void) { - /* - * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, - * GPE0_STS, GPE0_EN registers. - */ + /* Enable ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, GPE0_STS, GPE0_EN registers. */ soc_config_acpibase(); - /* - * Enabling PWRM Base for accessing - * Global Reset Cause Register. - */ + /* Enable PWRM Base for accessing Global Reset Cause Register. */ soc_config_pwrmbase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); /* Program SMBUS_BASE_ADDRESS and Enable it */ diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 1e65d9a..c7c1c5e 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -94,12 +94,9 @@ { PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, "Kabylake-U Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, "Kabylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, "Kabylake Super Sku" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, - "Kabylake-Y iHDCP 2.2 Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, - "Kabylake-U iHDCP 2.2 Premium" }, - { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, - "Kabylake-U iHDCP 2.2 Base" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22, "Kabylake-Y iHDCP 2.2 Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22, "Kabylake-U iHDCP 2.2 Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22, "Kabylake-U iHDCP 2.2 Base" }, }; static struct { @@ -181,8 +178,7 @@ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; - printk(BIOS_DEBUG, - "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", + printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); } @@ -269,8 +265,7 @@ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); printk(BIOS_DEBUG, " rank interleave %s\n", diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d5872..3a6decd 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -100,18 +100,12 @@ sizeof(params->SerialIoDevMode)); for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -119,8 +113,7 @@ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; @@ -129,14 +122,12 @@ } } - memcpy(params->PcieRpEnable, config->PcieRpEnable, - sizeof(params->PcieRpEnable)); + memcpy(params->PcieRpEnable, config->PcieRpEnable, sizeof(params->PcieRpEnable)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); params->EnableLan = config->EnableLan; params->Cio2Enable = config->Cio2Enable; @@ -178,10 +169,8 @@ if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - params->WakeConfigWolEnableOverride = - config->WakeConfigWolEnableOverride; - params->WakeConfigPcieWakeFromDeepSx = - config->WakeConfigPcieWakeFromDeepSx; + params->WakeConfigWolEnableOverride = config->WakeConfigWolEnableOverride; + params->WakeConfigPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PmConfigDeepSxPol = config->PmConfigDeepSxPol; params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert; params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert; @@ -189,14 +178,11 @@ params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PmConfigPciClockRun = config->PmConfigPciClockRun; params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PmConfigPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; + params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PmConfigPwrCycDur = config->PmConfigPwrCycDur; params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF; - params->SerialIrqConfigSirqMode = - config->serirq_mode == SERIRQ_CONTINUOUS; - params->SerialIrqConfigStartFramePulse = - config->SerialIrqConfigStartFramePulse; + params->SerialIrqConfigSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; + params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; @@ -204,11 +190,9 @@ params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; /* - * To disable Heci, the Psf needs to be left unlocked - * by FSP after end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in Fsp, - * do the changes and then lock it back in coreboot - * + * To disable Heci, the Psf needs to be left unlocked by FSP after end of post + * sequence. Based on the devicetree setting, we set the appropriate PsfUnlock + * policy in Fsp, do the changes and then lock it back in coreboot. */ if (config->HeciEnabled == 0) params->PsfUnlock = 1; @@ -249,8 +233,8 @@ /* Display the parameters for SiliconInit */ printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); fsp_display_upd_value("LogoPtr", 4, - (uint32_t)original->LogoPtr, - (uint32_t)params->LogoPtr); + (uint32_t)original->LogoPtr, + (uint32_t)params->LogoPtr); fsp_display_upd_value("LogoSize", 4, (uint32_t)original->LogoSize, (uint32_t)params->LogoSize); @@ -266,8 +250,7 @@ fsp_display_upd_value("TurboMode", 1, (uint32_t)original->TurboMode, (uint32_t)params->TurboMode); - fsp_display_upd_value("Device4Enable", 1, - original->Device4Enable, + fsp_display_upd_value("Device4Enable", 1, original->Device4Enable, params->Device4Enable); fsp_display_upd_value("PcieRpEnable[0]", 1, original->PcieRpEnable[0], params->PcieRpEnable[0]); @@ -309,130 +292,89 @@ params->PcieRpEnable[18]); fsp_display_upd_value("PcieRpEnable[19]", 1, original->PcieRpEnable[19], params->PcieRpEnable[19]); - fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, - original->PcieRpClkReqSupport[0], + fsp_display_upd_value("PcieRpClkReqSupport[0]", 1, original->PcieRpClkReqSupport[0], params->PcieRpClkReqSupport[0]); - fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, - original->PcieRpClkReqSupport[1], + fsp_display_upd_value("PcieRpClkReqSupport[1]", 1, original->PcieRpClkReqSupport[1], params->PcieRpClkReqSupport[1]); - fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, - original->PcieRpClkReqSupport[2], + fsp_display_upd_value("PcieRpClkReqSupport[2]", 1, original->PcieRpClkReqSupport[2], params->PcieRpClkReqSupport[2]); - fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, - original->PcieRpClkReqSupport[3], + fsp_display_upd_value("PcieRpClkReqSupport[3]", 1, original->PcieRpClkReqSupport[3], params->PcieRpClkReqSupport[3]); - fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, - original->PcieRpClkReqSupport[4], + fsp_display_upd_value("PcieRpClkReqSupport[4]", 1, original->PcieRpClkReqSupport[4], params->PcieRpClkReqSupport[4]); - fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, - original->PcieRpClkReqSupport[5], + fsp_display_upd_value("PcieRpClkReqSupport[5]", 1, original->PcieRpClkReqSupport[5], params->PcieRpClkReqSupport[5]); - fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, - original->PcieRpClkReqSupport[6], + fsp_display_upd_value("PcieRpClkReqSupport[6]", 1, original->PcieRpClkReqSupport[6], params->PcieRpClkReqSupport[6]); - fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, - original->PcieRpClkReqSupport[7], + fsp_display_upd_value("PcieRpClkReqSupport[7]", 1, original->PcieRpClkReqSupport[7], params->PcieRpClkReqSupport[7]); - fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, - original->PcieRpClkReqSupport[8], + fsp_display_upd_value("PcieRpClkReqSupport[8]", 1, original->PcieRpClkReqSupport[8], params->PcieRpClkReqSupport[8]); - fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, - original->PcieRpClkReqSupport[9], + fsp_display_upd_value("PcieRpClkReqSupport[9]", 1, original->PcieRpClkReqSupport[9], params->PcieRpClkReqSupport[9]); - fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, - original->PcieRpClkReqSupport[10], + fsp_display_upd_value("PcieRpClkReqSupport[10]", 1, original->PcieRpClkReqSupport[10], params->PcieRpClkReqSupport[10]); - fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, - original->PcieRpClkReqSupport[11], + fsp_display_upd_value("PcieRpClkReqSupport[11]", 1, original->PcieRpClkReqSupport[11], params->PcieRpClkReqSupport[11]); - fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, - original->PcieRpClkReqSupport[12], + fsp_display_upd_value("PcieRpClkReqSupport[12]", 1, original->PcieRpClkReqSupport[12], params->PcieRpClkReqSupport[12]); - fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, - original->PcieRpClkReqSupport[13], + fsp_display_upd_value("PcieRpClkReqSupport[13]", 1, original->PcieRpClkReqSupport[13], params->PcieRpClkReqSupport[13]); - fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, - original->PcieRpClkReqSupport[14], + fsp_display_upd_value("PcieRpClkReqSupport[14]", 1, original->PcieRpClkReqSupport[14], params->PcieRpClkReqSupport[14]); - fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, - original->PcieRpClkReqSupport[15], + fsp_display_upd_value("PcieRpClkReqSupport[15]", 1, original->PcieRpClkReqSupport[15], params->PcieRpClkReqSupport[15]); - fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, - original->PcieRpClkReqSupport[16], + fsp_display_upd_value("PcieRpClkReqSupport[16]", 1, original->PcieRpClkReqSupport[16], params->PcieRpClkReqSupport[16]); - fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, - original->PcieRpClkReqSupport[17], + fsp_display_upd_value("PcieRpClkReqSupport[17]", 1, original->PcieRpClkReqSupport[17], params->PcieRpClkReqSupport[17]); - fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, - original->PcieRpClkReqSupport[18], + fsp_display_upd_value("PcieRpClkReqSupport[18]", 1, original->PcieRpClkReqSupport[18], params->PcieRpClkReqSupport[18]); - fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, - original->PcieRpClkReqSupport[19], + fsp_display_upd_value("PcieRpClkReqSupport[19]", 1, original->PcieRpClkReqSupport[19], params->PcieRpClkReqSupport[19]); - fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, - original->PcieRpClkReqNumber[0], + fsp_display_upd_value("PcieRpClkReqNumber[0]", 1, original->PcieRpClkReqNumber[0], params->PcieRpClkReqNumber[0]); - fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, - original->PcieRpClkReqNumber[1], + fsp_display_upd_value("PcieRpClkReqNumber[1]", 1, original->PcieRpClkReqNumber[1], params->PcieRpClkReqNumber[1]); - fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, - original->PcieRpClkReqNumber[2], + fsp_display_upd_value("PcieRpClkReqNumber[2]", 1, original->PcieRpClkReqNumber[2], params->PcieRpClkReqNumber[2]); - fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, - original->PcieRpClkReqNumber[3], + fsp_display_upd_value("PcieRpClkReqNumber[3]", 1, original->PcieRpClkReqNumber[3], params->PcieRpClkReqNumber[3]); - fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, - original->PcieRpClkReqNumber[4], + fsp_display_upd_value("PcieRpClkReqNumber[4]", 1, original->PcieRpClkReqNumber[4], params->PcieRpClkReqNumber[4]); - fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, - original->PcieRpClkReqNumber[5], + fsp_display_upd_value("PcieRpClkReqNumber[5]", 1, original->PcieRpClkReqNumber[5], params->PcieRpClkReqNumber[5]); - fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, - original->PcieRpClkReqNumber[6], + fsp_display_upd_value("PcieRpClkReqNumber[6]", 1, original->PcieRpClkReqNumber[6], params->PcieRpClkReqNumber[6]); - fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, - original->PcieRpClkReqNumber[7], + fsp_display_upd_value("PcieRpClkReqNumber[7]", 1, original->PcieRpClkReqNumber[7], params->PcieRpClkReqNumber[7]); - fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, - original->PcieRpClkReqNumber[8], + fsp_display_upd_value("PcieRpClkReqNumber[8]", 1, original->PcieRpClkReqNumber[8], params->PcieRpClkReqNumber[8]); - fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, - original->PcieRpClkReqNumber[9], + fsp_display_upd_value("PcieRpClkReqNumber[9]", 1, original->PcieRpClkReqNumber[9], params->PcieRpClkReqNumber[9]); - fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, - original->PcieRpClkReqNumber[10], + fsp_display_upd_value("PcieRpClkReqNumber[10]", 1, original->PcieRpClkReqNumber[10], params->PcieRpClkReqNumber[10]); - fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, - original->PcieRpClkReqNumber[11], + fsp_display_upd_value("PcieRpClkReqNumber[11]", 1, original->PcieRpClkReqNumber[11], params->PcieRpClkReqNumber[11]); - fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, - original->PcieRpClkReqNumber[12], + fsp_display_upd_value("PcieRpClkReqNumber[12]", 1, original->PcieRpClkReqNumber[12], params->PcieRpClkReqNumber[12]); - fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, - original->PcieRpClkReqNumber[13], + fsp_display_upd_value("PcieRpClkReqNumber[13]", 1, original->PcieRpClkReqNumber[13], params->PcieRpClkReqNumber[13]); - fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, - original->PcieRpClkReqNumber[14], + fsp_display_upd_value("PcieRpClkReqNumber[14]", 1, original->PcieRpClkReqNumber[14], params->PcieRpClkReqNumber[14]); - fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, - original->PcieRpClkReqNumber[15], + fsp_display_upd_value("PcieRpClkReqNumber[15]", 1, original->PcieRpClkReqNumber[15], params->PcieRpClkReqNumber[15]); - fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, - original->PcieRpClkReqNumber[16], + fsp_display_upd_value("PcieRpClkReqNumber[16]", 1, original->PcieRpClkReqNumber[16], params->PcieRpClkReqNumber[16]); - fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, - original->PcieRpClkReqNumber[17], + fsp_display_upd_value("PcieRpClkReqNumber[17]", 1, original->PcieRpClkReqNumber[17], params->PcieRpClkReqNumber[17]); - fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, - original->PcieRpClkReqNumber[18], + fsp_display_upd_value("PcieRpClkReqNumber[18]", 1, original->PcieRpClkReqNumber[18], params->PcieRpClkReqNumber[18]); - fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, - original->PcieRpClkReqNumber[19], + fsp_display_upd_value("PcieRpClkReqNumber[19]", 1, original->PcieRpClkReqNumber[19], params->PcieRpClkReqNumber[19]); - fsp_display_upd_value("EnableLan", 1, original->EnableLan, - params->EnableLan); - fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, - params->Cio2Enable); + + fsp_display_upd_value("EnableLan", 1, original->EnableLan, params->EnableLan); + fsp_display_upd_value("Cio2Enable", 1, original->Cio2Enable, params->Cio2Enable); fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, params->SataSalpSupport); fsp_display_upd_value("SataPortsEnable[0]", 1, @@ -467,10 +409,8 @@ original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]); fsp_display_upd_value("SataPortsDevSlp[7]", 1, original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]); - fsp_display_upd_value("EnableAzalia", 1, - original->EnableAzalia, params->EnableAzalia); - fsp_display_upd_value("DspEnable", 1, original->DspEnable, - params->DspEnable); + fsp_display_upd_value("EnableAzalia", 1, original->EnableAzalia, params->EnableAzalia); + fsp_display_upd_value("DspEnable", 1, original->DspEnable, params->DspEnable); fsp_display_upd_value("IoBufferOwnership", 1, original->IoBufferOwnership, params->IoBufferOwnership); fsp_display_upd_value("PortUsb20Enable[0]", 1, @@ -525,12 +465,10 @@ original->PortUsb30Enable[8], params->PortUsb30Enable[8]); fsp_display_upd_value("PortUsb30Enable[9]", 1, original->PortUsb30Enable[9], params->PortUsb30Enable[9]); - fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, - params->XdciEnable); - fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable, - params->SsicPortEnable); - fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, - params->SmbusEnable); + fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, params->XdciEnable); + fsp_display_upd_value("SsicPortEnable", 1, + original->SsicPortEnable, params->SsicPortEnable); + fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, params->SmbusEnable); fsp_display_upd_value("SerialIoDevMode[0]", 1, original->SerialIoDevMode[0], params->SerialIoDevMode[0]); fsp_display_upd_value("SerialIoDevMode[1]", 1, @@ -559,10 +497,9 @@ original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled); fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled, params->ScsSdCardEnabled); - fsp_display_upd_value("IshEnable", 1, original->IshEnable, - params->IshEnable); - fsp_display_upd_value("ShowSpiController", 1, - original->ShowSpiController, params->ShowSpiController); + fsp_display_upd_value("IshEnable", 1, original->IshEnable, params->IshEnable); + fsp_display_upd_value("ShowSpiController", 1, original->ShowSpiController, + params->ShowSpiController); fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging, params->HsioMessaging); fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, @@ -571,45 +508,28 @@ params->EnableSata); fsp_display_upd_value("SataMode", 1, original->SataMode, params->SataMode); - fsp_display_upd_value("NumOfDevIntConfig", 1, - original->NumOfDevIntConfig, + fsp_display_upd_value("NumOfDevIntConfig", 1, original->NumOfDevIntConfig, params->NumOfDevIntConfig); - fsp_display_upd_value("PxRcConfig[PARC]", 1, - original->PxRcConfig[PCH_PARC], + fsp_display_upd_value("PxRcConfig[PARC]", 1, original->PxRcConfig[PCH_PARC], params->PxRcConfig[PCH_PARC]); - fsp_display_upd_value("PxRcConfig[PBRC]", 1, - original->PxRcConfig[PCH_PBRC], + fsp_display_upd_value("PxRcConfig[PBRC]", 1, original->PxRcConfig[PCH_PBRC], params->PxRcConfig[PCH_PBRC]); - fsp_display_upd_value("PxRcConfig[PCRC]", 1, - original->PxRcConfig[PCH_PCRC], + fsp_display_upd_value("PxRcConfig[PCRC]", 1, original->PxRcConfig[PCH_PCRC], params->PxRcConfig[PCH_PCRC]); - fsp_display_upd_value("PxRcConfig[PDRC]", 1, - original->PxRcConfig[PCH_PDRC], + fsp_display_upd_value("PxRcConfig[PDRC]", 1, original->PxRcConfig[PCH_PDRC], params->PxRcConfig[PCH_PDRC]); - fsp_display_upd_value("PxRcConfig[PERC]", 1, - original->PxRcConfig[PCH_PERC], + fsp_display_upd_value("PxRcConfig[PERC]", 1, original->PxRcConfig[PCH_PERC], params->PxRcConfig[PCH_PERC]); - fsp_display_upd_value("PxRcConfig[PFRC]", 1, - original->PxRcConfig[PCH_PFRC], + fsp_display_upd_value("PxRcConfig[PFRC]", 1, original->PxRcConfig[PCH_PFRC], params->PxRcConfig[PCH_PFRC]); - fsp_display_upd_value("PxRcConfig[PGRC]", 1, - original->PxRcConfig[PCH_PGRC], + fsp_display_upd_value("PxRcConfig[PGRC]", 1, original->PxRcConfig[PCH_PGRC], params->PxRcConfig[PCH_PGRC]); - fsp_display_upd_value("PxRcConfig[PHRC]", 1, - original->PxRcConfig[PCH_PHRC], + fsp_display_upd_value("PxRcConfig[PHRC]", 1, original->PxRcConfig[PCH_PHRC], params->PxRcConfig[PCH_PHRC]); - fsp_display_upd_value("GpioIrqRoute", 1, - original->GpioIrqRoute, - params->GpioIrqRoute); - fsp_display_upd_value("SciIrqSelect", 1, - original->SciIrqSelect, - params->SciIrqSelect); - fsp_display_upd_value("TcoIrqSelect", 1, - original->TcoIrqSelect, - params->TcoIrqSelect); - fsp_display_upd_value("TcoIrqEnable", 1, - original->TcoIrqEnable, - params->TcoIrqEnable); + fsp_display_upd_value("GpioIrqRoute", 1, original->GpioIrqRoute, params->GpioIrqRoute); + fsp_display_upd_value("SciIrqSelect", 1, original->SciIrqSelect, params->SciIrqSelect); + fsp_display_upd_value("TcoIrqSelect", 1, original->TcoIrqSelect, params->TcoIrqSelect); + fsp_display_upd_value("TcoIrqEnable", 1, original->TcoIrqEnable, params->TcoIrqEnable); fsp_display_upd_value("LockDownConfigGlobalSmi", 1, original->LockDownConfigGlobalSmi, params->LockDownConfigGlobalSmi); @@ -674,190 +594,127 @@ original->SerialIrqConfigStartFramePulse, params->SerialIrqConfigStartFramePulse); - fsp_display_upd_value("Psi1Threshold[0]", 1, - original->Psi1Threshold[0], + fsp_display_upd_value("Psi1Threshold[0]", 1, original->Psi1Threshold[0], params->Psi1Threshold[0]); - fsp_display_upd_value("Psi1Threshold[1]", 1, - original->Psi1Threshold[1], + fsp_display_upd_value("Psi1Threshold[1]", 1, original->Psi1Threshold[1], params->Psi1Threshold[1]); - fsp_display_upd_value("Psi1Threshold[2]", 1, - original->Psi1Threshold[2], + fsp_display_upd_value("Psi1Threshold[2]", 1, original->Psi1Threshold[2], params->Psi1Threshold[2]); - fsp_display_upd_value("Psi1Threshold[3]", 1, - original->Psi1Threshold[3], + fsp_display_upd_value("Psi1Threshold[3]", 1, original->Psi1Threshold[3], params->Psi1Threshold[3]); - fsp_display_upd_value("Psi1Threshold[4]", 1, - original->Psi1Threshold[4], + fsp_display_upd_value("Psi1Threshold[4]", 1, original->Psi1Threshold[4], params->Psi1Threshold[4]); - fsp_display_upd_value("Psi2Threshold[0]", 1, - original->Psi2Threshold[0], + fsp_display_upd_value("Psi2Threshold[0]", 1, original->Psi2Threshold[0], params->Psi2Threshold[0]); - fsp_display_upd_value("Psi2Threshold[1]", 1, - original->Psi2Threshold[1], + fsp_display_upd_value("Psi2Threshold[1]", 1, original->Psi2Threshold[1], params->Psi2Threshold[1]); - fsp_display_upd_value("Psi2Threshold[2]", 1, - original->Psi2Threshold[2], + fsp_display_upd_value("Psi2Threshold[2]", 1, original->Psi2Threshold[2], params->Psi2Threshold[2]); - fsp_display_upd_value("Psi2Threshold[3]", 1, - original->Psi2Threshold[3], + fsp_display_upd_value("Psi2Threshold[3]", 1, original->Psi2Threshold[3], params->Psi2Threshold[3]); - fsp_display_upd_value("Psi2Threshold[4]", 1, - original->Psi2Threshold[4], + fsp_display_upd_value("Psi2Threshold[4]", 1, original->Psi2Threshold[4], params->Psi2Threshold[4]); - fsp_display_upd_value("Psi3Threshold[0]", 1, - original->Psi3Threshold[0], + fsp_display_upd_value("Psi3Threshold[0]", 1, original->Psi3Threshold[0], params->Psi3Threshold[0]); - fsp_display_upd_value("Psi3Threshold[1]", 1, - original->Psi3Threshold[1], + fsp_display_upd_value("Psi3Threshold[1]", 1, original->Psi3Threshold[1], params->Psi3Threshold[1]); - fsp_display_upd_value("Psi3Threshold[2]", 1, - original->Psi3Threshold[2], + fsp_display_upd_value("Psi3Threshold[2]", 1, original->Psi3Threshold[2], params->Psi3Threshold[2]); - fsp_display_upd_value("Psi3Threshold[3]", 1, - original->Psi3Threshold[3], + fsp_display_upd_value("Psi3Threshold[3]", 1, original->Psi3Threshold[3], params->Psi3Threshold[3]); - fsp_display_upd_value("Psi3Threshold[4]", 1, - original->Psi3Threshold[4], + fsp_display_upd_value("Psi3Threshold[4]", 1, original->Psi3Threshold[4], params->Psi3Threshold[4]); - fsp_display_upd_value("Psi3Enable[0]", 1, - original->Psi3Enable[0], + fsp_display_upd_value("Psi3Enable[0]", 1, original->Psi3Enable[0], params->Psi3Enable[0]); - fsp_display_upd_value("Psi3Enable[1]", 1, - original->Psi3Enable[1], + fsp_display_upd_value("Psi3Enable[1]", 1, original->Psi3Enable[1], params->Psi3Enable[1]); - fsp_display_upd_value("Psi3Enable[2]", 1, - original->Psi3Enable[2], + fsp_display_upd_value("Psi3Enable[2]", 1, original->Psi3Enable[2], params->Psi3Enable[2]); - fsp_display_upd_value("Psi3Enable[3]", 1, - original->Psi3Enable[3], + fsp_display_upd_value("Psi3Enable[3]", 1, original->Psi3Enable[3], params->Psi3Enable[3]); - fsp_display_upd_value("Psi3Enable[4]", 1, - original->Psi3Enable[4], + fsp_display_upd_value("Psi3Enable[4]", 1, original->Psi3Enable[4], params->Psi3Enable[4]); - fsp_display_upd_value("Psi4Enable[0]", 1, - original->Psi4Enable[0], + fsp_display_upd_value("Psi4Enable[0]", 1, original->Psi4Enable[0], params->Psi4Enable[0]); - fsp_display_upd_value("Psi4Enable[1]", 1, - original->Psi4Enable[1], + fsp_display_upd_value("Psi4Enable[1]", 1, original->Psi4Enable[1], params->Psi4Enable[1]); - fsp_display_upd_value("Psi4Enable[2]", 1, - original->Psi4Enable[2], + fsp_display_upd_value("Psi4Enable[2]", 1, original->Psi4Enable[2], params->Psi4Enable[2]); - fsp_display_upd_value("Psi4Enable[3]", 1, - original->Psi4Enable[3], + fsp_display_upd_value("Psi4Enable[3]", 1, original->Psi4Enable[3], params->Psi4Enable[3]); - fsp_display_upd_value("Psi4Enable[4]", 1, - original->Psi4Enable[4], + fsp_display_upd_value("Psi4Enable[4]", 1, original->Psi4Enable[4], params->Psi4Enable[4]); - fsp_display_upd_value("ImonSlope[0]", 1, - original->ImonSlope[0], + fsp_display_upd_value("ImonSlope[0]", 1, original->ImonSlope[0], params->ImonSlope[0]); - fsp_display_upd_value("ImonSlope[1]", 1, - original->ImonSlope[1], + fsp_display_upd_value("ImonSlope[1]", 1, original->ImonSlope[1], params->ImonSlope[1]); - fsp_display_upd_value("ImonSlope[2]", 1, - original->ImonSlope[2], + fsp_display_upd_value("ImonSlope[2]", 1, original->ImonSlope[2], params->ImonSlope[2]); - fsp_display_upd_value("ImonSlope[3]", 1, - original->ImonSlope[3], + fsp_display_upd_value("ImonSlope[3]", 1, original->ImonSlope[3], params->ImonSlope[3]); - fsp_display_upd_value("ImonSlope[4]", 1, - original->ImonSlope[4], + fsp_display_upd_value("ImonSlope[4]", 1, original->ImonSlope[4], params->ImonSlope[4]); - fsp_display_upd_value("ImonOffse[0]t", 1, - original->ImonOffset[0], + fsp_display_upd_value("ImonOffse[0]t", 1, original->ImonOffset[0], params->ImonOffset[0]); - fsp_display_upd_value("ImonOffse[1]t", 1, - original->ImonOffset[1], + fsp_display_upd_value("ImonOffse[1]t", 1, original->ImonOffset[1], params->ImonOffset[1]); - fsp_display_upd_value("ImonOffse[2]t", 1, - original->ImonOffset[2], + fsp_display_upd_value("ImonOffse[2]t", 1, original->ImonOffset[2], params->ImonOffset[2]); - fsp_display_upd_value("ImonOffse[3]t", 1, - original->ImonOffset[3], + fsp_display_upd_value("ImonOffse[3]t", 1, original->ImonOffset[3], params->ImonOffset[3]); - fsp_display_upd_value("ImonOffse[4]t", 1, - original->ImonOffset[4], + fsp_display_upd_value("ImonOffse[4]t", 1, original->ImonOffset[4], params->ImonOffset[4]); - fsp_display_upd_value("IccMax[0]", 1, - original->IccMax[0], + fsp_display_upd_value("IccMax[0]", 1, original->IccMax[0], params->IccMax[0]); - fsp_display_upd_value("IccMax[1]", 1, - original->IccMax[1], + fsp_display_upd_value("IccMax[1]", 1, original->IccMax[1], params->IccMax[1]); - fsp_display_upd_value("IccMax[2]", 1, - original->IccMax[2], + fsp_display_upd_value("IccMax[2]", 1, original->IccMax[2], params->IccMax[2]); - fsp_display_upd_value("IccMax[3]", 1, - original->IccMax[3], + fsp_display_upd_value("IccMax[3]", 1, original->IccMax[3], params->IccMax[3]); - fsp_display_upd_value("IccMax[4]", 1, - original->IccMax[4], + fsp_display_upd_value("IccMax[4]", 1, original->IccMax[4], params->IccMax[4]); - fsp_display_upd_value("VrVoltageLimit[0]", 1, - original->VrVoltageLimit[0], + fsp_display_upd_value("VrVoltageLimit[0]", 1, original->VrVoltageLimit[0], params->VrVoltageLimit[0]); - fsp_display_upd_value("VrVoltageLimit[1]", 1, - original->VrVoltageLimit[1], + fsp_display_upd_value("VrVoltageLimit[1]", 1, original->VrVoltageLimit[1], params->VrVoltageLimit[1]); - fsp_display_upd_value("VrVoltageLimit[2]", 1, - original->VrVoltageLimit[2], + fsp_display_upd_value("VrVoltageLimit[2]", 1, original->VrVoltageLimit[2], params->VrVoltageLimit[2]); - fsp_display_upd_value("VrVoltageLimit[3]", 1, - original->VrVoltageLimit[3], + fsp_display_upd_value("VrVoltageLimit[3]", 1, original->VrVoltageLimit[3], params->VrVoltageLimit[3]); - fsp_display_upd_value("VrVoltageLimit[4]", 1, - original->VrVoltageLimit[4], + fsp_display_upd_value("VrVoltageLimit[4]", 1, original->VrVoltageLimit[4], params->VrVoltageLimit[4]); - fsp_display_upd_value("VrConfigEnable[0]", 1, - original->VrConfigEnable[0], + fsp_display_upd_value("VrConfigEnable[0]", 1, original->VrConfigEnable[0], params->VrConfigEnable[0]); - fsp_display_upd_value("VrConfigEnable[1]", 1, - original->VrConfigEnable[1], + fsp_display_upd_value("VrConfigEnable[1]", 1, original->VrConfigEnable[1], params->VrConfigEnable[1]); - fsp_display_upd_value("VrConfigEnable[2]", 1, - original->VrConfigEnable[2], + fsp_display_upd_value("VrConfigEnable[2]", 1, original->VrConfigEnable[2], params->VrConfigEnable[2]); - fsp_display_upd_value("VrConfigEnable[3]", 1, - original->VrConfigEnable[3], + fsp_display_upd_value("VrConfigEnable[3]", 1, original->VrConfigEnable[3], params->VrConfigEnable[3]); - fsp_display_upd_value("VrConfigEnable[4]", 1, - original->VrConfigEnable[4], + fsp_display_upd_value("VrConfigEnable[4]", 1, original->VrConfigEnable[4], params->VrConfigEnable[4]); - fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, - original->SerialIoI2cVoltage[0], + fsp_display_upd_value("SerialIoI2cVoltage[0]", 1, original->SerialIoI2cVoltage[0], params->SerialIoI2cVoltage[0]); - fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, - original->SerialIoI2cVoltage[1], + fsp_display_upd_value("SerialIoI2cVoltage[1]", 1, original->SerialIoI2cVoltage[1], params->SerialIoI2cVoltage[1]); - fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, - original->SerialIoI2cVoltage[2], + fsp_display_upd_value("SerialIoI2cVoltage[2]", 1, original->SerialIoI2cVoltage[2], params->SerialIoI2cVoltage[2]); - fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, - original->SerialIoI2cVoltage[3], + fsp_display_upd_value("SerialIoI2cVoltage[3]", 1, original->SerialIoI2cVoltage[3], params->SerialIoI2cVoltage[3]); - fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, - original->SerialIoI2cVoltage[4], + fsp_display_upd_value("SerialIoI2cVoltage[4]", 1, original->SerialIoI2cVoltage[4], params->SerialIoI2cVoltage[4]); - fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, - original->SerialIoI2cVoltage[5], + fsp_display_upd_value("SerialIoI2cVoltage[5]", 1, original->SerialIoI2cVoltage[5], params->SerialIoI2cVoltage[5]); - fsp_display_upd_value("SendVrMbxCmd", 1, - original->SendVrMbxCmd, - params->SendVrMbxCmd); - fsp_display_upd_value("AcousticNoiseMitigation", 1, - original->AcousticNoiseMitigation, + fsp_display_upd_value("SendVrMbxCmd", 1, original->SendVrMbxCmd, params->SendVrMbxCmd); + fsp_display_upd_value("AcousticNoiseMitigation", 1, original->AcousticNoiseMitigation, params->AcousticNoiseMitigation); - fsp_display_upd_value("SlowSlewRateForIa", 1, - original->SlowSlewRateForIa, + fsp_display_upd_value("SlowSlewRateForIa", 1, original->SlowSlewRateForIa, params->SlowSlewRateForIa); - fsp_display_upd_value("SlowSlewRateForGt", 1, - original->SlowSlewRateForGt, + fsp_display_upd_value("SlowSlewRateForGt", 1, original->SlowSlewRateForGt, params->SlowSlewRateForGt); - fsp_display_upd_value("SlowSlewRateForSa", 1, - original->SlowSlewRateForSa, + fsp_display_upd_value("SlowSlewRateForSa", 1, original->SlowSlewRateForSa, params->SlowSlewRateForSa); - fsp_display_upd_value("FastPkgCRampDisable", 1, - original->FastPkgCRampDisable, + fsp_display_upd_value("FastPkgCRampDisable", 1, original->FastPkgCRampDisable, params->FastPkgCRampDisable); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1313dc1..1dbe590 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -142,8 +142,7 @@ /* * The following fields come from FspUpdVpd.h. - * These are configuration values that are passed to FSP during - * MemoryInit. + * These are configuration values that are passed to FSP during MemoryInit. */ u64 PlatformMemorySize; u8 SmramMask; @@ -191,9 +190,8 @@ /* SATA related */ u8 EnableSata; enum { - /* Documentation and header files of Skylake FSP disagree on - the values, Kaby Lake FSP (KabylakeFsp0001 on github) uses - these: */ + /* Documentation and header files of Skylake FSP disagree on the values, + * Kaby Lake FSP (KabylakeFsp0001 on github) uses these: */ KBLFSP_SATA_MODE_AHCI = 0, KBLFSP_SATA_MODE_RAID = 1, } SataMode; @@ -224,8 +222,7 @@ /* * Pcie Root Port configuration: - * each element of array corresponds to - * respective PCIe root port. + * each element of array corresponds to respective PCIe root port. */ /* PEG Max Link Width */ @@ -361,8 +358,7 @@ /* * The following fields come from fsp_vpd.h - * These are configuration values that are passed to FSP during - * SiliconInit. + * These are configuration values that are passed to FSP during SiliconInit. */ u32 LogoPtr; u32 LogoSize; @@ -446,8 +442,7 @@ */ u8 PmConfigPciClockRun; /* - * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, - * 1: Enabled + * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled */ u8 PmConfigSlpStrchSusUp; /* @@ -481,8 +476,7 @@ /* * VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; /* diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..87bf644 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -86,14 +86,11 @@ }; /* - * If the PCIe root port at function 0 is disabled, - * the PCIe root ports might be coalesced after FSP silicon init. - * The below function will swap the devfn of the first enabled device - * in devicetree and function 0 resides a pci device - * so that it won't confuse coreboot. + * If the PCIe root port at function 0 is disabled, the PCIe root ports might be coalesced + * after FSP silicon init. The below function will swap the devfn of the first enabled device + * in devicetree and function 0 resides a pci device so that it won't confuse coreboot. */ -static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, - size_t pci_groups) +static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, size_t pci_groups) { struct device *func0; unsigned int devfn, devfn0; @@ -117,18 +114,13 @@ * Then find first enabled device to replace func0 * as that port was move to func0. */ - for (i = 1; i < pcie_rp_group[group].func_count; - i++, devfn += inc) { + for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { struct device *dev = pcidev_path_on_root(devfn); if (dev == NULL || !dev->enabled) continue; - /* - * Found the first enabled device in - * a given dev number. - */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); + /* Found the first enabled device in a given dev number. */ + printk(BIOS_INFO, "PCI func %d was swapped to func 0.\n", i); func0->path.pci.devfn = dev->path.pci.devfn; dev->path.pci.devfn = devfn0; break; @@ -160,8 +152,7 @@ pcie_update_device_tree(&pcie_table_skl_pch_h[0], ARRAY_SIZE(pcie_table_skl_pch_h)); } else { - printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" - " is not found\n", id); + printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x is not found\n", id); return; } } @@ -250,18 +241,12 @@ params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = - config->usb2_ports[i].enable; - params->Usb2OverCurrentPin[i] = - config->usb2_ports[i].ocpin; - params->Usb2AfePetxiset[i] = - config->usb2_ports[i].pre_emp_bias; - params->Usb2AfeTxiset[i] = - config->usb2_ports[i].tx_bias; - params->Usb2AfePredeemp[i] = - config->usb2_ports[i].tx_emp_enable; - params->Usb2AfePehalfbit[i] = - config->usb2_ports[i].pre_emp_bit; + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { @@ -269,8 +254,7 @@ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; - params->Usb3HsioTxDeEmph[i] = - config->usb3_ports[i].tx_de_emp; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; } if (config->usb3_ports[i].tx_downscale_amp) { params->Usb3HsioTxDownscaleAmpEnable[i] = 1; @@ -287,23 +271,20 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); /* - * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for - * all the enabled PCIe root ports, invalid(0x1F) is set for - * disabled PCIe root ports. + * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for all the enabled + * PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. */ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { if (config->PcieRpClkReqSupport[i]) - params->PcieRpClkSrcNumber[i] = - config->PcieRpClkSrcNumber[i]; + params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i]; else params->PcieRpClkSrcNumber[i] = 0x1F; } @@ -344,12 +325,9 @@ params->ScsSdCardEnabled = config->ScsSdCardEnabled; if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; + params->PchScsEmmcHs400DllDataValid = !!config->EmmcHs400DllNeed; + params->PchScsEmmcHs400RxStrobeDll1 = config->ScsEmmcHs400RxStrobeDll1; + params->PchScsEmmcHs400TxDataDll = config->ScsEmmcHs400TxDataDll; } /* If ISH is enabled, enable ISH elements */ @@ -373,9 +351,8 @@ tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; /* - * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree - * setting, we set the appropriate PsfUnlock policy in FSP, + * To disable HECI, the Psf needs to be left unlocked by FSP till end of post sequence. + * Based on the devicetree setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; @@ -384,7 +361,7 @@ params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; /* - * Skip Spi Flash Lockdown from inside FSP. + * Skip SPI Flash Lockdown from inside FSP. * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). * So, it becomes coreboot's responsibility to set this bit @@ -413,8 +390,7 @@ params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; params->PchPmLpcClockRun = config->PmConfigPciClockRun; params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; - params->PchPmPwrBtnOverridePeriod = - config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; /* Indicate whether platform supports Voltage Margining */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..c551df8 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -151,8 +151,7 @@ /* Set long term power limit to TDP */ limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); + tdp_pl1 = ((conf->tdp_pl1_override == 0) ? tdp : (conf->tdp_pl1_override * power_unit)); limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); /* Set PL1 Pkg Power clamp bit */ @@ -182,10 +181,8 @@ if (conf->tdp_psyspl2) { limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); limit.hi = 0; - printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", conf->tdp_psyspl2); + limit.hi |= (conf->tdp_psyspl2 * power_unit) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; @@ -196,20 +193,16 @@ if (conf->tdp_psyspl3) { limit = rdmsr(MSR_PL3_CONTROL); limit.lo = 0; - printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", conf->tdp_psyspl3); + limit.lo |= (conf->tdp_psyspl3 * power_unit) & PKG_POWER_LIMIT_MASK; /* Enable PsysPl3 */ limit.lo |= PKG_POWER_LIMIT_EN; /* set PsysPl3 time window */ limit.lo |= (conf->tdp_psyspl3_time & - PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; + PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; /* set PsysPl3 duty cycle */ limit.lo |= (conf->tdp_psyspl3_dutycycle & - PKG_POWER_LIMIT_DUTYCYCLE_MASK) << - PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; + PKG_POWER_LIMIT_DUTYCYCLE_MASK) << PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; wrmsr(MSR_PL3_CONTROL, limit); } @@ -217,10 +210,8 @@ if (conf->tdp_pl4) { limit = rdmsr(MSR_VR_CURRENT_CONFIG); limit.lo = 0; - printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", - conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & - PKG_POWER_LIMIT_MASK; + printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", conf->tdp_pl4); + limit.lo |= (conf->tdp_pl4 * power_unit) & PKG_POWER_LIMIT_MASK; wrmsr(MSR_VR_CURRENT_CONFIG, limit); } @@ -382,20 +373,17 @@ /* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); /* C-state Interrupt Response Latency Control 4 - package C9 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); /* C-state Interrupt Response Latency Control 5 - package C10 */ msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } @@ -410,8 +398,7 @@ /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer - * frequency is used. + * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; /* Set PM1 timer IO port and enable*/ @@ -424,9 +411,10 @@ void soc_core_init(struct device *cpu) { /* Clear out pending MCEs */ - /* TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. */ + /* + * TODO(adurbin): This should only be done on a cold boot. Also, some of these + * banks are core vs package scope. For now every CPU clears every bank. + */ mca_configure(); /* Enable the local CPU apics */ @@ -481,10 +469,7 @@ /* Set Max Ratio */ cpu_set_max_ratio(); - /* - * Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ + /* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */ smm_southbridge_enable(GBL_EN); /* Lock down the SMRAM space. */ @@ -503,9 +488,8 @@ static const struct mp_ops mp_ops = { /* - * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, - * that are set prior to ramstage. - * Real MTRRs programming are being done after resource allocation. + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, that are set + * prior to ramstage. Real MTRRs programming are being done after resource allocation. */ .pre_mp_init = soc_fsp_load, .get_cpu_count = get_cpu_count, @@ -545,8 +529,7 @@ if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; else - return (msr1.lo & PRMRR_SUPPORTED) && - (current_patch_id == new_patch_id - 1); + return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } void cpu_lock_sgx_memory(void) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 47d6137..2bf9c52 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -52,19 +52,13 @@ #define PME_STS_BIT (1 << 15) #ifdef __SIMPLE_DEVICE__ -static void pch_log_add_elog_event(const struct pme_status_info *info, - pci_devfn_t dev) +static void pch_log_add_elog_event(const struct pme_status_info *info, pci_devfn_t dev) #else -static void pch_log_add_elog_event(const struct pme_status_info *info, - struct device *dev) +static void pch_log_add_elog_event(const struct pme_status_info *info, struct device *dev) #endif { - /* - * If wake source is XHCI, check for detailed wake source events on - * USB2/3 ports. - */ - if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + /* If wake source is XHCI, check for detailed wake source events on USB2/3 ports. */ + if ((info->dev == PCH_DEV_XHCI) && pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return; elog_add_event_wake(info->elog_event, 0); @@ -105,11 +99,10 @@ } /* - * If device is still not found, but the wake source is internal PME, - * try probing XHCI ports to see if any of the USB2/3 ports indicate - * that it was the wake source. This path would be taken in case of GSMI - * logging with S0ix where the pci_pm_resume_noirq runs and clears the - * PME_STS_BIT in controller register. + * If device is still not found, but the wake source is internal PME, try probing XHCI + * ports to see if any of the USB2/3 ports indicate that it was the wake source. This + * path would be taken in case of GSMI logging with S0ix where the pci_pm_resume_noirq + * runs and clears the PME_STS_BIT in controller register. */ if (!dev_found) dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); @@ -155,10 +148,7 @@ if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT)) continue; - /* - * Linux kernel uses PME STS bit information. So do not clear - * this bit. - */ + /* Linux kernel uses PME STS bit information. So do not clear this bit. */ pch_log_add_elog_event(&pme_status_info[i], dev); } } @@ -234,8 +224,7 @@ } /* TCO Timeout */ - if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + if (ps->prev_sleep_state != ACPI_S3 && ps->tco2_sts & TCO_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ @@ -253,11 +242,9 @@ /* ACPI Wake Event */ if (ps->prev_sleep_state != ACPI_S0) { if (deep_sx) - elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, - ps->prev_sleep_state); + elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, ps->prev_sleep_state); else - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - ps->prev_sleep_state); + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); } } diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 8afaf4d..633c347 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -79,8 +79,7 @@ config = config_of(dev); /* - * Set low maximum temp value used for dynamic thermal sensor - * shutdown consideration. + * Set low maximum temp value used for dynamic thermal sensor shutdown consideration. * * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c index a4c3726..b5d5e33 100644 --- a/src/soc/intel/skylake/fspcar.c +++ b/src/soc/intel/skylake/fspcar.c @@ -23,12 +23,9 @@ .Reserved = {0}, }, .FsptCoreUpd = { - .MicrocodeRegionBase = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, - .MicrocodeRegionSize = - (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .MicrocodeRegionBase = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, }, }; diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..3a211ac 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -176,17 +176,14 @@ return routes; } -uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, - int dw_reg, uint32_t reg_val) +uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { if (CONFIG(SKYLAKE_SOC_PCH_H)) return reg_val; - /* - * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 - * ~ GPP_F11. - */ + + /* For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 ~ GPP_F11. */ if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1) reg_val = reg_val & ~(PAD_CFG1_TOL_1V8); - return reg_val; + return reg_val; } diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c06893e..fae6469 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -63,11 +63,10 @@ write32(base + PCH_PP_DIVISOR, reg32); /* So far all devices seem to use the PCH PWM function. - The CPU PWM registers are all zero after reset. */ + The CPU PWM registers are all zero after reset. */ if (conf->gpu_pch_backlight_pwm_hz) { - /* Reference clock is 24MHz. We can choose either a 16 - or a 128 step increment. Use 16 if we would have less - than 100 steps otherwise. */ + /* Reference clock is 24MHz. We can choose either a 16 or a 128 step increment. + * Use 16 if we would have less than 100 steps otherwise. */ const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; unsigned int pwm_increment, pwm_period; u32 south_chicken1; @@ -82,15 +81,12 @@ } write32(base + SOUTH_CHICKEN1, south_chicken1); - pwm_period = 24 * 1000 * 1000 / pwm_increment - / conf->gpu_pch_backlight_pwm_hz; + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; /* Start with a 50% duty cycle. */ - write32(base + BLC_PWM_PCH_CTL2, - pwm_period << 16 | pwm_period / 2); + write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); write32(base + BLC_PWM_PCH_CTL1, - !!conf->gpu_pch_backlight_polarity << 29 | - BLM_PCH_PWM_ENABLE); + !!conf->gpu_pch_backlight_polarity << 29 | BLM_PCH_PWM_ENABLE); } } @@ -101,9 +97,8 @@ graphics_setup_panel(dev); /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver does not execute. + * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. This will allow the + * kernel to use 4-lane eDP links properly if the VBIOS or GOP driver does not execute. */ ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { @@ -117,12 +112,9 @@ pci_write_config32(dev, PCI_COMMAND, reg32); /* - * GFX PEIM module inside FSP binary is taking care of graphics - * initialization based on RUN_FSP_GOP Kconfig option and input - * VBT file. - * - * In case of non-FSP solution, SoC need to select another - * Kconfig to perform GFX initialization. + * GFX PEIM module inside FSP binary is taking care of graphics initialization based on + * RUN_FSP_GOP Kconfig option and input VBT file. In case of non-FSP solution, SoC need + * to select another Kconfig to perform GFX initialization. */ if (CONFIG(RUN_FSP_GOP)) { /* nothing to do */ @@ -159,8 +151,8 @@ /* FIXME: Add platform specific mailbox initialization */ } -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) +uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, + struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index c39c066..f883ee5 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -30,9 +30,9 @@ unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); void southbridge_inject_dsdt(struct device *device); -unsigned long southbridge_write_acpi_tables(struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); -unsigned long northbridge_write_acpi_tables(struct device *, - unsigned long current, struct acpi_rsdp *); +unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long current, + struct acpi_rsdp *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 0681f78..7455999 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -42,8 +42,7 @@ /* Common Timer Copy (CTC) frequency - 24MHz. */ #define CTC_FREQ 24000000 -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) +#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 13a0a7a..3bfaba5 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -18,8 +18,8 @@ #define _SOC_GPIO_H_ #include <soc/gpio_defs.h> -#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in - soc/gpio_defs.h */ +/* intelblocks/gpio.h depends on definitions in soc/gpio_defs.h */ +#include <intelblocks/gpio.h> #define CROS_GPIO_DEVICE_NAME "INT344B:00" #endif diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..e012e3a 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -35,10 +35,8 @@ #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) #define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM3_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS)) + ((NUM_GPIO_COM0_GPI_REGS) + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) + (NUM_GPIO_COM2_GPI_REGS)) /* * IOxAPIC IRQs for the GPIOs @@ -220,9 +218,9 @@ /* Register defines. */ #define GPIO_MISCCFG 0x10 -#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 -#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 #define HOSTSW_OWN_REG_0 0xd0 #define PAD_CFG_BASE 0x400 #define GPI_INT_STS_0 0x100 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c73d766..f1220de 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -22,8 +22,8 @@ /* * Memory-mapped I/O registers. */ -#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 -#define PCH_PRESERVED_BASE_SIZE 0x02000000 +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 #define EARLY_I2C_BASE_ADDRESS 0xfe040000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index a25e5ac..82de495 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -43,8 +43,8 @@ int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels); /* - * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0 - * on error. + * Add nau88l25 headset codec on provided SSP link. + * Return 0 on succes, < 0 on error. */ int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink); @@ -72,8 +72,8 @@ int nhlt_soc_add_rt5514(struct nhlt *nhlt, int hwlink, int num_channels); /* - * Add rt5663 headset codec on provided SSP link. Return 0 on success, < 0 - * on error. + * Add rt5663 headset codec on provided SSP link. + * Return 0 on success, < 0 on error. */ int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink); @@ -84,8 +84,8 @@ int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); /* - * Add da7219 headset codec on provided SSP link. Return 0 on success, < 0 - * on error. + * Add da7219 headset codec on provided SSP link. + * Return 0 on success, < 0 on error. */ int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 615edac..a220d8c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -145,8 +145,7 @@ * - on microcontroller writes (io 0x62/0x66) * - on TCO events */ -#define ENABLE_SMI_PARAMS \ - (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) +#define ENABLE_SMI_PARAMS (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) /* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ #define ETR 0xac diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 88ce9e3..96faace 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -30,9 +30,8 @@ msr_t smrr_base; msr_t smrr_mask; /* - * The smm_save_state_in_msrs field indicates if SMM save state - * locations live in MSRs. This indicates to the CPUs how to adjust - * the SMMBASE and IEDBASE + * The smm_save_state_in_msrs field indicates if SMM save state locations live in MSRs. + * This indicates to the CPUs how to adjust the SMMBASE and IEDBASE */ int smm_save_state_in_msrs; }; diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index aebbbdf..2fa6f9f 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -27,15 +27,10 @@ struct vr_config { - /* - * The below settings will take effect when this is set to 1 - * for that domain. - */ + /* The below settings will take effect when this is set to 1 for that domain. */ int vr_config_enable; - /* Power State X current cutoff in 1/4 Amp increments - * Range is 0-128A - */ + /* Power State X current cutoff in 1/4 Amp increments Range is 0-128A */ int psi1threshold; int psi2threshold; int psi3threshold; @@ -45,8 +40,8 @@ int psi4enable; /* - * Imon slope correction. Specified in 1/100 increment - * values. Range is 0-200. 125 = 1.25 + * Imon slope correction. Specified in 1/100 increment values. + * Range is 0-200. 125 = 1.25 */ int imon_slope; @@ -72,8 +67,7 @@ #if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains - * 0 = System Agent, 1 = IA Core, 2 = Ring, - * 3 = GT unsliced, 4 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced */ enum vr_domain { VR_SYSTEM_AGENT, @@ -85,8 +79,7 @@ }; #else /* VrConfig Settings for 4 domains - * 0 = System Agent, 1 = IA Core, - * 2 = GT unsliced, 3 = GT sliced + * 0 = System Agent, 1 = IA Core, 2 = GT unsliced, 3 = GT sliced */ enum vr_domain { VR_SYSTEM_AGENT, @@ -97,6 +90,5 @@ }; #endif -void fill_vr_domain_config(void *params, - int domain, const struct vr_config *cfg); +void fill_vr_domain_config(void *params, int domain, const struct vr_config *cfg); #endif diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ddaffda..8ce0f78 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -24,198 +24,143 @@ #include <string.h> static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { - /* - * cAVS(Audio, Voice, Speech), INTA is default, programmed in - * PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), - /* - * SMBus Controller, no default value, programmed in - * PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* cAVS(Audio, Voice, Speech), INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + + /* SMBus Controller, no default value, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), - /* - * SerialIo: UART #0, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[7] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), - /* - * SerialIo: UART #1, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[8] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), - /* - * SerialIo: SPI #0, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[10] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), - /* - * SerialIo: SPI #1, INTA is default, - * programmed in PCR[SERIALIO] + PCICFGCTRL[11] - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + + /* SerialIo: UART #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[7] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART0), int_A, + LPSS_UART0_IRQ), + + /* SerialIo: UART #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[8] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_UART1), int_B, + LPSS_UART1_IRQ), + + /* SerialIo: SPI #0, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[10] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI0), int_C, + LPSS_SPI0_IRQ), + + /* SerialIo: SPI #1, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[11] */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_GSPI1), int_D, + LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), - /* PCI Express Port, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), - /* - * PCI Express Port 1, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), - /* - * PCI Express Port 2, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), - /* - * PCI Express Port 3, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), - /* - * PCI Express Port 4, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), - /* - * PCI Express Port 5, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), - /* - * PCI Express Port 6, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), - /* - * PCI Express Port 7, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), - /* - * PCI Express Port 8, INT is default, - * programmed in PciCfgSpace + FCh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + + /* PCI Express Port, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + + /* PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + + /* PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + + /* PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + + /* PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + + /* PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + + /* PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + + /* PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + + /* PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* * SerialIo UART Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[9] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), /* * SerialIo UART Controller #5, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[6] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), /* * SerialIo UART Controller #4, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[5] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), - /* - * SATA Controller, INTA is default, - * programmed in PciCfgSpace + 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, - PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + + /* SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + /* * SerialIo I2C Controller #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[1] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), /* * SerialIo I2C Controller #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[2] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), /* * SerialIo I2C Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[3] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), /* * SerialIo I2C Controller #3, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[4] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), - /* - * USB 3.0 xHCI Controller, no default value, - * programmed in PciCfgSpace 3Dh - */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + + /* USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + /* Camera IO Host Controller */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, - PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) }; void soc_irq_settings(FSP_SIL_UPD *params) @@ -229,9 +174,8 @@ /* Get Device Int Count */ intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ - memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) - (params->DevIntConfigPtr), devintconfig, intdeventry * - sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); + memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr), + devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); params->NumOfDevIntConfig = intdeventry; /* PxRC to IRQ programming */ diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584..b838c5c 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -93,38 +93,22 @@ /* HFSTS2[27:24] Power Management Event */ static const char *const me_pmevent_values[] = { - [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = - "Clean Moff->Mx wake", - [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = - "Moff->Mx wake after an error", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = - "Clean global reset", - [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = - "Global reset after an error", - [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = - "Clean Intel ME reset", - [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = - "Intel ME reset due to exception", - [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = - "Pseudo-global reset", - [ME_HFS2_PMEVENT_CM0_CM3] = - "CM0->CM3", - [ME_HFS2_PMEVENT_CM3_CM0] = - "CM3->CM0", - [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = - "Non-power cycle reset", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = - "Power cycle reset through M3", - [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = - "Power cycle reset through Moff", - [ME_HFS2_PMEVENT_CMX_CMOFF] = - "Cx/Mx->Cx/Moff", - [ME_HFS2_PMEVENT_CM0_CM0PG] = - "CM0->CM0PG", - [ME_HFS2_PMEVENT_CM3_CM3PG] = - "CM3->CM3PG", - [ME_HFS2_PMEVENT_CM0PG_CM0] = - "CM0PG->CM0" + [ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE] = "Clean Moff->Mx wake", + [ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR] = "Moff->Mx wake after an error", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET] = "Clean global reset", + [ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR] = "Global reset after an error", + [ME_HFS2_PMEVENT_CLEAN_ME_RESET] = "Clean Intel ME reset", + [ME_HFS2_PMEVENT_ME_RESET_EXCEPTION] = "Intel ME reset due to exception", + [ME_HFS2_PMEVENT_PSEUDO_ME_RESET] = "Pseudo-global reset", + [ME_HFS2_PMEVENT_CM0_CM3] = "CM0->CM3", + [ME_HFS2_PMEVENT_CM3_CM0] = "CM3->CM0", + [ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET] = "Non-power cycle reset", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3] = "Power cycle reset through M3", + [ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF] = "Power cycle reset through Moff", + [ME_HFS2_PMEVENT_CMX_CMOFF] = "Cx/Mx->Cx/Moff", + [ME_HFS2_PMEVENT_CM0_CM0PG] = "CM0->CM0PG", + [ME_HFS2_PMEVENT_CM3_CM3PG] = "CM3->CM3PG", + [ME_HFS2_PMEVENT_CM0PG_CM0] = "CM0PG->CM0" }; @@ -136,70 +120,41 @@ /* Progress Code 1 states */ static const char *const me_progress_bup_values[] = { - [ME_HFS2_STATE_BUP_INIT] = - "Initialization starts", - [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = - "Disable the host wake event", - [ME_HFS2_STATE_BUP_CG_ENABLE] = - "Enabling CG for cset", - [ME_HFS2_STATE_BUP_PM_HND_EN] = - "Enabling PM handshaking", - [ME_HFS2_STATE_BUP_FLOW_DET] = - "Flow determination start process", - [ME_HFS2_STATE_BUP_PMC_PATCHING] = - "PMC Patching process", - [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = - "Get VSCC params", - [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = - "Set VSCC params", + [ME_HFS2_STATE_BUP_INIT] = "Initialization starts", + [ME_HFS2_STATE_BUP_DIS_HOST_WAKE] = "Disable the host wake event", + [ME_HFS2_STATE_BUP_CG_ENABLE] = "Enabling CG for cset", + [ME_HFS2_STATE_BUP_PM_HND_EN] = "Enabling PM handshaking", + [ME_HFS2_STATE_BUP_FLOW_DET] = "Flow determination start process", + [ME_HFS2_STATE_BUP_PMC_PATCHING] = "PMC Patching process", + [ME_HFS2_STATE_BUP_GET_FLASH_VSCC] = "Get VSCC params", + [ME_HFS2_STATE_BUP_SET_FLASH_VSCC] = "Set VSCC params", [ME_HFS2_STATE_BUP_VSCC_ERR] = - "Error reading/matching the VSCC table in the descriptor", - [ME_HFS2_STATE_BUP_EFSS_INIT] = - "Initialize EFFS", - [ME_HFS2_STATE_BUP_CHECK_STRAP] = - "Check to see if straps say ME DISABLED", - [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = - "Timeout waiting for PWROK", - [ME_HFS2_STATE_BUP_STRAP_DIS] = - "EFFS says ME disabled", + "Error reading/matching the VSCC table in the descriptor", + [ME_HFS2_STATE_BUP_EFSS_INIT] = "Initialize EFFS", + [ME_HFS2_STATE_BUP_CHECK_STRAP] = "Check to see if straps say ME DISABLED", + [ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT] = "Timeout waiting for PWROK", + [ME_HFS2_STATE_BUP_STRAP_DIS] = "EFFS says ME disabled", [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = - "Possibly handle BUP manufacturing override strap", - [ME_HFS2_STATE_BUP_M3] = - "Bringup in M3", - [ME_HFS2_STATE_BUP_M0] = - "Bringup in M0", - [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = - "Flow detection error", - [ME_HFS2_STATE_BUP_M3_CLK_ERR] = - "M3 clock switching error", + "Possibly handle BUP manufacturing override strap", + [ME_HFS2_STATE_BUP_M3] = "Bringup in M3", + [ME_HFS2_STATE_BUP_M0] = "Bringup in M0", + [ME_HFS2_STATE_BUP_FLOW_DET_ERR] = "Flow detection error", + [ME_HFS2_STATE_BUP_M3_CLK_ERR] = "M3 clock switching error", [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = - "Host error - CPU reset timeout, DID timeout, memory missing", - [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = - "M3 kernel load", - [ME_HFS2_STATE_BUP_T32_MISSING] = - "T34 missing - cannot program ICC", - [ME_HFS2_STATE_BUP_WAIT_DID] = - "Waiting for DID BIOS message", - [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = - "Waiting for DID BIOS message failure", - [ME_HFS2_STATE_BUP_DID_NO_FAIL] = - "DID reported no error", - [ME_HFS2_STATE_BUP_ENABLE_UMA] = - "Enabling UMA", - [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = - "Enabling UMA error", - [ME_HFS2_STATE_BUP_SEND_DID_ACK] = - "Sending DID Ack to BIOS", - [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = - "Sending DID Ack to BIOS error", - [ME_HFS2_STATE_BUP_M0_CLK] = - "Switching clocks in M0", - [ME_HFS2_STATE_BUP_M0_CLK_ERR] = - "Switching clocks in M0 error", - [ME_HFS2_STATE_BUP_TEMP_DIS] = - "ME in temp disable", - [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = - "M0 kernel load", + "Host error - CPU reset timeout, DID timeout, memory missing", + [ME_HFS2_STATE_BUP_M3_KERN_LOAD] = "M3 kernel load", + [ME_HFS2_STATE_BUP_T32_MISSING] = "T34 missing - cannot program ICC", + [ME_HFS2_STATE_BUP_WAIT_DID] = "Waiting for DID BIOS message", + [ME_HFS2_STATE_BUP_WAIT_DID_FAIL] = "Waiting for DID BIOS message failure", + [ME_HFS2_STATE_BUP_DID_NO_FAIL] = "DID reported no error", + [ME_HFS2_STATE_BUP_ENABLE_UMA] = "Enabling UMA", + [ME_HFS2_STATE_BUP_ENABLE_UMA_ERR] = "Enabling UMA error", + [ME_HFS2_STATE_BUP_SEND_DID_ACK] = "Sending DID Ack to BIOS", + [ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR] = "Sending DID Ack to BIOS error", + [ME_HFS2_STATE_BUP_M0_CLK] = "Switching clocks in M0", + [ME_HFS2_STATE_BUP_M0_CLK_ERR] = "Switching clocks in M0 error", + [ME_HFS2_STATE_BUP_TEMP_DIS] = "ME in temp disable", + [ME_HFS2_STATE_BUP_M0_KERN_LOAD] = "M0 kernel load", }; static void print_me_version(void *unused) @@ -258,8 +213,7 @@ */ heci_reset(); - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, - HECI_MKHI_ADD)) + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, HECI_MKHI_ADD)) goto failed; if (!heci_receive(&resp, &resp_size)) @@ -293,18 +247,14 @@ hfs3.data = me_read_config32(PCI_ME_HFSTS3); hfs6.data = me_read_config32(PCI_ME_HFSTS6); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", - hfs.data); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", - hfs2.data); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", - hfs3.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 1 : 0x%08X\n", hfs.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 2 : 0x%08X\n", hfs2.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 3 : 0x%08X\n", hfs3.data); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 4 : 0x%08X\n", me_read_config32(PCI_ME_HFSTS4)); printk(BIOS_DEBUG, "ME: Host Firmware Status Register 5 : 0x%08X\n", me_read_config32(PCI_ME_HFSTS5)); - printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", - hfs6.data); + printk(BIOS_DEBUG, "ME: Host Firmware Status Register 6 : 0x%08X\n", hfs6.data); /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs.fields.fpt_bad ? "BAD" : "OK"); @@ -344,12 +294,10 @@ printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (hfs2.fields.progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ - if (hfs2.fields.current_state - < ARRAY_SIZE(me_progress_rom_values) + if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_rom_values) && me_progress_rom_values[hfs2.fields.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_rom_values[ - hfs2.fields.current_state]); + me_progress_rom_values[hfs2.fields.current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; @@ -359,12 +307,10 @@ break; case ME_HFS2_PHASE_BUP: /* Bringup Phase */ - if (hfs2.fields.current_state - < ARRAY_SIZE(me_progress_bup_values) + if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_bup_values) && me_progress_bup_values[hfs2.fields.current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[ - hfs2.fields.current_state]); + me_progress_bup_values[hfs2.fields.current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state); break; @@ -417,8 +363,7 @@ printk(BIOS_DEBUG, "Corporate\n"); break; default: - printk(BIOS_DEBUG, "Unknown (0x%x)\n", - hfs3.fields.fw_sku); + printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3.fields.fw_sku); } } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 4c3c58a..acd5e92 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -40,8 +40,7 @@ static bool is_ptt_enable(void) { - if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == - PTT_PRESENT) + if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == PTT_PRESENT) return true; return false; @@ -80,8 +79,7 @@ } /* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) +static size_t get_prmrr_size(uintptr_t dram_base, const struct soc_intel_skylake_config *config) { uintptr_t prmrr_base = dram_base; size_t prmrr_size; @@ -95,12 +93,10 @@ return 0; /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. + * PRMRR Sizes that are > 1MB and < 32MB are not supported and will fail out. */ if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); + die("PRMRR Sizes that are > 1MB and < 32MB are not supported!\n"); prmrr_base -= prmrr_size; if (prmrr_size >= 32*MiB) diff --git a/src/soc/intel/skylake/nhlt/nau88l25.c b/src/soc/intel/skylake/nhlt/nau88l25.c index dd91435..7dd82fa 100644 --- a/src/soc/intel/skylake/nhlt/nau88l25.c +++ b/src/soc/intel/skylake/nhlt/nau88l25.c @@ -15,8 +15,7 @@ #include <soc/nhlt.h> -/* The same DSP firmware settings are used for both the capture and - * render endpoints. */ +/* The same DSP firmware settings are used for both the capture and render endpoints. */ static const struct nhlt_format_config nau88l25_formats[] = { /* 48 KHz 24-bits per sample. */ { diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index 9c48c7b..5be881c 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -53,8 +53,7 @@ { switch (num_channels) { case 4: - return nhlt_add_ssp_endpoints(nhlt, hwlink, - rt5514_4ch_descriptors, + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5514_4ch_descriptors, ARRAY_SIZE(rt5514_4ch_descriptors)); default: return -1; diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c index c5a3f53..a308265 100644 --- a/src/soc/intel/skylake/nhlt/rt5663.c +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -16,8 +16,7 @@ #include <soc/nhlt.h> /* - * The same DSP firmware settings are used for both the capture and - * render endpoints. + * The same DSP firmware settings are used for both the capture and render endpoints. */ static const struct nhlt_format_config rt5663_formats[] = { /* 48 KHz 24-bits per sample. */ diff --git a/src/soc/intel/skylake/p2sb.c b/src/soc/intel/skylake/p2sb.c index c1e9118..f118b38 100644 --- a/src/soc/intel/skylake/p2sb.c +++ b/src/soc/intel/skylake/p2sb.c @@ -31,14 +31,13 @@ * Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband * access for MIPI controller. */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | - (1 << 16) | (1 << 10) | (1 << 1); + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) | (1 << 16) | + (1 << 10) | (1 << 1); ep_mask[P2SB_EP_MASK_5_REG] = mask; /* - * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband - * access for XHCI controller. + * Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband access for XHCI controller. */ mask = (1 << 6) | (1 << 5); diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe0605..65075ea 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -48,8 +48,7 @@ } /* - * Set which power state system will be after reapplying - * the power (from G3 State) + * Set which power state system will be after reapplying the power (from G3 State) */ void pmc_soc_set_afterg3_en(const bool on) { @@ -84,10 +83,8 @@ static const struct reg_script pch_pmc_misc_init_script[] = { /* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */ - REG_PCI_RMW16(GEN_PMCON_B, - ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), - S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | - DIS_SLP_X_STRCH_SUS_UP), + REG_PCI_RMW16(GEN_PMCON_B, ~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK), + S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP), /* Enable SCI and clear SLP requests. */ REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), REG_SCRIPT_END @@ -107,8 +104,7 @@ uint32_t reg; uint8_t *pmcbase = pmc_mmio_regs(); - printk(BIOS_DEBUG, "%sabling Deep S%c\n", - enable ? "En" : "Dis", sx + '0'); + printk(BIOS_DEBUG, "%sabling Deep S%c\n", enable ? "En" : "Dis", sx + '0'); reg = read32(pmcbase + offset); if (enable) reg |= mask; @@ -168,12 +164,10 @@ static void pm1_enable_pwrbtn_smi(void *unused) { /* - * Enable power button SMI only before jumping to payload. This ensures - * that: + * Enable power button SMI only before jumping to payload. This ensures that: * 1. Power button SMI is enabled only after coreboot is done. - * 2. On resume path, power button SMI is not enabled and thus avoids - * any shutdowns because of power button presses due to power button - * press in resume path. + * 2. On resume path, power button SMI is not enabled and thus avoids any shutdowns + * because of power button presses due to power button press in resume path. */ pmc_update_pm1_enable(PWRBTN_EN); } @@ -181,10 +175,9 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); /* - * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in - * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable - * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE# - * pin. + * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in deep_sx_config. + * If WAKE# pin is not enabled, then PCI Express Wake Disable bit needs to be set + * in PM1_EN to avoid unnecessary wakes caused by WAKE# pin. */ static void pm1_handle_wake_pin(void *unused) { diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b03..ee3c74d 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -212,22 +212,18 @@ } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { /* - * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. + * Check for any power failure to determine if this a wake from S5 because + * the PCH does not set the WAK_STS bit when waking from a true G3 state. */ - if (!(ps->pm1_sts & WAK_STS) && - (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) + if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5; /* - * If waking from S3 determine if deep S3 is enabled. If not, - * need to check both deep sleep well and normal suspend well. - * Otherwise just check deep sleep well. + * If waking from S3 determine if deep S3 is enabled. If not, need to check both + * deep sleep well and normal suspend well. Otherwise just check deep sleep well. */ if (prev_sleep_state == ACPI_S3) { /* PWR_FLR represents deep sleep power well loss. */ @@ -250,8 +246,7 @@ ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); @@ -260,8 +255,7 @@ ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); - printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", - ps->gen_pmcon_a, ps->gen_pmcon_b); + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", ps->gen_pmcon_a, ps->gen_pmcon_b); printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index ff1a959..a87ce47 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -24,14 +24,12 @@ static void do_force_global_reset(void) { /* - * BIOS should ensure it does a global reset - * to reset both host and Intel ME by setting - * PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] + * BIOS should ensure it does a global reset to reset both host and + * Intel ME by setting PCH PMC [B0:D31:F2 register offset 0x1048 bit 20] */ pmc_global_reset_enable(true); - /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port - * to global reset platform */ + /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port to global reset platform */ do_full_reset(); } @@ -39,7 +37,7 @@ { if (send_global_reset() != 0) { /* If ME unable to reset platform then - * force global reset using PMC CF9GR register*/ + * force global reset using PMC CF9GR register */ do_force_global_reset(); } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2d0de2f..e1e3ad0 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -51,8 +51,7 @@ } /* UPD parameters to be initialized before MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) { const struct soc_intel_skylake_config *config; @@ -61,11 +60,10 @@ config = config_of_path(PCH_DEVFN_LPC); /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake does not - * have access to the bios_reserved range so it always assumes 8MB is - * used and so the kernel will avoid the last 8MB of the stolen window. - * With the default stolen size of 32MB(-8MB) there is not enough space - * for FBC to work with a high resolution panel. + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have access to + * the bios_reserved range so it always assumes 8MB is used and so the kernel will + * avoid the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB), + * there is not enough space for FBC to work with a high resolution panel. */ upd->IgdDvmt50PreAlloc = 2; @@ -90,34 +88,25 @@ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); + memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param); memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { /* Display the parameters for MemoryInit */ printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - fsp_display_upd_value("PlatformMemorySize", 8, - old->PlatformMemorySize, new->PlatformMemorySize); - fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, - new->MemorySpdPtr00); - fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, - new->MemorySpdPtr01); - fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, - new->MemorySpdPtr10); - fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, - new->MemorySpdPtr11); + fsp_display_upd_value("PlatformMemorySize", 8, old->PlatformMemorySize, + new->PlatformMemorySize); + fsp_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00, new->MemorySpdPtr00); + fsp_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01, new->MemorySpdPtr01); + fsp_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10, new->MemorySpdPtr10); + fsp_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11, new->MemorySpdPtr11); fsp_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen, new->MemorySpdDataLen); fsp_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0], @@ -208,46 +197,32 @@ new->RcompResistor[1]); fsp_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2], new->RcompResistor[2]); - fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], - new->RcompTarget[0]); - fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], - new->RcompTarget[1]); - fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], - new->RcompTarget[2]); - fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], - new->RcompTarget[3]); - fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], - new->RcompTarget[4]); - fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, - new->CaVrefConfig); + fsp_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0], new->RcompTarget[0]); + fsp_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1], new->RcompTarget[1]); + fsp_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2], new->RcompTarget[2]); + fsp_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3], new->RcompTarget[3]); + fsp_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4], new->RcompTarget[4]); + fsp_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig, new->CaVrefConfig); fsp_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask); - fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, - new->MrcFastBoot); + fsp_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot, new->MrcFastBoot); fsp_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); fsp_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); fsp_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); - fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, - new->EnableTraceHub); + fsp_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub); fsp_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, new->IgdDvmt50PreAlloc); - fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, - new->InternalGfx); - fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, - new->ApertureSize); + fsp_display_upd_value("InternalGfx", 1, old->InternalGfx, new->InternalGfx); + fsp_display_upd_value("ApertureSize", 1, old->ApertureSize, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); - fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, - new->FspCarBase); - fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, - new->FspCarSize); + fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, new->FspCarBase); + fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, new->FspCarSize); } /* SOC initialization after RAM is enabled. */ void soc_after_ram_init(struct romstage_params *params) { - /* Set the DISB as soon as possible after DRAM - * init and MRC cache is saved. - */ + /* Set the DISB as soon as possible after DRAM init and MRC cache is saved. */ pmc_set_disb(); } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index ecd1428..c517d1f 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -60,22 +60,16 @@ struct dimm_info *dest_dimm; struct memory_info *mem_info; const MEMORY_INFO_DATA_HOB *memory_info_hob; - const uint8_t smbios_memory_info_guid[16] = - FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; /* Locate the memory info HOB, presence validated by raminit */ - memory_info_hob = - fsp_find_extension_hob_by_guid(smbios_memory_info_guid, - &hob_size); + memory_info_hob = fsp_find_extension_hob_by_guid(smbios_memory_info_guid, &hob_size); if (memory_info_hob == NULL || hob_size == 0) { printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } - /* - * Allocate CBMEM area for DIMM information used to populate SMBIOS - * table 17 - */ + /* Allocate CBMEM area for DIMM information used to populate SMBIOS table 17 */ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); if (mem_info == NULL) { printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); @@ -165,8 +159,7 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } -static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, - FSP_M_TEST_CONFIG *m_t_cfg, +static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, FSP_M_TEST_CONFIG *m_t_cfg, const struct soc_intel_skylake_config *config) { const struct device *dev; @@ -177,8 +170,7 @@ * device pci 01.0 on end # enable PEG0 root port * device pci 01.1 off end # do not configure PEG1 * - * If PEG port is not defined in the device tree, it will be disabled - * in FSP + * If PEG port is not defined in the device tree, it will be disabled in FSP */ dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ if (!dev || !dev->enabled) @@ -239,7 +231,7 @@ m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) - mask |= (1<<i); + mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; @@ -269,12 +261,11 @@ } else { m_cfg->InternalGfx = 1; /* - * Set IGD stolen size to 64MB. The FBC hardware for skylake - * does not have access to the bios_reserved range so it always - * assumes 8MB is used and so the kernel will avoid the last - * 8MB of the stolen window. With the default stolen size of - * 32MB(-8MB) there is not enough space for FBC to work with - * a high resolution panel + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not have + * access to the bios_reserved range so it always assumes 8MB is used and so + * the kernel will avoid the last 8MB of the stolen window. With the default + * stolen size of 32MB(-8MB) there is not enough space for FBC to work with + * a high resolution panel. */ m_cfg->IgdDvmt50PreAlloc = 2; } @@ -324,14 +315,10 @@ /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); + memory_cfg->MmaTestContentPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); + memory_cfg->MmaTestContentSize = region_device_sz(&mma_cfg->test_content); + memory_cfg->MmaTestConfigPtr = (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); + memory_cfg->MmaTestConfigSize = region_device_sz(&mma_cfg->test_param); memory_cfg->MrcFastBoot = 0x00; memory_cfg->SaGv = 0x02; } diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea24..48884ec 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -33,8 +33,7 @@ if (config->ignore_vtd) return; - const bool vtd_capable = - !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); if (!vtd_capable) return; @@ -58,11 +57,9 @@ }; /* Set Fixed MMIO address into PCI configuration space */ - sa_set_pci_bar(soc_fixed_pci_resources, - ARRAY_SIZE(soc_fixed_pci_resources)); + sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources)); /* Set Fixed MMIO address into MCH base address */ - sa_set_mch_bar(soc_fixed_mch_resources, - ARRAY_SIZE(soc_fixed_mch_resources)); + sa_set_mch_bar(soc_fixed_mch_resources, ARRAY_SIZE(soc_fixed_mch_resources)); systemagent_vtd_init(); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..b4f16e9 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -27,19 +27,15 @@ void smihandler_soc_check_illegal_access(uint32_t tco_sts) { - if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) - && fast_spi_wpd_status())) + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) && fast_spi_wpd_status())) return; /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS + * BWE is RW, so the SMI was caused by a write to BWE, not by a write to the BIOS * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. + * This is the place where we notice someone is trying to tinker with the BIOS. + * We are trying to be nice and just ignore it. A more resolute answer would be + * to power down the box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); fast_spi_enable_wp(); @@ -48,8 +44,7 @@ /* SMI handlers that should be serviced in SCI mode too. */ uint32_t smihandler_soc_get_sci_mask(void) { - uint32_t sci_mask = - SMI_HANDLER_SCI_EN(APM_STS_BIT) | + uint32_t sci_mask = SMI_HANDLER_SCI_EN(APM_STS_BIT) | SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); return sci_mask; diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..f92d3f4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -46,23 +46,20 @@ wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask); } -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, +static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; /* - * The relocated handler runs with all CPUs concurrently. Therefore - * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. + * The relocated handler runs with all CPUs concurrently. Therefore stagger + * the entry points adjusting SMBASE downwards by save state size * CPU num. */ smbase = staggered_smbase; iedbase = relo_params->ied_base; - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", smbase, iedbase); /* * All threads need to set IEDBASE and SMBASE to the relocated @@ -93,8 +90,7 @@ } else { em64t101_smm_state_save_area_t *save_state; - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - - sizeof(*save_state)); + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -120,12 +116,10 @@ } /* - * The relocation work is actually performed in SMM context, but the code - * resides in the ramstage module. This occurs by trampolining from the default - * SMRAM entry point to here. + * The relocation work is actually performed in SMM context, but the code resides in the + * ramstage module. This occurs by trampolining from the default SMRAM entry point to here. */ -void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { msr_t mtrr_cap; struct smm_relocation_params *relo_params = &smm_reloc_params; @@ -133,18 +127,15 @@ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu); /* - * Determine if the processor supports saving state in MSRs. If so, - * enable it before the non-BSPs run so that SMM relocation can occur - * in parallel in the non-BSP CPUs. + * Determine if the processor supports saving state in MSRs. If so, enable it before + * the non-BSPs run so that SMM relocation can occur in parallel in the non-BSP CPUs. */ if (cpu == 0) { /* - * If smm_save_state_in_msrs is 1 then that means this is the - * 2nd time through the relocation handler for the BSP. - * Parallel SMM handler relocation is taking place. However, - * it is desired to access other CPUs save state in the real - * SMM handler. Therefore, disable the SMM save state in MSRs - * feature. + * If smm_save_state_in_msrs is 1 then that means this is the 2nd time through + * the relocation handler for the BSP. Parallel SMM handler relocation is + * taking place. However, it is desired to access other CPUs save state in the + * real SMM handler. Therefore, disable the SMM save state in MSRs feature. */ if (relo_params->smm_save_state_in_msrs) { msr_t smm_feature_control; @@ -154,10 +145,9 @@ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control); } else if (bsp_setup_msr_save_state(relo_params)) /* - * Just return from relocation handler if MSR save - * state is enabled. In that case the BSP will come - * back into the relocation handler to setup the new - * SMBASE as well disabling SMM save state in MSRs. + * Just return from relocation handler if MSR save state is enabled. + * In that case the BSP will come back into the relocation handler + * to setup the new SMBASE as well disabling SMM save state in MSRs. */ return; } @@ -210,8 +200,7 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); } -void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) +void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -243,10 +232,9 @@ void smm_relocate(void) { /* - * If smm_save_state_in_msrs is non-zero then parallel SMM relocation - * shall take place. Run the relocation handler a second time on the - * BSP to do * the final move. For APs, a relocation handler always - * needs to be run. + * If smm_save_state_in_msrs is non-zero then parallel SMM relocation shall take place. + * Run the relocation handler a second time on the BSP to do * the final move. + * For APs, a relocation handler always needs to be run. */ if (smm_reloc_params.smm_save_state_in_msrs) smm_initiate_relocation_parallel(); @@ -258,9 +246,8 @@ { struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. + * LOCK the SMM memory window and enable normal SMM. After running this + * function, only a full reset can make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 410265f..825078b 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -30,23 +30,21 @@ bool soc_is_vtd_capable(void) { struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - return root_dev && - !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); + + return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); } /* * SoC implementation * - * Add all known fixed memory ranges for Host Controller/Memory - * controller. + * Add all known fixed memory ranges for Host Controller/Memory controller. */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); static const struct sa_mmio_descriptor soc_fixed_resources[] = { - { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, - "PCIEXBAR" }, + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, @@ -60,11 +58,9 @@ if (!config->ignore_vtd && soc_is_vtd_capable()) { if (igd_dev && igd_dev->enabled) - sa_add_fixed_mmio_resources(dev, index, - &soc_gfxvt_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); - sa_add_fixed_mmio_resources(dev, index, - &soc_vtvc0_mmio_descriptor, 1); + sa_add_fixed_mmio_resources(dev, index, &soc_vtvc0_mmio_descriptor, 1); } } diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 089dd5d..7febe24 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -295,8 +295,7 @@ } #endif -void fill_vr_domain_config(void *params, - int domain, const struct vr_config *chip_cfg) +void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params; const struct vr_config *cfg; -- To view, visit https://review.coreboot.org/c/coreboot/+/35172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3749286a1166b5be9e40cbf94e8bb6366469b22 Gerrit-Change-Number: 35172 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/amd/picasso: Begin adding FSP support
by Marshall Dawson (Code Review) 01 May '20

01 May '20

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34423 to review the following change. Change subject: soc/amd/picasso: Begin adding FSP support ...................................................................... soc/amd/picasso: Begin adding FSP support AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Unlike Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. in EDK II, and has no entry points for easy inclusion into a legacy BIOS. AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver. * Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. * Remove cbmem initialization, as the FSP driver does this step. * Add chipset_handle_reset() for compatibility. * Increase the size set to WB for ramstage, as ramstage outgrew the region. Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/reset.c M src/soc/amd/picasso/romstage.c 4 files changed, 44 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/34423/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 840de12..3c27f15 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -61,6 +61,18 @@ select POSTCAR_CONSOLE select SSE2 select RTC + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select ADD_FSP_BINARIES + select HAVE_CF9_RESET + +config FSP_DEBUG_ALL + bool "Enable all FSP debug support" + default y + select DISPLAY_HOBS + select DISPLAY_UPD_DATA + select DISPLAY_FSP_CALLS_AND_STATUS + select DISPLAY_FSP_HEADER config VBOOT select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 8d49271..d94091d 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -26,6 +26,7 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include "chip.h" +#include <fsp/api.h> /* Supplied by i2c.c */ extern struct device_operations picasso_i2c_mmio_ops; @@ -117,6 +118,8 @@ static void soc_init(void *chip_info) { + fsp_silicon_init(acpi_is_wakeup_s3()); + southbridge_init(chip_info); setup_bsp_ramtop(); } diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 9841038..03cf306 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -22,6 +22,7 @@ #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> +#include <fsp/util.h> void set_warm_reset_flag(void) { @@ -56,3 +57,17 @@ /* TODO: Would a warm_reset() suffice? */ do_cold_reset(); } + +void chipset_handle_reset(uint32_t status) +{ + switch (status) { + case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ + printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); + do_cold_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index da4ed8d..2b2813d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -37,6 +37,7 @@ #include <soc/northbridge.h> #include <soc/southbridge.h> #include <soc/romstage.h> +#include <fsp/api.h> __weak void romstage_mainboard_early_init(void) {} __weak void romstage_mainboard_init(int s3_resume) {} @@ -80,6 +81,11 @@ timestamp_add(TS_START_ROMSTAGE, stage_start); } +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + // dummy +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -137,27 +143,26 @@ boot_count_increment(); post_code(0x49); + + /* fsp_memory_init() requires cbmem_top() before returning. Use TOM. + * todo: verify TOM < UMA region when UMA is below 4GB */ msr_t tom = rdmsr(TOP_MEM); tom.lo &= ~0xffffff; backup_top_of_low_cacheable(tom.lo); - post_code(0x4a); - if (cbmem_recovery(s3_resume)) - printk(BIOS_CRIT, "Failed to recover cbmem\n"); - if (romstage_handoff_init(s3_resume)) - printk(BIOS_ERR, "Failed to set romstage handoff data\n"); + fsp_memory_init(s3_resume); - post_code(0x4b); + post_code(0x4a); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. + * 32 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t) cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + postcar_frame_add_mtrr(&pcf, top_of_ram - 32*MiB, 32*MiB, MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ @@ -174,7 +179,7 @@ tseg_base = (uintptr_t)smm_base; postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); - post_code(0x4c); + post_code(0x4b); run_postcar_phase(&pcf); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Gerrit-Change-Number: 34423 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

10 42

Change in ...coreboot[master]: payloads/ipxe: Enable HTTPS support
by Felix Singer (Code Review) 01 May '20

01 May '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31086 Change subject: payloads/ipxe: Enable HTTPS support ...................................................................... payloads/ipxe: Enable HTTPS support HTTPS needs a newer iPXE version than 2017.3, because it doesn't work with this release. Tested under master branch. Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/31086/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..05b6f4dd 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -54,6 +54,7 @@ sed 's|#define\s*COMCONSOLE.*|#define COMCONSOLE $(IPXE_UART)|' "$(project_dir)/src/config/serial.h" > "$(project_dir)/src/config/serial.h.tmp" sed 's|#define\s*COMSPEED.*|#define COMSPEED $(CONFIG_TTYS0_BAUD)|' "$(project_dir)/src/config/serial.h.tmp" > "$(project_dir)/src/config/serial.h" endif + sed -ie 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" build: config echo " MAKE $(project_name) $(TAG-y)" -- To view, visit https://review.coreboot.org/c/coreboot/+/31086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25d4ce9260fa8c00fdea0e19f5e927559371af0 Gerrit-Change-Number: 31086 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: [WIP] arch/x86: Add linker script for early DRAM
by Kyösti Mälkki (Code Review) 29 Apr '20

29 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35035 ) Change subject: [WIP] arch/x86: Add linker script for early DRAM ...................................................................... [WIP] arch/x86: Add linker script for early DRAM Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/early_dram.ld 1 file changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35035/1 diff --git a/src/arch/x86/early_dram.ld b/src/arch/x86/early_dram.ld new file mode 100644 index 0000000..24b9551 --- /dev/null +++ b/src/arch/x86/early_dram.ld @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file is included inside a SECTIONS block */ +. = CONFIG_DCACHE_RAM_BASE; +.car.data . (NOLOAD) : { + _car_region_start = . ; + + /* Stack for CAR stages. Since it persists across all stages that + * use CAR it can be reused. The chipset/SoC is expected to provide + * the stack size. */ +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) + _car_stack_start = .; + . += CONFIG_DCACHE_BSP_STACK_SIZE; + _car_stack_end = .; +#endif + /* The pre-ram cbmem console as well as the timestamp region are fixed + * in size. Therefore place them above the car global section so that + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ + PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) + + TIMESTAMP(., 0x200) + + _car_ehci_dbg_info_start = .; + /* Reserve sizeof(struct ehci_dbg_info). */ + . += 80; + _car_ehci_dbg_info_end = .; + + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); +} + +_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); +#if !CONFIG(CAR_GLOBAL_MIGRATION) +_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780 Gerrit-Change-Number: 35035 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

10 109

Change in coreboot[master]: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg
by Sridhar Siricilla (Code Review) 28 Apr '20

28 Apr '20

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35227 to review the following change. Change subject: src/soc/intel/common/block/cse: Add funtion to send CSE reset msg ...................................................................... src/soc/intel/common/block/cse: Add funtion to send CSE reset msg Add send_heci_reset_req_message() to send reset request to CSE. This reset can be GLOBAL RESET/HOST ONLY RESET/CSE ONLY RESET. Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35227/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 7697a4a..9585a09 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -69,10 +69,18 @@ #define HECI_OP_MODE_SEC_OVERRIDE 5 +/* Global Reset Command ID */ +#define MKHI_GLOBAL_RESET_REQ 0xb +#define MKHI_GROUP_ID_CBM 0 + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 2 + static struct cse_device { uintptr_t sec_bar; } g_cse; +/* HFSTS1 */ union me_hfs { u32 data; struct { @@ -595,6 +603,54 @@ return reg; } +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be GLOBAL_RESET/ + * HOST_RESET_ONLY/HOST_RESET_ONLY. + */ +int send_heci_reset_req_message(u8 rst_type) +{ + int status; + struct reset_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + } __packed reply; + struct reset_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u8 req_origin; + u8 reset_type; + } __packed; + struct reset_message msg = { + .group_id = MKHI_GROUP_ID_CBM, + .cmd = MKHI_GLOBAL_RESET_REQ, + .req_origin = GR_ORIGIN_BIOS_POST, + .reset_type = rst_type + }; + size_t reply_size; + + if (!((rst_type == GLOBAL_RESET) + || (rst_type == HOST_RESET_ONLY) + || (rst_type == CSE_RESET_ONLY))) { + return -1; + } + + heci_reset(); + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + printk(BIOS_ERR, "HECI Global Reset(type=%d) Command\n", rst_type); + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); + if (status != 1) + return -1; + + printk(BIOS_DEBUG, "HECI GBL RST success!\n"); + return 0; +} #if ENV_RAMSTAGE diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 82e07cf..ceeca88e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -70,6 +70,13 @@ */ int wait_cse_rec(void); +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset can be + * GLOBAL_RESET/HOST_RESET_ONLY/HOST_RESET_ONLY. + * Returns -1 on failure a 0 on success. + */ +int send_heci_reset_req_message(u8 rst_type); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 @@ -83,4 +90,11 @@ PCI_ME_HFSTS6 = 0x6C, }; + +/* Command GLOBAL_RESET_REQ Reset Types */ +#define GLOBAL_RESET 1 +#define HOST_RESET_ONLY 2 +#define CSE_RESET_ONLY 3 + + #endif // SOC_INTEL_COMMON_MSR_H -- To view, visit https://review.coreboot.org/c/coreboot/+/35227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29b560dde1549b8268163e18d9b1bbbf1935d54a Gerrit-Change-Number: 35227 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

3 14

Change in ...coreboot[master]: security/lockdown: Write-protect WP_RO
by Patrick Rudolph (Code Review) 28 Apr '20

28 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32705 Change subject: security/lockdown: Write-protect WP_RO ...................................................................... security/lockdown: Write-protect WP_RO Add another choice to boot media protection and write-protect WP_RO in case VBOOT is enabled. Tested on Lenovo T520: The WP_RO region is write-protected. Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/security/lockdown/bootmedia.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/32705/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index bb4d072..1e982d8 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -15,6 +15,18 @@ config BOOTMEDIA_LOCK_NONE bool "Don't lock boot media sections" +config BOOTMEDIA_LOCK_VBOOT_RO + bool "Write-protect WP_RO region in boot media" + depends on VBOOT + help + Select this if you want to write-protect the WP_RO region as specified + in the VBOOT FMAP. You will only be able to write the regions + FW_MAIN_A/FW_MAIN_B, which are not write-protected using the internal + programmer. + The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + config BOOTMEDIA_LOCK_RO bool "Write-protect the whole boot media" help diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c index 8fb4ae9..6fa2de2 100644 --- a/src/security/lockdown/bootmedia.c +++ b/src/security/lockdown/bootmedia.c @@ -17,6 +17,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <bootstate.h> +#include <fmap.h> /* * Enable write protection on the WP_RO region of the bootmedia. @@ -47,8 +48,23 @@ "of whole bootmedia\n"); locked = true; } - } + } else if (CONFIG(BOOTMEDIA_LOCK_VBOOT_RO)) { + struct region_device dev; + if (fmap_locate_area_as_rdev("WP_RO", &dev) < 0) { + printk(BIOS_ERR, "BM-LOCKDOWN: Could not find region 'WP_RO'\n"); + } else { + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(&dev, wp_prot[i]) < 0) + continue; + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "WP_RO region\n"); + locked = true; + } + } + } if (!locked) printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2 Gerrit-Change-Number: 32705 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

11 54

Change in ...coreboot[master]: security: Add common boot media write protection
by Patrick Rudolph (Code Review) 28 Apr '20

28 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32704 Change subject: security: Add common boot media write protection ...................................................................... security: Add common boot media write protection Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Tested on Lenovo T520. The whole flash is protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/Kconfig M src/security/Makefile.inc A src/security/lockdown/Kconfig A src/security/lockdown/Makefile.inc A src/security/lockdown/bootmedia.c M src/soc/intel/common/block/fast_spi/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/finalize.c 8 files changed, 124 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32704/1 diff --git a/src/security/Kconfig b/src/security/Kconfig index 6a334ac..99cb054 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -14,3 +14,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" +source "src/security/lockdown/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index a940b82..a74e498 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += vboot subdirs-y += tpm +subdirs-y += lockdown diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig new file mode 100644 index 0000000..bb4d072 --- /dev/null +++ b/src/security/lockdown/Kconfig @@ -0,0 +1,46 @@ + +config SECURITY_BOOTMEDIA_LOCKDOWN + bool + default n + help + Platform support the locking of boot media. This can be for example + SPI controller protected regions or flash status register locking. + +if SECURITY_BOOTMEDIA_LOCKDOWN + +choice + prompt "Boot media protection" + default BOOTMEDIA_LOCK_NONE + +config BOOTMEDIA_LOCK_NONE + bool "Don't lock boot media sections" + +config BOOTMEDIA_LOCK_RO + bool "Write-protect the whole boot media" + help + Select this if you want to write-protect the whole firmware boot + media. The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the flash chip using the + internal programmer any more. + +config BOOTMEDIA_LOCK_NO_ACCESS + bool "Read- and write-protect the whole boot media" + help + Select this if you want to protect the firmware boot media against + all further accesses. On platforms that memory map a part of the + boot media the corresponding region is still readable. + The locking will take place during the chipset lockdown, which is + either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or + has to be triggered later (e.g. by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the boot media using the + internal programmer any more. + +endchoice + +endif diff --git a/src/security/lockdown/Makefile.inc b/src/security/lockdown/Makefile.inc new file mode 100644 index 0000000..c287b9b --- /dev/null +++ b/src/security/lockdown/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SECURITY_BOOTMEDIA_LOCKDOWN) += bootmedia.c diff --git a/src/security/lockdown/bootmedia.c b/src/security/lockdown/bootmedia.c new file mode 100644 index 0000000..8fb4ae9 --- /dev/null +++ b/src/security/lockdown/bootmedia.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <bootstate.h> + +/* + * Enable write protection on the WP_RO region of the bootmedia. + */ +static void security_lockdown_bootmedia(void *unused) +{ + static const int wp_prot[] = {MEDIA_WP, CTRLR_WP}; + const struct region_device *rdev; + bool locked = false; + + if (CONFIG(BOOTMEDIA_LOCK_RO)) { + rdev = boot_device_ro(); + + for (size_t i = 0; i < ARRAY_SIZE(wp_prot); i++) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Trying write-protection" + "#%zu ...\n", i); + if (boot_device_wp_region(rdev, wp_prot[i]) < 0) + continue; + + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled write-protection of" + "whole bootmedia\n"); + locked = true; + } + } else if (CONFIG(BOOTMEDIA_LOCK_NO_ACCESS)) { + rdev = boot_device_ro(); + if (boot_device_wp_region(rdev, CTRLR_RWP) == 0) { + printk(BIOS_INFO, "BM-LOCKDOWN: Enabled read- and write protection" + "of whole bootmedia\n"); + locked = true; + } + } + + if (!locked) + printk(BIOS_INFO, "BM-LOCKDOWN: Didn't enable bootmedia protection\n"); +} + +/* BS_POST_DEVICE will lock the hardware */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, security_lockdown_bootmedia, + NULL); diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 4bd1f59..ff02844 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_FAST_SPI bool + select SECURITY_BOOTMEDIA_LOCKDOWN help Intel Processor common FAST_SPI support diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90d..39234a8 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI def_bool n select SPI_FLASH + select SECURITY_BOOTMEDIA_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n @@ -68,42 +69,3 @@ config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON - -if SOUTHBRIDGE_INTEL_COMMON_FINALIZE - -choice - prompt "Flash locking during chipset lockdown" - default LOCK_SPI_FLASH_NONE - -config LOCK_SPI_FLASH_NONE - bool "Don't lock flash sections" - -config LOCK_SPI_FLASH_RO - bool "Write-protect all flash sections" - help - Select this if you want to write-protect the whole firmware flash - chip. The locking will take place during the chipset lockdown, which - is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) - or has to be triggered later (e.g. by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -config LOCK_SPI_FLASH_NO_ACCESS - bool "Write-protect all flash sections and read-protect non-BIOS sections" - help - Select this if you want to protect the firmware flash against all - further accesses (with the exception of the memory mapped BIOS re- - gion which is always readable). The locking will take place during - the chipset lockdown, which is either triggered by coreboot (when - INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. - by the payload or the OS). - - NOTE: If you trigger the chipset lockdown unconditionally, - you won't be able to write to the flash chip using the - internal programmer any more. - -endchoice - -endif diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index 80c65bb..6f7934a 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -28,16 +28,6 @@ { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (CONFIG(LOCK_SPI_FLASH_RO) || - CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { - int i; - u32 lockmask = 1UL << 31; - if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) - lockmask |= 1 << 15; - for (i = 0; i < 20; i += 4) - RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; - } - /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -- To view, visit https://review.coreboot.org/c/coreboot/+/32704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Gerrit-Change-Number: 32704 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 39

Change in ...coreboot[master]: soc/intel/apl: Add chip.h setting for PCIe ASPM
by Thomas Heijligen (Code Review) 22 Apr '20

22 Apr '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31351 to review the following change. Change subject: soc/intel/apl: Add chip.h setting for PCIe ASPM ...................................................................... soc/intel/apl: Add chip.h setting for PCIe ASPM We don't use a direct mapping to the UPD values so we don't have to set it to the default `auto` in all devicetrees. Change-Id: I169722c3c63be66772cb57a429ec7b83230fa234 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31351/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3634509..cfe8d4a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -669,6 +669,7 @@ { FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; + int i; /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); @@ -693,6 +694,11 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + for (i = 0; i < ARRAY_SIZE(silconfig->PcieRpAspm); ++i) { + if (cfg->pcie_rp_aspm[i] != ASPM_IGNORE) + silconfig->PcieRpAspm[i] = cfg->pcie_rp_aspm[i] - 1; + } + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..b8f9f8c 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -57,6 +57,18 @@ /* De-emphasis enable configuration for each PCIe root port */ uint8_t pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; + /* ASPM enable setting for each PCIe root port */ + enum { + ASPM_IGNORE = 0, + /* Enumeration values below are off-by-one compared to the + UPD to have the default 0 ignore the devicetree setting: */ + ASPM_DISABLED, + ASPM_L0S, + ASPM_L1, + ASPM_L0SL1, + ASPM_AUTO, + } pcie_rp_aspm[MAX_PCIE_PORTS]; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I169722c3c63be66772cb57a429ec7b83230fa234 Gerrit-Change-Number: 31351 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFO...
by Mike Banon (Code Review) 20 Apr '20

20 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33919 Change subject: src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP ...................................................................... src/mainboard/asus/am1i-a/buildOpts.c: set a board type to AMD_PLATFORM_DESKTOP Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33919/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index cba0894..98bc620 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -115,7 +115,7 @@ #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE -- To view, visit https://review.coreboot.org/c/coreboot/+/33919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd Gerrit-Change-Number: 33919 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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