coreboot-gerrit September 2019

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Change in ...coreboot[master]: src/mainboard/sony: Add Sony VPCEH2K1E
by Angel Pons (Code Review) 10 Apr '20

10 Apr '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30973 Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ...................................................................... src/mainboard/sony: Add Sony VPCEH2K1E Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/1 diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig b/src/mainboard/sony/vpceh2k1e/Kconfig new file mode 100644 index 0000000..7d1f6ca --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig @@ -0,0 +1,44 @@ +if BOARD_SONY_VPCEH2K1E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default sony_corporation/vpceh2k1e + +config MAINBOARD_PART_NUMBER + string + default "VPCEH2K1E" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x908b + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x104d + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig.name b/src/mainboard/sony/vpceh2k1e/Kconfig.name new file mode 100644 index 0000000..3de2fcc --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SONY_VPCEH2K1E + bool "VPCEH2K1E" diff --git a/src/mainboard/sony/vpceh2k1e/Makefile.inc b/src/mainboard/sony/vpceh2k1e/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/sony/vpceh2k1e/acpi/ec.asl b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl new file mode 100644 index 0000000..9988369 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/platform.asl b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl new file mode 100644 index 0000000..15d53d9 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/superio.asl b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl new file mode 100644 index 0000000..8bfc1a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/sony/vpceh2k1e/acpi_tables.c b/src/mainboard/sony/vpceh2k1e/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sony/vpceh2k1e/board_info.txt b/src/mainboard/sony/vpceh2k1e/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/sony/vpceh2k1e/devicetree.cb b/src/mainboard/sony/vpceh2k1e/devicetree.cb new file mode 100644 index 0000000..d96ae12 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/devicetree.cb @@ -0,0 +1,63 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x104d 0x908b inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x000c0601" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00040069" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x9" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/sony/vpceh2k1e/dsdt.asl b/src/mainboard/sony/vpceh2k1e/dsdt.asl new file mode 100644 index 0000000..675703b --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/sony/vpceh2k1e/gpio.c b/src/mainboard/sony/vpceh2k1e/gpio.c new file mode 100644 index 0000000..5a16e8e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sony/vpceh2k1e/hda_verb.c b/src/mainboard/sony/vpceh2k1e/hda_verb.c new file mode 100644 index 0000000..d2c4fa3 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/hda_verb.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x104d5a00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104d5a00), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03211040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x400001f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x03a15030), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x400001f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x400001f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x400001f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x400001f0), + + /* NID 0x22. */ + AZALIA_PIN_CFG(0x0, 0x22, 0x400001f0), + + /* NID 0x23. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a70150), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sony/vpceh2k1e/mainboard.c b/src/mainboard/sony/vpceh2k1e/mainboard.c new file mode 100644 index 0000000..08cb738 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + if (0) { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, + /* 10 */ 0x94, 0x94, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x14, 0xc0, 0x00, + /* 40 */ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x2d, 0x29, 0x00, 0x31, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x41, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x6e, 0x0a, 0x28, 0x0a, 0x01, 0x01, 0x26, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x10, 0x02, 0x00, 0x00, 0x09, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, + /* d0 */ 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0b, 0x1a, + /* e0 */ 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x58, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sony/vpceh2k1e/romstage.c b/src/mainboard/sony/vpceh2k1e/romstage.c new file mode 100644 index 0000000..0e1c365 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0601); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 0, 1, -1 }, + { 1, 1, 3 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 1, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Gerrit-Change-Number: 30973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: soc/amd/picasso: Add basic MTRR settings to hybrid romstage
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35297 ) Change subject: soc/amd/picasso: Add basic MTRR settings to hybrid romstage ...................................................................... soc/amd/picasso: Add basic MTRR settings to hybrid romstage Program the system flash as WP to allow it to be cacheable. This was done during bootblock on previous systems. Since this code and its data are in DRAM, set them to WP. Prior to running ramstage, set its anticipated target location as WP also. Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/romstage.c 2 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35297/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 66e6650..15f319f 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -25,8 +25,18 @@ #define ROMSTAGE_SIZE (64 * KiB) /* Enforced by Makefile.inc for PSP info */ #define ROMSTAGE_TOP (CONFIG_ROMSTAGE_ADDR + ROMSTAGE_SIZE) +#define EARLYRAM_TOP (ROMSTAGE_TOP + CONFIG_EARLYRAM_SIZE) #if ROMSTAGE_TOP & 0xffff # error Top of the BIOS binary image must be 64KB aligned #endif +#define EARLY_DRAM_MTRR_BASE \ + ALIGN_DOWN(CONFIG_ROMSTAGE_ADDR, 32 * MiB) +#define EARLY_DRAM_MTRR_SIZE \ + ALIGN_UP(ROMSTAGE_SIZE + CONFIG_EARLYRAM_SIZE, 32 * MiB) +#define EARLY_DRAM_MTRR_TOP \ + (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) + +#define EARLY_RAMSTAGE_MTRR_SZ (16 * MiB) + #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 92361f9..b4c8013 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -21,8 +21,10 @@ #include <delay.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/x86/bist.h> +#include <cpu/amd/mtrr.h> #include <cpu/amd/msr.h> #include <cbmem.h> #include <console/console.h> @@ -56,10 +58,68 @@ fch_early_init(); } +static int set_early_mtrrs(void) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, EARLY_DRAM_MTRR_BASE, EARLY_DRAM_MTRR_SIZE, + MTRR_TYPE_WRBACK); + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); + return 0; +} + +static void set_mtrrs_for_ramstage(void) +{ + uintptr_t smm_base; + size_t smm_size; + uintptr_t smm_top; + uintptr_t mem_top; + uintptr_t ramstage_wb_base; + size_t ramstage_wb_size; + int mtrr; + + smm_region(&smm_base, &smm_size); + smm_top = smm_base + smm_size; + + mem_top = (uintptr_t)cbmem_top(); + + /* Cache anticipated ramstage location through the top of TSEG */ + ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_size = smm_top - ramstage_wb_base; + + /* Make sure MTRR base and size are usable */ + if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { + ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); + ramstage_wb_base = smm_top - ramstage_wb_size; + } + if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { + printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); + return; + } + + mtrr = get_free_var_mtrr(); + if (mtrr >= 0) + set_var_mtrr(mtrr, ramstage_wb_base, ramstage_wb_size, + MTRR_TYPE_WRBACK); + else + printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n"); +} + asmlinkage void soc_hybrid_romstage_entry(uint32_t bist, uint64_t early_tsc) { uintptr_t top_of_mem; int s3_resume; + int early_mtrr_err; post_code(0x40); if (CONFIG(COLLECT_TIMESTAMPS)) { @@ -70,6 +130,7 @@ /* Many of these tasks typically happen in bootblock, but execution * begins in romstage for this device. */ post_code(0x41); + early_mtrr_err = set_early_mtrrs(); post_code(0x42); romstage_soc_early_init(); @@ -96,6 +157,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + if (early_mtrr_err) + printk(BIOS_WARNING, "Early MTRRs were not set properly\n"); + post_code(0x48); if (!s3_resume && CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); @@ -111,6 +175,7 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x4b); + set_mtrrs_for_ramstage(); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Gerrit-Change-Number: 35297 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: security/vboot: Decouple measured boot from verified boot
by Bill XIE (Code Review) 31 Mar '20

31 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35077 ) Change subject: security/vboot: Decouple measured boot from verified boot ...................................................................... security/vboot: Decouple measured boot from verified boot As said in CB:34977, currently TPM and CRTM are initialized just before romstage loads a file within CBFS, or initialized in vboot_logic() if CONFIG_VBOOT is set. Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/lib/cbfs.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/misc.h M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 8 files changed, 136 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35077/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..246e741 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -327,6 +327,9 @@ * devices. */ const struct cbfs_locator __weak cbfs_master_header_locator = { .name = "Master Header Locator", +#if !CONFIG(VBOOT) && CONFIG(VBOOT_MEASURED_BOOT) + .prepare = measured_boot_init_crtm, +#endif .locate = cbfs_master_header_props, }; diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index a2d32cf..cb936cf 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -8,7 +8,10 @@ romstage-y += tss/tcg-1.2/tss.c verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c -postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tss/tcg-1.2/tss.c +endif ## TSPI @@ -16,7 +19,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c @@ -45,7 +51,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..36dd3dd 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -20,7 +20,7 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) #include <vb2_api.h> #include <vb2_sha.h> #include <assert.h> @@ -220,7 +220,7 @@ return TPM_SUCCESS; } -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, const char *rname) { @@ -279,4 +279,4 @@ printk(BIOS_DEBUG, "TPM: Measured %s into PCR %d\n", rname, pcr); return TPM_SUCCESS; } -#endif /* VBOOT */ +#endif /* VBOOT || VBOOT_MEASURED_BOOT */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c6..955e8a6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -menu "Verified Boot (vboot)" +menu "vboot functionalities" config VBOOT bool "Verify firmware with vboot." @@ -21,21 +21,17 @@ select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2 depends on !MISSING_BOARD_RESET help - Enabling VBOOT will use vboot to verify the components of the firmware + Enabling verified voot will use vboot to verify the components of the firmware (stages, payload, etc). -if VBOOT - -comment "Anti-Rollback Protection disabled because mocking secdata is enabled." - depends on VBOOT_MOCK_SECDATA - config VBOOT_MEASURED_BOOT - bool "Enable Measured Boot" + bool "Measure firmware components with vboot." default n depends on TPM1 || TPM2 depends on !VBOOT_RETURN_FROM_VERSTAGE help - Enables measured boot mode in vboot (experimental) + Enables measured boot will use vboot to measure the components of the firmware + (stages, payload, etc) to PCRs within TPM. (experimental) config VBOOT_MEASURED_BOOT_RUNTIME_DATA string "Runtime data whitelist" @@ -45,6 +41,13 @@ Runtime data whitelist of cbfs filenames. Needs to be a comma separated list +if VBOOT + +comment "Anti-Rollback Protection disabled because mocking secdata is enabled." + depends on VBOOT_MOCK_SECDATA + +comment "A non-trivial fmd file with sections required by vboot is needed." + config VBOOT_SLOTS_RW_A bool "Firmware RO + RW_A" help diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f10..0729d9f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -14,6 +14,58 @@ ## GNU General Public License for more details. ## +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) + +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c +endif + + +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $(filter-out -I$(obj),$(1)))) + +# call with $1 = stage name to create rules for building the library +# for the stage and adding it to the stage's set of object files. +define vboot-for-stage +VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) +VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) +VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes +VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG + +$$(VB2_LIB_$(1)): $(obj)/config.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ + CC="$$(CC_$(1))" \ + CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ + $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ + V=$(V) \ + fwlib20 + +$(1)-srcs += $$(VB2_LIB_$(1)) + +endef # vboot-for-stage + +CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include + +$(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) +$(eval $(call vboot-for-stage,ramstage)) +$(eval $(call vboot-for-stage,postcar)) + +endif # CONFIG_VBOOT_MEASURED_BOOT || CONFIG_VBOOT + +ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) +bootblock-y += vboot_crtm.c +verstage-y += vboot_crtm.c +romstage-y += vboot_crtm.c +ramstage-y += vboot_crtm.c +postcar-y += vboot_crtm.c +endif # CONFIG_VBOOT_MEASURED_BOOT + ifeq ($(CONFIG_VBOOT),y) bootblock-y += bootmode.c @@ -22,6 +74,12 @@ verstage-y += bootmode.c postcar-y += bootmode.c +bootblock-y += vboot_common.c +verstage-y += vboot_common.c +romstage-y += vboot_common.c +ramstage-y += vboot_common.c +postcar-y += vboot_common.c + # When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by # the time verstage runs. ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) @@ -63,19 +121,7 @@ verstage-y += vboot_loader.c postcar-y += vboot_loader.c -bootblock-y += vboot_common.c -verstage-y += vboot_common.c -romstage-y += vboot_common.c -ramstage-y += vboot_common.c -postcar-y += vboot_common.c -ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) -bootblock-y += vboot_crtm.c -verstage-y += vboot_crtm.c -romstage-y += vboot_crtm.c -ramstage-y += vboot_crtm.c -postcar-y += vboot_crtm.c -endif bootblock-y += common.c verstage-y += vboot_logic.c @@ -89,10 +135,6 @@ romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif -ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) -verstage-y += tpm_common.c -endif - romstage-y += vboot_logic.c romstage-y += common.c @@ -101,41 +143,6 @@ romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ - $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $(filter-out -I$(obj),$(1)))) - -# call with $1 = stage name to create rules for building the library -# for the stage and adding it to the stage's set of object files. -define vboot-for-stage -VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) -VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) -VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes -VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG - -$$(VB2_LIB_$(1)): $(obj)/config.h - printf " MAKE $(subst $(obj)/,,$(@))\n" - +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ - CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ - $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ - V=$(V) \ - fwlib20 - -$(1)-srcs += $$(VB2_LIB_$(1)) - -endef # vboot-for-stage - -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include - -$(eval $(call vboot-for-stage,bootblock)) -$(eval $(call vboot-for-stage,romstage)) -$(eval $(call vboot-for-stage,ramstage)) -$(eval $(call vboot-for-stage,postcar)) - ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) $(eval $(call vboot-for-stage,verstage)) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 725f5fd..8761b84 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -127,5 +127,21 @@ } } +static inline int vboot_crtm_is_set(void) +{ + extern int crtm_is_set; + if (CONFIG(VBOOT)) { + return vboot_logic_executed(); + } else if(ENV_ROMSTAGE) { + return car_get_var(crtm_is_set); + } else { +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } +} + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..92f05e5 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -19,11 +19,13 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/misc.h> #include <string.h> +#include <timestamp.h> /* * This functions sets the TCPA log namespace * for the cbfs file (region) lookup. */ + static int create_tcpa_metadata(const struct region_device *rdev, const char *cbfs_name, char log_string[TCPA_PCR_HASH_NAME]) { @@ -90,7 +92,8 @@ } } - if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE) || + CONFIG(VBOOT_MEASURED_BOOT)) { struct cbfsf romstage_data; /* measure romstage from RO */ if (cbfs_boot_locate(&romstage_data, @@ -164,7 +167,7 @@ struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; - if (!vboot_logic_executed()) + if (!vboot_crtm_is_set()) return 0; cbfsf_file_type(fh, &cbfs_type); @@ -193,3 +196,26 @@ return tpm_measure_region(&rdev, pcr_index, tcpa_metadata); } + +int crtm_is_set CAR_GLOBAL; + +void measured_boot_init_crtm(void) +{ + if (ENV_ROMSTAGE) { + timestamp_add_now(TS_START_TPMINIT); + int result = tpm_setup(vboot_platform_is_resuming()); + timestamp_add_now(TS_END_TPMINIT); + + if (result == TPM_SUCCESS) { + result = vboot_init_crtm(); + if(result != VB2_SUCCESS) { + printk(BIOS_INFO, + "Initializing CRTM failed!"); + } else { + car_set_var(crtm_is_set, 1); + } + } else { + printk(BIOS_INFO, "TPM setup failed!"); + } + } +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..87bfa2d 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -53,6 +53,10 @@ * return 0 if successful, else an error */ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +/* + * Initialize crtm without running vboot_logic() + */ +void measured_boot_init_crtm(void); #else #define vboot_measure_cbfs_hook(fh, name) 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Gerrit-Change-Number: 35077 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

12 184

Change in ...coreboot[master]: SKL: Add ACPI brightness control
by Matthew Garrett (Code Review) 28 Mar '20

28 Mar '20

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32549 Change subject: SKL: Add ACPI brightness control ...................................................................... SKL: Add ACPI brightness control Hook up the generic src/drivers/intel/gma ACPI backlight control for Skylake. Based on a patch by Matt DeVillier <matt.devillier(a)gmail.com>. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h 7 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32549/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..6489e8e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -33,6 +33,10 @@ pci_dev_init(dev); } +__weak void gma_ssdt(struct device *dev) +{ +} + static uintptr_t graphics_get_bar(unsigned long index) { struct device *dev = SA_DEV_IGD; @@ -104,6 +108,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt_generator = gma_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 6be7661..077f0db 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -51,4 +51,7 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask); uintptr_t graphics_get_memory_base(void); +void gma_ssdt(struct device *dev); +struct i915_gpu_controller_info *intel_igd_get_controller_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..6963f70 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + BRTL, 32, // 0x54 - 0x57 Brightness Level + CSTE, 16, // 0x58 - 0x59 Current display state + NSTE, 16, // 0x5a - 0x5b Next display state /* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..f0095bc 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -56,6 +56,9 @@ /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* Graphics */ +#include <drivers/intel/gma/acpi/pch.asl> + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e7..51bb740 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/i915.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -580,6 +581,8 @@ /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67a..1be5f9d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -122,3 +122,22 @@ printk(BIOS_DEBUG, "current = %lx\n", current); return current; } + +struct i915_gpu_controller_info *intel_igd_get_controller_info(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + if (!dev) + return NULL; + struct soc_intel_skylake_config *chip = dev->chip_info; + return &chip->gfx; +} + +void gma_ssdt(struct device *dev) +{ + struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(); + + if (!gfx) + return; + + drivers_intel_gma_displays_ssdt_generate(gfx); +} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..5a2ca38 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u32 brtl; /* 0x54 - 0x57 Brightness Level */ + u16 cste; /* 0x58 - 0x59 Current display state */ + u16 nste; /* 0x5a - 0x5b Next display state */ + u8 rsvd[88]; /* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Gerrit-Change-Number: 32549 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

8 23

Change in ...coreboot[master]: Disable SeaBIOS options not supported by hardware: scripts to apply t...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33885 Change subject: Disable SeaBIOS options not supported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options not supported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:33870 and CB:33871 to disable SeaBIOS options not supported by G505S and AM1I-A hardware. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/33870 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/33871 src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33885/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..c1212bf --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./0cd2b7a.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..5e4c1ef --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./053e2ea.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./0cd2b7a.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..0ce0113c --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +rm -f "./053e2ea.diff" +wget "https://review.coreboot.org/changes/33870/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +rm -f "./0cd2b7a.diff" +wget "https://review.coreboot.org/changes/33871/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./0cd2b7a.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..5135520 --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +ed3f92502e35897256e364e146ad7515414552c4e4e87031bfaae1f30ecdad1d ./053e2ea.diff +6c5fd1060ccf3b84687eb76594ed63a76472c573ea968d9efec40f4c3eccb53d ./0cd2b7a.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e Gerrit-Change-Number: 33885 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 11

Change in ...coreboot[master]: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by h...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33871 Change subject: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this motherboard. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33871/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbe..6d88992 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -54,4 +54,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 Gerrit-Change-Number: 33871 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by Mike Banon (Code Review) 27 Mar '20

27 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33874 Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply two changes CB:31448 and CB:31450 to add the discrete GPU support for AMD Lenovo G505S. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2452a75d425f8f647e81314111c462d1195d595d --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33874/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..aca4adb --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < "./b7d4266.diff" +### diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..6137cc4 --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_dgpu_my.txt" +sha256sum "./8e35cfe.diff" > "./sha256sums_dgpu_my.txt" +sha256sum "./b7d4266.diff" >> "./sha256sums_dgpu_my.txt" +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" + exit 1 +fi +# diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..e0d4a2a --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +rm -f "./8e35cfe.diff" +wget "https://review.coreboot.org/changes/31448/revisions/17/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +rm -f "./b7d4266.diff" +wget "https://review.coreboot.org/changes/31450/revisions/12/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b7d4266.diff" +### diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b607b61 --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,2 @@ +284cb0908c498c730dd8ed994c65ffd186d1dd34b4bc3432c9e7ccf7f40313e2 ./8e35cfe.diff +0edfa4f1bb2310220f0d6be2228f0be15d2ab0256e63fa1ed6fecc1650e1f938 ./b7d4266.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2452a75d425f8f647e81314111c462d1195d595d Gerrit-Change-Number: 33874 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: mb/google/sarien: Modify Melfas touchscreen reset delay
by Ivy Jian (Code Review) 27 Mar '20

27 Mar '20

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34162 ) Change subject: mb/google/sarien: Modify Melfas touchscreen reset delay ...................................................................... mb/google/sarien: Modify Melfas touchscreen reset delay Modify reset_delay_ms as 115ms to waiting for Melfas device I2C interface ready after touch fw AU and rebind driver. BUG=b:136560969 BRANCH=sarien TEST=Touchscreen works fine after touch FW auto updated. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34162/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849..53189ce 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -343,7 +343,7 @@ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "reset_delay_ms" = "115" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/34162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Gerrit-Change-Number: 34162 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 3

Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503 Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ...................................................................... drivers/intel/gma: Add `new-pch.asl` for Skylake+ This should work as `pch.asl` equivalent for Skylake and later platforms. Untested. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1 diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Gerrit-Change-Number: 31503 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: soc/intel/skylake: Add Lewisburg PCH GPIOs support
by Maxim Polyakov (Code Review) 23 Mar '20

23 Mar '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35031 ) Change subject: soc/intel/skylake: Add Lewisburg PCH GPIOs support ...................................................................... soc/intel/skylake: Add Lewisburg PCH GPIOs support The pin layout in this patch corresponds to the driver in the linux kernel for Lewisburg PCH GPIO hardware [1] [1] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h A src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h M src/soc/intel/skylake/include/soc/pcr_ids.h 5 files changed, 440 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35031/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 13c1517..34fd97c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -175,6 +175,12 @@ help Choose this option if you have a PCH-H chipset. +config WELISBURG_SOC_PCH_H + bool + default n + help + Choose this option if you have the Lewisburg C62x PCH chipset. + config NHLT_DMIC_2CH bool default n diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..0130936 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -36,6 +36,9 @@ static const struct pad_group skl_community_com0_groups[] = { INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ +#if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */ +#endif }; static const struct pad_group skl_community_com1_groups[] = { @@ -48,19 +51,38 @@ INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */ #else INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ +# if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ +# else INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */ +# endif #endif }; static const struct pad_group skl_community_com3_groups[] = { #if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +#elif CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_I0, GPP_I0, RCOMP_3P3), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */ #endif }; +#if CONFIG(WELISBURG_SOC_PCH_H) +static const struct pad_group skl_community_com4_groups[] = { + INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */ + INTEL_GPP(GPP_J0, GPP_K0, RCOMP_1P8_3P3), /* GPP G */ +}; + +static const struct pad_group skl_community_com5_groups[] = { + INTEL_GPP(GPP_J0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_J0, GPP_H0, GPP_H23), /* GPP H */ + INTEL_GPP(GPP_J0, GPP_L2, GPP_L19), /* GPP L */ +}; +#endif + static const struct pad_group skl_community_com2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ }; @@ -69,7 +91,11 @@ { .port = PID_GPIOCOM0, .first_pad = GPP_A0, +#if CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_F23, +#else .last_pad = GPP_B23, +#endif .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -89,6 +115,8 @@ .first_pad = GPP_C0, #if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, +#elif CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_E12, #else .last_pad = GPP_E23, #endif @@ -108,7 +136,7 @@ .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if CONFIG(SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -130,6 +158,44 @@ .groups = skl_community_com3_groups, .num_groups = ARRAY_SIZE(skl_community_com3_groups), }, { +#if CONFIG(WELISBURG_SOC_PCH_H) + .port = PID_GPIOCOM4, + .first_pad = GPP_J0, + .last_pad = GPP_K10, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com4_groups, + .num_groups = ARRAY_SIZE(skl_community_com4_groups), + }, { + .port = PID_GPIOCOM4, + .first_pad = GPP_G0, + .last_pad = GPP_L19, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com5_groups, + .num_groups = ARRAY_SIZE(skl_community_com5_groups), + }, { +#endif .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -161,17 +227,27 @@ static const struct pmc_to_gpio_route routes[] = { { GPP_A, GPP_A}, { GPP_B, GPP_B}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_F, GPP_F}, +#endif { GPP_C, GPP_C}, { GPP_D, GPP_D}, { GPP_E, GPP_E}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_I, GPP_I}, + { GPP_J, GPP_J}, + { GPP_K, GPP_K}, +#else { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if CONFIG(SKYLAKE_SOC_PCH_H) +# if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, +# endif #endif { GPD, GPD}, }; + *num = ARRAY_SIZE(routes); return routes; } @@ -179,7 +255,7 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (CONFIG(SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..0285989 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -20,6 +20,8 @@ #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> +#elif CONFIG(WELISBURG_SOC_PCH_H) +# include <soc/gpio_wlb_pch_defs.h> #else # include <soc/gpio_soc_defs.h> #endif @@ -33,6 +35,22 @@ #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#if CONFIG(WELISBURG_SOC_PCH_H) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) +#endif + +#if CONFIG(WELISBURG_SOC_PCH_H) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + +#else #define NUM_GPI_STATUS_REGS \ ((NUM_GPIO_COM0_GPI_REGS) +\ @@ -218,6 +236,8 @@ #define GPD10_IRQ 0x5a #define GPD11_IRQ 0x5b +#endif + /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 diff --git a/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h new file mode 100644 index 0000000..636837c --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_WLB_PCH_DEFS_H_ +#define _SOC_GPIO_WLB_PCH_DEFS_H_ + +/* GPIO Community 0 */ +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_F 0x2 +/* GPIO Community 1 */ +#define GPP_C 0x3 +#define GPP_D 0x4 +#define GPP_E 0x5 +/* GPIO Community 3 */ +#define GPP_I 0x6 +/* GPIO Community 4 */ +#define GPP_J 0x7 +#define GPP_K 0x8 +/* GPIO Community 5 */ +#define GPP_G 0x9 +#define GPP_H 0xA +#define GPP_L 0xB +/* GPIO Community 2 */ +#define GPD 0xC + +#define GPIO_NUM_GROUPS 13 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group F */ +#define GPP_F0 48 +#define GPP_F1 49 +#define GPP_F2 50 +#define GPP_F3 51 +#define GPP_F4 52 +#define GPP_F5 53 +#define GPP_F6 54 +#define GPP_F7 55 +#define GPP_F8 56 +#define GPP_F9 57 +#define GPP_F10 58 +#define GPP_F11 59 +#define GPP_F12 60 +#define GPP_F13 61 +#define GPP_F14 62 +#define GPP_F15 63 +#define GPP_F16 64 +#define GPP_F17 65 +#define GPP_F18 66 +#define GPP_F19 67 +#define GPP_F20 68 +#define GPP_F21 69 +#define GPP_F22 70 +#define GPP_F23 71 + +#define NUM_GPIO_COM0_PADS (GPP_F23 - GPP_A0 + 1) + +/* Group C */ +#define GPP_C0 72 +#define GPP_C1 73 +#define GPP_C2 74 +#define GPP_C3 75 +#define GPP_C4 76 +#define GPP_C5 77 +#define GPP_C6 78 +#define GPP_C7 79 +#define GPP_C8 80 +#define GPP_C9 81 +#define GPP_C10 82 +#define GPP_C11 83 +#define GPP_C12 84 +#define GPP_C13 85 +#define GPP_C14 86 +#define GPP_C15 87 +#define GPP_C16 88 +#define GPP_C17 89 +#define GPP_C18 90 +#define GPP_C19 91 +#define GPP_C20 92 +#define GPP_C21 93 +#define GPP_C22 94 +#define GPP_C23 95 +/* Group D */ +#define GPP_D0 96 +#define GPP_D1 97 +#define GPP_D2 98 +#define GPP_D3 99 +#define GPP_D4 100 +#define GPP_D5 101 +#define GPP_D6 102 +#define GPP_D7 103 +#define GPP_D8 104 +#define GPP_D9 105 +#define GPP_D10 106 +#define GPP_D11 107 +#define GPP_D12 108 +#define GPP_D13 109 +#define GPP_D14 110 +#define GPP_D15 111 +#define GPP_D16 112 +#define GPP_D17 113 +#define GPP_D18 114 +#define GPP_D19 115 +#define GPP_D20 116 +#define GPP_D21 117 +#define GPP_D22 118 +#define GPP_D23 119 +/* Group E */ +#define GPP_E0 120 +#define GPP_E1 121 +#define GPP_E2 122 +#define GPP_E3 123 +#define GPP_E4 124 +#define GPP_E5 125 +#define GPP_E6 126 +#define GPP_E7 127 +#define GPP_E8 128 +#define GPP_E9 129 +#define GPP_E10 130 +#define GPP_E11 131 +#define GPP_E12 132 + +#define NUM_GPIO_COM1_PADS (GPP_E12 - GPP_C0 + 1) + +/* Group I */ +#define GPP_I0 133 +#define GPP_I1 134 +#define GPP_I2 135 +#define GPP_I3 136 +#define GPP_I4 137 +#define GPP_I5 138 +#define GPP_I6 139 +#define GPP_I7 140 +#define GPP_I8 141 +#define GPP_I9 142 +#define GPP_I10 143 +#define RCOMP_3P3 144 + +#define NUM_GPIO_COM3_PADS (RCOMP_3P3 - GPP_I0 + 1) + +/* Group J */ +#define GPP_J0 145 +#define GPP_J1 146 +#define GPP_J2 147 +#define GPP_J3 148 +#define GPP_J4 149 +#define GPP_J5 150 +#define GPP_J6 151 +#define GPP_J7 152 +#define GPP_J8 153 +#define GPP_J9 154 +#define GPP_J10 155 +#define GPP_J11 156 +#define GPP_J12 157 +#define GPP_J13 158 +#define GPP_J14 159 +#define GPP_J15 160 +#define GPP_J16 161 +#define GPP_J17 162 +#define GPP_J18 163 +#define GPP_J19 164 +#define GPP_J20 165 +#define GPP_J21 166 +#define GPP_J22 167 +#define GPP_J23 168 +/* Group K */ +#define GPP_K0 169 +#define GPP_K1 170 +#define GPP_K2 171 +#define GPP_K3 172 +#define GPP_K4 173 +#define GPP_K5 174 +#define GPP_K6 175 +#define GPP_K7 176 +#define GPP_K8 177 +#define GPP_K9 178 +#define GPP_K10 179 + +#define RCOMP_1P8_3P3 180 + +#define NUM_GPIO_COM4_PADS (RCOMP_1P8_3P3 - GPP_J0 + 1) + +/* Group G */ +#define GPP_G0 181 +#define GPP_G1 182 +#define GPP_G2 183 +#define GPP_G3 184 +#define GPP_G4 185 +#define GPP_G5 186 +#define GPP_G6 187 +#define GPP_G7 188 +#define GPP_G8 189 +#define GPP_G9 190 +#define GPP_G10 191 +#define GPP_G11 192 +#define GPP_G12 193 +#define GPP_G13 194 +#define GPP_G14 195 +#define GPP_G15 196 +#define GPP_G16 197 +#define GPP_G17 198 +#define GPP_G18 199 +#define GPP_G19 200 +#define GPP_G20 201 +#define GPP_G21 202 +#define GPP_G22 203 +#define GPP_G23 204 +/* Group H */ +#define GPP_H0 205 +#define GPP_H1 206 +#define GPP_H2 207 +#define GPP_H3 208 +#define GPP_H4 209 +#define GPP_H5 210 +#define GPP_H6 211 +#define GPP_H7 212 +#define GPP_H8 213 +#define GPP_H9 214 +#define GPP_H10 215 +#define GPP_H11 216 +#define GPP_H12 217 +#define GPP_H13 218 +#define GPP_H14 219 +#define GPP_H15 220 +#define GPP_H16 221 +#define GPP_H17 222 +#define GPP_H18 223 +#define GPP_H19 224 +#define GPP_H20 225 +#define GPP_H21 226 +#define GPP_H22 227 +#define GPP_H23 228 +/* Group L */ +#define GPP_L2 229 +#define GPP_L3 230 +#define GPP_L4 231 +#define GPP_L5 232 +#define GPP_L6 233 +#define GPP_L7 234 +#define GPP_L8 235 +#define GPP_L9 236 +#define GPP_L10 237 +#define GPP_L11 238 +#define GPP_L12 239 +#define GPP_L13 240 +#define GPP_L14 241 +#define GPP_L15 242 +#define GPP_L16 243 +#define GPP_L17 244 +#define GPP_L18 245 +#define GPP_L19 246 + +#define NUM_GPIO_COM5_PADS (GPP_L23 - GPP_G0 + 1) + +/* Group GPD */ +#define GPD0 247 +#define GPD1 248 +#define GPD2 249 +#define GPD3 250 +#define GPD4 251 +#define GPD5 252 +#define GPD6 253 +#define GPD7 254 +#define GPD8 255 +#define GPD9 256 +#define GPD10 257 +#define GPD11 258 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#endif diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index 71affd8..1185e17 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -20,6 +20,8 @@ * Port ids */ #define PID_PSTH 0x89 +#define PID_GPIOCOM5 0x11 +#define PID_GPIOCOM4 0xAB #define PID_GPIOCOM3 0xAC #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE -- To view, visit https://review.coreboot.org/c/coreboot/+/35031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Gerrit-Change-Number: 35031 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019