coreboot-gerrit July 2019

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34268 ) Change subject: soc/intel/fsp_baytrail: Add missing typedef gpio_t ...................................................................... soc/intel/fsp_baytrail: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I63d59c3f41b7cfe223e8d37b72a388c8d09ac732 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_baytrail/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/34268/1 diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 3549894..b8b95d7 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -330,6 +330,9 @@ u32 sci : 1; } __packed; +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + struct soc_gpio_config { const struct soc_gpio_map *ncore; const struct soc_gpio_map *score; -- To view, visit https://review.coreboot.org/c/coreboot/+/34268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63d59c3f41b7cfe223e8d37b72a388c8d09ac732 Gerrit-Change-Number: 34268 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34267 ) Change subject: soc/intel/denverton_ns: Add missing typedef gpio_t ...................................................................... soc/intel/denverton_ns: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I9dc90201eb1a344a9e9b379fe08a2af7807026ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/denverton_ns/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/34267/1 diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h index 082de21..860b95b 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -49,4 +49,7 @@ #include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in lines above and soc/gpio_defs.h */ +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + #endif /* _SOC_DENVERTON_NS_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc90201eb1a344a9e9b379fe08a2af7807026ed Gerrit-Change-Number: 34267 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34266 ) Change subject: soc/intel/cannonlake: Add missing typedef gpio_t ...................................................................... soc/intel/cannonlake: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I6bc27515262ece228c4a08be992e50ed89962211 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/include/soc/gpio.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34266/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index e7056eb..80393e9 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -28,6 +28,10 @@ #ifndef __ACPI__ struct pad_config; void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); + +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bc27515262ece228c4a08be992e50ed89962211 Gerrit-Change-Number: 34266 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34265 ) Change subject: soc/intel/broadwell: Add missing typedef gpio_t ...................................................................... soc/intel/broadwell: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I55770e969a7949f3b9a35b8a23ed07ba969cad3b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/34265/1 diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index c0ac134..d97cb03 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -162,6 +162,9 @@ .owner = GPIO_OWNER_GPIO, \ .conf1 = GPIO_SENSE_DISABLE } +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + struct gpio_config { u8 gpio; u32 conf0; -- To view, visit https://review.coreboot.org/c/coreboot/+/34265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55770e969a7949f3b9a35b8a23ed07ba969cad3b Gerrit-Change-Number: 34265 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34262 ) Change subject: soc/amd/stoneyridge: Add missing typedef gpio_t ...................................................................... soc/amd/stoneyridge: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: Ib3e4b08df4419b20113059b513126830b5174e99 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34262/1 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index d8774f0..115462d 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -23,6 +23,9 @@ #include <soc/iomap.h> #include <amdblocks/gpio_banks.h> +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + /* The following sections describe only the GPIOs defined for this SOC */ #define SOC_GPIO_TOTAL_PINS 149 -- To view, visit https://review.coreboot.org/c/coreboot/+/34262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3e4b08df4419b20113059b513126830b5174e99 Gerrit-Change-Number: 34262 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Correct 'gpio_t' typedef
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34260 ) Change subject: soc/intel/fsp_broadwell_de: Correct 'gpio_t' typedef ...................................................................... soc/intel/fsp_broadwell_de: Correct 'gpio_t' typedef <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I62b39a53ad14cefe6e98c772e8a3c4d80dd5d84e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_broadwell_de/include/soc/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/34260/1 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h index 1159d03..6a2d2f2 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h @@ -121,7 +121,7 @@ /* Define gpio_t here to be able to use src/include/gpio.h for gpio_set() and gpio_get().*/ -typedef uint8_t gpio_t; +typedef uint32_t gpio_t; /* Configure GPIOs with mainboard provided settings */ void init_gpios(const struct gpio_config config[]); -- To view, visit https://review.coreboot.org/c/coreboot/+/34260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62b39a53ad14cefe6e98c772e8a3c4d80dd5d84e Gerrit-Change-Number: 34260 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34263 ) Change subject: soc/intel/apollolake: Add missing typedef gpio_t ...................................................................... soc/intel/apollolake: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I1ede5e9ebb6bdcd9f49b8d67ab53d0fddb1a3d24 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/include/soc/gpio.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34263/1 diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 939c449..ca3b96b 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -24,4 +24,8 @@ #endif #include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in soc/gpio_glk.h and soc/gpio_apl.h */ + +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ede5e9ebb6bdcd9f49b8d67ab53d0fddb1a3d24 Gerrit-Change-Number: 34263 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT
by HAOUAS Elyes (Code Review) 18 Oct '19

18 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34438 ) Change subject: bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT ...................................................................... bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT Found-by: util/lint/kconfig_lint Change-Id: I8d2001a614e8317b3d3c4f247afe8e6470b7e128 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-q35/bootblock.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/soc/intel/broadwell/bootblock/systemagent.c 6 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34438/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index d5ca7f9..354db3c 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -26,12 +26,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index c076c55..8ac89d8 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -23,12 +23,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 2c1bd58..c63283d 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -21,12 +21,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 604088b..68a0f63 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -22,12 +22,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. * That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1..86882fc 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -22,12 +22,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 7aaed78..01a77d9 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -24,12 +24,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. -- To view, visit https://review.coreboot.org/c/coreboot/+/34438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2001a614e8317b3d3c4f247afe8e6470b7e128 Gerrit-Change-Number: 34438 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: modify vdram1 voltage
by hsin-hsiung wang (Code Review) 18 Oct '19

18 Oct '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33186 Change subject: mediatek/mt8183: modify vdram1 voltage ...................................................................... mediatek/mt8183: modify vdram1 voltage Dram DVFS needs calibration with different vdram1 voltage to get correct parameters, so we provide a api to change vdram1 voltage. BUG=b:80501386 BRANCH=none TEST=measure vdram1 voltage with multimeter Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33186/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 02937ba..c90e6e4 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -26,6 +26,9 @@ PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_VDRAM1_OP_EN = 0x1610, + PMIC_VDRAM1_DBG0 = 0x161e, + PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, }; @@ -38,5 +41,7 @@ void mt6358_init(void); void pmic_set_power_hold(bool enable); +unsigned int pmic_get_vdram1_vol(void); +void pmic_set_vdram1_vol(unsigned int vdram_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7054243..ea4e7bd 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -733,6 +733,29 @@ pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); } +unsigned int pmic_get_vdram1_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); + return (500000 + vol_reg * 12500); +} + +void pmic_set_vdram1_vol(unsigned int vdram_uv) +{ + unsigned int vol_reg; + + if (500000 > vdram_uv) + vol_reg = 0; + else if (vdram_uv > 1300000) + vol_reg = 0x40; + else + vol_reg = (vdram_uv - 500000) / 12500; + + pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Gerrit-Change-Number: 33186 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: NOT_FOR_MERGE: soc/amd/picasso: Disable BERT table generation
by Marshall Dawson (Code Review) 17 Oct '19

17 Oct '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34426 to review the following change. Change subject: NOT_FOR_MERGE: soc/amd/picasso: Disable BERT table generation ...................................................................... NOT_FOR_MERGE: soc/amd/picasso: Disable BERT table generation For the moment, the reserved memory for BERT goofs our presumed memory map. Change-Id: I789ece3c324b88652dc60776afe5a7b9edf08b2a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/34426/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3c27f15..fd1b221 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -232,7 +232,6 @@ config ACPI_BERT bool "Build ACPI BERT Table" - default y depends on HAVE_ACPI_TABLES help Report Machine Check errors identified in POST to the OS in an -- To view, visit https://review.coreboot.org/c/coreboot/+/34426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I789ece3c324b88652dc60776afe5a7b9edf08b2a Gerrit-Change-Number: 34426 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019