coreboot-gerrit July 2019

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Change in coreboot[master]: device: Fix naked reference to CONFIG_DEBUG_RAM_SETUP
by HAOUAS Elyes (Code Review) 23 Nov '19

23 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34439 ) Change subject: device: Fix naked reference to CONFIG_DEBUG_RAM_SETUP ...................................................................... device: Fix naked reference to CONFIG_DEBUG_RAM_SETUP Found-by: util/lint/kconfig_lint Change-Id: I360c4f563c2aa2acc740eac6c4e0145bda18edb7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr2.c M src/device/dram/ddr3.c M src/include/device/dram/common.h M src/include/device/dram/ddr3.h 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/34439/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 60588b8..eec2d74 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -668,8 +668,8 @@ /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is -* selected, or for a purely informative output. +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is +* true, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure */ diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 834dc83..8d79710 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -624,8 +624,8 @@ /** * \brief Print the info in DIMM * -* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is -* selected, or for a purely informative output. +* Print info about the DIMM. Useful to use when CONFIG(DEBUG_RAM_SETUP) is +* true, or for a purely informative output. * * @param dimm pointer to already decoded @ref dimm_attr structure */ diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index b1677c8..7be58ab 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -45,10 +45,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is not selected, these messages are automatically * disabled. * @{ */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0f9373e..19bce96 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -49,10 +49,10 @@ /** @} */ /** - * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * \brief Convenience macro for enabling printk with CONFIG(DEBUG_RAM_SETUP) * * Use this macro instead of printk(); for verbose RAM initialization messages. - * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * When CONFIG(DEBUG_RAM_SETUP) is false, these messages are automatically * disabled. * @{ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I360c4f563c2aa2acc740eac6c4e0145bda18edb7 Gerrit-Change-Number: 34439 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/t430: Add support for MRC raminit
by Petr K (Code Review) 22 Nov '19

22 Nov '19

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33539 Change subject: mb/lenovo/t430: Add support for MRC raminit ...................................................................... mb/lenovo/t430: Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on 32500 Signed-off-by: Petr K <piotrkloc94(a)hotmail.com> Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/romstage.c 3 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/33539/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 2731b69..a992377 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,32 @@ end end + # PEI data + + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index db50bb3..fa46dc3 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -96,3 +97,19 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + + +void mainboard_fill_pei_data(struct pei_data *pei_data) + +{ + +} + + +int mainboard_should_reset_usb(int s3resume) + +{ + + return !s3resume; + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e097f7bb6b1de55b9e6a84efa4f9c630cee0745 Gerrit-Change-Number: 33539 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci: Reduce scope of dev_find_slot()
by Kyösti Mälkki (Code Review) 21 Nov '19

21 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34084 ) Change subject: device/pci: Reduce scope of dev_find_slot() ...................................................................... device/pci: Reduce scope of dev_find_slot() We only keep it around because amdfam10 does not yet work correctly without it. Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34084/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index c1b0b06..691cd80 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -35,6 +35,8 @@ * @param devfn A device/function number. * @return Pointer to the device structure (if found), 0 otherwise. */ + +#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10) DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn) { @@ -51,6 +53,7 @@ } return result; } +#endif /** * Given a Device Path Type, find the device structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/34084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307 Gerrit-Change-Number: 34084 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL)
by HAOUAS Elyes (Code Review) 21 Nov '19

21 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32915 Change subject: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) ...................................................................... {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) i945/early_init.c already set to 'RCBA32(V0CTL) = 0x80000001' Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c84..9ab4af1 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -140,9 +140,6 @@ static void rcba_config(void) { - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 0c7c0cf..8c0b3e4 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 502eac3..2404fb7 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; -- To view, visit https://review.coreboot.org/c/coreboot/+/32915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Gerrit-Change-Number: 32915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/spi: Use 64 bits in multiplication
by Jacob Garber (Code Review) 20 Nov '19

20 Nov '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34373 ) Change subject: drivers/spi: Use 64 bits in multiplication ...................................................................... drivers/spi: Use 64 bits in multiplication speed is a 64 bit variable, so use 64 bits in the intermediate calculations to avoid possible overflow. Change-Id: Id36eda6d64057cde4750184d03c9701011edb890 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1402094 --- M src/drivers/spi/cbfs_spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34373/1 diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index ad282c6..9437c2e 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -55,7 +55,7 @@ u64 speed; /* KiB/s */ int bps; /* Bits per second */ - speed = size * 1000 / usecs; + speed = size * 1000ULL / usecs; bps = speed * 8; printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/34373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36eda6d64057cde4750184d03c9701011edb890 Gerrit-Change-Number: 34373 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/supermicro: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 20 Nov '19

20 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33897 Change subject: mainboard/supermicro: remove stdlib.h when unused ...................................................................... mainboard/supermicro: remove stdlib.h when unused Change-Id: Ib9946d9a6e9d3a9a64b8d7909faed805b55bff02 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c M src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c 3 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/33897/1 diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index 6279d9c..5f4d9f3 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index f32312d..1d06155 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -21,10 +21,8 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> #include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 8bc96c2..58a23bb 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -16,9 +16,7 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> -#include <stdlib.h> #include <cpu/amd/multicore.h> - #include <cpu/amd/amdfam10_sysconf.h> /* Global variables for MB layouts and these will be shared by irqtable mptable -- To view, visit https://review.coreboot.org/c/coreboot/+/33897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9946d9a6e9d3a9a64b8d7909faed805b55bff02 Gerrit-Change-Number: 33897 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd/amdmct/mct: Fix condition whith identical branches
by HAOUAS Elyes (Code Review) 20 Nov '19

20 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34207 ) Change subject: nb/amd/amdmct/mct: Fix condition whith identical branches ...................................................................... nb/amd/amdmct/mct: Fix condition whith identical branches Change-Id: Ie5ee2e2527c6745381c7bdd2cbe3212fdd28e8ba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdmct/mct/mctardk4.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/34207/1 diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 2e16a80..6c40d68 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -118,12 +118,8 @@ if (Speed == 3) { *AddrTmgCTL = 0x00202220; } else if (Speed == 2) { - if (MAAload == 4) + if (MAAload == 4 || MAAload == 16) *AddrTmgCTL = 0x002B2F00; - else if (MAAload == 16) - *AddrTmgCTL = 0x002B2F00; - else if (MAAload == 8) - *AddrTmgCTL = 0x002F2F00; else *AddrTmgCTL = 0x002F2F00; } else if (Speed == 1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/34207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ee2e2527c6745381c7bdd2cbe3212fdd28e8ba Gerrit-Change-Number: 34207 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/fsp_rangeley: Fix naked reference to CONFIG_CONSOLE_POST
by HAOUAS Elyes (Code Review) 20 Nov '19

20 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34436 ) Change subject: sb/intel/fsp_rangeley: Fix naked reference to CONFIG_CONSOLE_POST ...................................................................... sb/intel/fsp_rangeley: Fix naked reference to CONFIG_CONSOLE_POST Change-Id: I82d696ec79cb8a182e6b35de70c0e1ede2fa0bd9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/fsp_rangeley/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34436/1 diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2c2427e..297e1c4 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -43,7 +43,7 @@ * This causes the I/O to clog and a side effect is * that the reset button stops functioning. So * instead just use outb so it doesn't output to the - * console when CONFIG_CONSOLE_POST. + * console when CONFIG(CONSOLE_POST). */ outb(0x40, 0x80); -- To view, visit https://review.coreboot.org/c/coreboot/+/34436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d696ec79cb8a182e6b35de70c0e1ede2fa0bd9 Gerrit-Change-Number: 34436 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/nvidia/ck804: Fix naked reference to CONFIG_NORTHBRIDGE_AMD_AMDFAM10
by HAOUAS Elyes (Code Review) 20 Nov '19

20 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34437 ) Change subject: sb/nvidia/ck804: Fix naked reference to CONFIG_NORTHBRIDGE_AMD_AMDFAM10 ...................................................................... sb/nvidia/ck804: Fix naked reference to CONFIG_NORTHBRIDGE_AMD_AMDFAM10 Change-Id: I7c2e1370c1f3332cee85ae6c8f0515df778ecc73 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/nvidia/ck804/early_setup_car.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/34437/1 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index e2cc40a..d21ec8d 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -253,7 +253,7 @@ RES_PCI_IO, CK804_DEV(9, 0, 0x74), 0xffffffc0, 0x00000000, /* - * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * Avoid touching 0x78 for CONFIG(NORTHBRIDGE_AMD_AMDFAM10) for * non-primary chains too??? */ RES_PCI_IO, CK804_DEV(1, 0, 0x78), 0xc0ffffff, 0x20000000, -- To view, visit https://review.coreboot.org/c/coreboot/+/34437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c2e1370c1f3332cee85ae6c8f0515df778ecc73 Gerrit-Change-Number: 34437 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: build system: Add various compiler flags that enable warnings on UB
by Patrick Georgi (Code Review) 18 Nov '19

18 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32814 Change subject: build system: Add various compiler flags that enable warnings on UB ...................................................................... build system: Add various compiler flags that enable warnings on UB Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32814/1 diff --git a/Makefile.inc b/Makefile.inc index 9860da1..f2e010c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -410,6 +410,8 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack +CFLAGS_common += -pedantic-errors -Wnull-dereference +CFLAGS_common += -Wno-aggressive-loop-optimizations -Wreturn-type # cf. commit f69a99db (coreboot: x86: enable gc-sections) CFLAGS_common += -Wno-unused-but-set-variable endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Gerrit-Change-Number: 32814 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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