coreboot-gerrit July 2019

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Change in coreboot[master]: soc/amd/stoneyridge,picasso: Switch SMM lock condition
by Kyösti Mälkki (Code Review) 09 Jul '19

09 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34127 ) Change subject: soc/amd/stoneyridge,picasso: Switch SMM lock condition ...................................................................... soc/amd/stoneyridge,picasso: Switch SMM lock condition SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for this platform in coreboot codebase. The SMM lock should be set based on whether SMM is installed or not, HAVE_SMI_HANDLER currently tells that. Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/picasso/finalize.c M src/soc/amd/stoneyridge/finalize.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34127/1 diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 6572e1a..5a4627a 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -29,7 +29,7 @@ if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (CONFIG(SMM_TSEG)) { + if (CONFIG(HAVE_SMI_HANDLER)) { mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 6572e1a..5a4627a 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -29,7 +29,7 @@ if (hwcr.lo & SMM_LOCK) /* Skip if already locked, avoid GPF */ return; - if (CONFIG(SMM_TSEG)) { + if (CONFIG(HAVE_SMI_HANDLER)) { mask = rdmsr(SMM_MASK_MSR); mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); -- To view, visit https://review.coreboot.org/c/coreboot/+/34127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46 Gerrit-Change-Number: 34127 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Replace some uses of SMM_TSEG
by Kyösti Mälkki (Code Review) 09 Jul '19

09 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34126 ) Change subject: arch/x86: Replace some uses of SMM_TSEG ...................................................................... arch/x86: Replace some uses of SMM_TSEG No reason why the files could not be used with ASEG. Attempts to use malloc() from ASEG would still fail, though, due the lack of heap. Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/Makefile.inc M src/lib/Makefile.inc 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/34126/1 diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 4f0c2ef..3311849 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -8,8 +8,8 @@ endif smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c -smm-$(CONFIG_SMM_TSEG) += die.c -smm-$(CONFIG_SMM_TSEG) += post.c +smm-y += die.c +smm-y += post.c verstage-y += init.c verstage-y += printk.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f6d3f6d..f0738ee 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -117,7 +117,6 @@ ramstage-y += memchr.c ramstage-y += memcmp.c ramstage-y += malloc.c -smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += dimm_info_util.c ramstage-y += delay.c ramstage-y += fallback_boot.c @@ -190,6 +189,7 @@ ramstage-y += boot_device.c smm-y += boot_device.c +smm-y += malloc.c smm-y += delay.c smm-y += fmap.c smm-y += cbfs.c memcmp.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638 Gerrit-Change-Number: 34126 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class
by Kyösti Mälkki (Code Review) 09 Jul '19

09 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34125 ) Change subject: arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class ...................................................................... arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/pi/00630F01/Makefile.inc M src/cpu/intel/common/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/ec/acpi/Makefile.inc M src/ec/lenovo/pmh7/Makefile.inc M src/mainboard/google/auron/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/butterfly/Makefile.inc M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/dragonegg/Makefile.inc M src/mainboard/google/eve/Makefile.inc M src/mainboard/google/fizz/Makefile.inc M src/mainboard/google/fizz/variants/karma/Makefile.inc M src/mainboard/google/glados/Makefile.inc M src/mainboard/google/glados/variants/caroline/Makefile.inc M src/mainboard/google/glados/variants/cave/Makefile.inc M src/mainboard/google/glados/variants/chell/Makefile.inc M src/mainboard/google/glados/variants/glados/Makefile.inc M src/mainboard/google/hatch/Makefile.inc M src/mainboard/google/jecht/Makefile.inc M src/mainboard/google/kahlee/Makefile.inc M src/mainboard/google/link/Makefile.inc M src/mainboard/google/octopus/Makefile.inc M src/mainboard/google/poppy/Makefile.inc M src/mainboard/google/poppy/variants/nami/Makefile.inc M src/mainboard/google/poppy/variants/nautilus/Makefile.inc M src/mainboard/google/poppy/variants/nocturne/Makefile.inc M src/mainboard/google/rambi/Makefile.inc M src/mainboard/google/reef/Makefile.inc M src/mainboard/google/sarien/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/google/stout/Makefile.inc M src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/mainboard/intel/cannonlake_rvp/Makefile.inc M src/mainboard/intel/dcp847ske/Makefile.inc M src/mainboard/intel/glkrvp/Makefile.inc M src/mainboard/intel/kblrvp/Makefile.inc M src/mainboard/intel/kunimitsu/Makefile.inc M src/mainboard/intel/strago/Makefile.inc M src/mainboard/lenovo/g505s/Makefile.inc M src/mainboard/lenovo/l520/Makefile.inc M src/mainboard/lenovo/s230u/Makefile.inc M src/mainboard/lenovo/t420/Makefile.inc M src/mainboard/lenovo/t420s/Makefile.inc M src/mainboard/lenovo/t430/Makefile.inc M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t520/Makefile.inc M src/mainboard/lenovo/t530/Makefile.inc M src/mainboard/lenovo/t60/Makefile.inc M src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc M src/mainboard/lenovo/x201/Makefile.inc M src/mainboard/lenovo/x220/Makefile.inc M src/mainboard/lenovo/x230/Makefile.inc M src/mainboard/lenovo/x60/Makefile.inc M src/mainboard/lenovo/z61t/Makefile.inc M src/mainboard/packardbell/ms2290/Makefile.inc M src/mainboard/scaleway/tagada/Makefile.inc M src/northbridge/intel/fsp_rangeley/Makefile.inc M src/northbridge/intel/gm45/Makefile.inc M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/nehalem/Makefile.inc M src/northbridge/intel/sandybridge/Makefile.inc M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801gx/Makefile.inc M src/southbridge/intel/i82801ix/Makefile.inc M src/southbridge/intel/i82801jx/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc 80 files changed, 100 insertions(+), 105 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/34125/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 025b933..32e0173 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -404,8 +404,6 @@ smm-y += memset.c smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),) smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c endif -endif diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 98a7050..46ae346 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c +smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 98a7050..46ae346 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c +smm-y += udelay.c subdirs-y += ../../mtrr subdirs-y += ../../smm diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index b67ca85..2fc6da9 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -2,4 +2,4 @@ romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c +smm-y += fsb.c diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 72f66ef..a472da2 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -13,8 +13,8 @@ romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += finalize.c +smm-y += tsc_freq.c ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) bootblock-y += monotonic_timer.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index f494e9b..9a11b06 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -13,11 +13,11 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c ramstage-y += acpi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c romstage-y += stage_cache.c ramstage-y += stage_cache.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 78a6283..f5de8c3 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -15,14 +15,14 @@ ramstage-y += common.c romstage-y += common.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c +smm-y += common.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index e6add1d..5c7aab3 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -36,13 +36,16 @@ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual +endif + ifeq ($(CONFIG_SMM_TSEG),y) smmstub-y += smm_stub.S smm-y += smm_module_handler.c -ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual # SMM Stub Module. The stub is used as a trampoline for relocation and normal @@ -82,10 +85,6 @@ $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) -ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual -endif - smm-y += smmhandler.S smm-y += smihandler.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 9751cac..ab7453f 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -3,6 +3,4 @@ romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c -endif diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index 34fc307..fae8fbf 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -2,6 +2,6 @@ ramstage-y += ec.c romstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c +smm-y += ec.c endif diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index a619cc7..d5524dc 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,7 +1,7 @@ ifeq ($(CONFIG_EC_LENOVO_PMH7),y) ramstage-y += pmh7.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c +smm-y += pmh7.c romstage-y += pmh7.c endif diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index d2b6d0e..6b1de05 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -19,7 +19,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index bb90e97..e1bebc1 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -18,7 +18,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c ramstage-y += lan.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c variants/$(VARIANT_DIR)/led.c +smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 8033e1c..b6654b8 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -19,6 +19,6 @@ ramstage-y += chromeos.c romstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 027c49c..86198a6 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -24,7 +24,7 @@ ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/dragonegg/Makefile.inc b/src/mainboard/google/dragonegg/Makefile.inc index 39e94d0..dcd8cbc 100644 --- a/src/mainboard/google/dragonegg/Makefile.inc +++ b/src/mainboard/google/dragonegg/Makefile.inc @@ -26,7 +26,7 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/eve/Makefile.inc b/src/mainboard/google/eve/Makefile.inc index c96e23e..d853404 100644 --- a/src/mainboard/google/eve/Makefile.inc +++ b/src/mainboard/google/eve/Makefile.inc @@ -26,4 +26,4 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 59f84b5..5514090 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -25,7 +25,7 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/fizz/variants/karma/Makefile.inc b/src/mainboard/google/fizz/variants/karma/Makefile.inc index 7475522..ec115e4 100644 --- a/src/mainboard/google/fizz/variants/karma/Makefile.inc +++ b/src/mainboard/google/fizz/variants/karma/Makefile.inc @@ -3,4 +3,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc index ccfeb85..da9de29 100644 --- a/src/mainboard/google/glados/Makefile.inc +++ b/src/mainboard/google/glados/Makefile.inc @@ -29,7 +29,7 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/glados/variants/caroline/Makefile.inc b/src/mainboard/google/glados/variants/caroline/Makefile.inc index 73d7090..21b20e6 100644 --- a/src/mainboard/google/glados/variants/caroline/Makefile.inc +++ b/src/mainboard/google/glados/variants/caroline/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/cave/Makefile.inc b/src/mainboard/google/glados/variants/cave/Makefile.inc index 5d95e34..f3b52c2 100644 --- a/src/mainboard/google/glados/variants/cave/Makefile.inc +++ b/src/mainboard/google/glados/variants/cave/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/chell/Makefile.inc b/src/mainboard/google/glados/variants/chell/Makefile.inc index 2eff4b1..986bdd8 100644 --- a/src/mainboard/google/glados/variants/chell/Makefile.inc +++ b/src/mainboard/google/glados/variants/chell/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/glados/variants/glados/Makefile.inc b/src/mainboard/google/glados/variants/glados/Makefile.inc index 82dbcad..b6dbbd4 100644 --- a/src/mainboard/google/glados/variants/glados/Makefile.inc +++ b/src/mainboard/google/glados/variants/glados/Makefile.inc @@ -16,7 +16,7 @@ romstage-y += variant.c ramstage-y += variant.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += variant.c +smm-y += variant.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index 3f35f82..01a1eb8 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -24,7 +24,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 116792f..9ea24f6 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -19,7 +19,7 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c +smm-y += smihandler.c led.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 770a999..0abd884 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -29,7 +29,7 @@ verstage-y += chromeos.c verstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 89bb365..e6c7be1 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index 1a9adbc..aa05524 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -8,7 +8,7 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/poppy/Makefile.inc b/src/mainboard/google/poppy/Makefile.inc index 86754e6..030cf1d 100644 --- a/src/mainboard/google/poppy/Makefile.inc +++ b/src/mainboard/google/poppy/Makefile.inc @@ -25,7 +25,7 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 0033c60..7c1e480 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -35,7 +35,7 @@ ramstage-y += nhlt.c ramstage-y += mainboard.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c # Add OEM ID table cbfs-files-y += oem.bin diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc index c715206..3a36b83b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc @@ -14,5 +14,5 @@ ramstage-y += mainboard.c ramstage-y += sku.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += sku.c +smm-y += smihandler.c +smm-y += sku.c diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc index 260d9c0..371655a 100644 --- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += mainboard.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c +smm-y += ec.c diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index 7c0fb35..0e80b64 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -19,7 +19,7 @@ ramstage-y += irqroute.c ramstage-y += w25q64.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc index 3701a91..a115677 100644 --- a/src/mainboard/google/reef/Makefile.inc +++ b/src/mainboard/google/reef/Makefile.inc @@ -8,7 +8,7 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 7c37bc9..7e23044 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -20,7 +20,7 @@ romstage-y += romstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 53e8dff..921f9e7 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -18,7 +18,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index be1f0fe..f4f2284 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -18,8 +18,8 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c +smm-y += mainboard_smi.c +smm-y += ec.c SRC_ROOT = $(src)/mainboard/google/stout romstage-y += gpio.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 80dd0d2..f030989 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += OemCustomize.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 06e86c1..e34704d 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,4 +17,4 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index c18fd9b..d984771 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -27,7 +27,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/dcp847ske/Makefile.inc b/src/mainboard/intel/dcp847ske/Makefile.inc index 4d516f6..96bac06 100644 --- a/src/mainboard/intel/dcp847ske/Makefile.inc +++ b/src/mainboard/intel/dcp847ske/Makefile.inc @@ -1,4 +1,4 @@ romstage-y += early_southbridge.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/intel/glkrvp/Makefile.inc b/src/mainboard/intel/glkrvp/Makefile.inc index f2da379..ea5b2c6 100644 --- a/src/mainboard/intel/glkrvp/Makefile.inc +++ b/src/mainboard/intel/glkrvp/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += mainboard.c verstage-$(CONFIG_CHROMEOS) += chromeos.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index 6da41ae..ffed7a2 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -33,7 +33,7 @@ ramstage-y += hda_verb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index 3330a0a..933074b 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -28,7 +28,7 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index e6f0c9e..3f88b3d 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -25,4 +25,4 @@ ramstage-y += ramstage.c ramstage-y += w25q64.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index 80dd0d2..f030989 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -22,4 +22,4 @@ ramstage-y += OemCustomize.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-y += mainboard_smi.c diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 2aa7f0f..2ce116f 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -15,6 +15,6 @@ romstage-y += romstage.c romstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index dea2e4e..88626a2 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -1,6 +1,6 @@ romstage-y += gpio.c ramstage-y += ec.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c # FIXME: SPD images for samsung_8gb and hynix_8gb are missing. # It's possible that no mainboards with that variation were manufactured. diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 2dab950..30cf715 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 2dab950..30cf715 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index ada25f7..558ab0a 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,5 +1,5 @@ romstage-y += romstage.c romstage-y += gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index d70c22e..4008f5a 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 7187013..ee4669c 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 7187013..ee4669c 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index 8473a13..f646af8 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -13,6 +13,6 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-y += dock.c romstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index ee08d78..63b41a4 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -15,7 +15,7 @@ subdirs-y += spd -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc index f7ff93b..f972356 100644 --- a/src/mainboard/lenovo/x201/Makefile.inc +++ b/src/mainboard/lenovo/x201/Makefile.inc @@ -13,8 +13,8 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += dock.c +smm-y += smihandler.c romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index 2c52c21..a1cbc4c 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 2dab950..30cf715 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index 4b17ea8..a7ad539 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-y += dock.c romstage-y += dock.c ramstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/lenovo/z61t/Makefile.inc b/src/mainboard/lenovo/z61t/Makefile.inc index 8473a13..f646af8 100644 --- a/src/mainboard/lenovo/z61t/Makefile.inc +++ b/src/mainboard/lenovo/z61t/Makefile.inc @@ -13,6 +13,6 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-y += dock.c romstage-y += dock.c romstage-y += gpio.c diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index da1f50d..b23d2e5 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -13,6 +13,6 @@ ## GNU General Public License for more details. ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc index c33e993..8370c8a 100644 --- a/src/mainboard/scaleway/tagada/Makefile.inc +++ b/src/mainboard/scaleway/tagada/Makefile.inc @@ -26,6 +26,6 @@ postcar-y += bmcinfo.c romstage-y += bmcinfo.c ramstage-y += bmcinfo.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += bmcinfo.c +smm-y += bmcinfo.c CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc index 410a308..f9bf050 100644 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc @@ -27,7 +27,7 @@ romstage-y += ../../../arch/x86/walkcbfs.S romstage-y += port_access.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c +smm-y += udelay.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index 16a9ddb..e74f475 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -35,7 +35,7 @@ ramstage-y += northbridge.c ramstage-y += gma.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c +smm-y += ../../../cpu/x86/lapic/apic_timer.c postcar-y += ram_calc.c diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 7abbcca..ca1c04f 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -29,7 +29,7 @@ romstage-y += early_init.c romstage-y += report_platform.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 6722621..c0d46c9 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -27,7 +27,7 @@ romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c postcar-y += ram_calc.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index c77f3ba..8a0b67b 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -26,7 +26,7 @@ ramstage-y += common.c romstage-y += common.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c +smm-y += common.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c @@ -46,7 +46,7 @@ romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +smm-y += finalize.c postcar-y += ram_calc.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index e9d5022..cfd8149 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -71,10 +71,10 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_util.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += pmutil.c +smm-y += soc_util.c +smm-y += smihandler.c +smm-y += tsc_freq.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index ca2b353..2fbf34e 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -33,10 +33,10 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += tsc_freq.c ramstage-y += spi.c romstage-y += spi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += spi.c +smm-y += spi.c ramstage-y += chip.c ramstage-y += iosf.c romstage-y += iosf.c @@ -51,8 +51,8 @@ ramstage-y += acpi.c ramstage-y += lpe.c ramstage-y += lpss.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += pmutil.c +smm-y += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index e8a3189..c73c12a 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -31,9 +31,9 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-y += vtd.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5d3d5b4..cd0a1d5 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -31,7 +31,7 @@ romstage-y += imc.c ramstage-y += imc.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c +smm-y += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # ROMSIG At ROMBASE + 0x20000: diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index c7cd757..c8949b0 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -60,8 +60,8 @@ ramstage-$(CONFIG_HUDSON_UART) += uart.c ramstage-y += usb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +smm-y += smihandler.c +smm-y += smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b6023b0..b23fa7a 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -34,7 +34,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 5ba2130..ae0a10f 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -26,7 +26,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 6e7f9bf..237c2d5 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -32,7 +32,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index caa4932..0b9ade8 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -33,7 +33,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_init.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 6626bb5..02da814 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -29,7 +29,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3e3ef35..e53ed8d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -42,8 +42,8 @@ ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c pch.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c +smm-y += smihandler.c me_9.x.c pch.c +smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c @@ -52,7 +52,7 @@ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c +smm-y += lp_gpio.c endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Gerrit-Change-Number: 34125 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mainboard/portwell/m107: Do initial mainboard commit
by Paul Menzel (Code Review) 09 Jul '19

09 Jul '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 16: (4 comments) https://review.coreboot.org/c/coreboot/+/29470/16/Documentation/mainboard/p… File Documentation/mainboard/portwell/pq7-m107.md: https://review.coreboot.org/c/coreboot/+/29470/16/Documentation/mainboard/p… PS16, Line 9: make menuconfig Mark up as code with ``? https://review.coreboot.org/c/coreboot/+/29470/16/Documentation/mainboard/p… PS16, Line 28: to on? https://review.coreboot.org/c/coreboot/+/29470/16/Documentation/mainboard/p… PS16, Line 37: avaiable available https://review.coreboot.org/c/coreboot/+/29470/16/Documentation/mainboard/p… PS16, Line 59: - SeaBIOS payload What version? -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 16 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Jul 2019 12:41:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: add toshiba satellite u940 initial support
by franlego98 franlego98 (Code Review) 09 Jul '19

09 Jul '19

franlego98 franlego98 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34171 ) Change subject: add toshiba satellite u940 initial support ...................................................................... add toshiba satellite u940 initial support Change-Id: Ibaa45ddeed07c2757876e88e8c3d2f4e50d29d8e --- A src/mainboard/toshiba/Kconfig A src/mainboard/toshiba/Kconfig.name A src/mainboard/toshiba/satellite_u940/Kconfig A src/mainboard/toshiba/satellite_u940/Kconfig.name A src/mainboard/toshiba/satellite_u940/Makefile.inc A src/mainboard/toshiba/satellite_u940/acpi/ec.asl A src/mainboard/toshiba/satellite_u940/acpi/platform.asl A src/mainboard/toshiba/satellite_u940/acpi/superio.asl A src/mainboard/toshiba/satellite_u940/acpi_tables.c A src/mainboard/toshiba/satellite_u940/board_info.txt A src/mainboard/toshiba/satellite_u940/devicetree.cb A src/mainboard/toshiba/satellite_u940/dsdt.asl A src/mainboard/toshiba/satellite_u940/gma-mainboard.ads A src/mainboard/toshiba/satellite_u940/gpio.c A src/mainboard/toshiba/satellite_u940/hda_verb.c A src/mainboard/toshiba/satellite_u940/mainboard.c A src/mainboard/toshiba/satellite_u940/romstage.c 17 files changed, 852 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/34171/1 diff --git a/src/mainboard/toshiba/Kconfig b/src/mainboard/toshiba/Kconfig new file mode 100644 index 0000000..1466d64 --- /dev/null +++ b/src/mainboard/toshiba/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_TOSHIBA + +choice + prompt "Mainboard model" + +source "src/mainboard/toshiba/*/Kconfig.name" + +endchoice + +source "src/mainboard/toshiba/*/Kconfig" + +config MAINBOARD_TOSHIBA + string + default "TOSHIBA" + +endif # VENDOR_TOSHIBA diff --git a/src/mainboard/toshiba/Kconfig.name b/src/mainboard/toshiba/Kconfig.name new file mode 100644 index 0000000..47dbb59 --- /dev/null +++ b/src/mainboard/toshiba/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_TOSHIBA + bool "TOSHIBA" diff --git a/src/mainboard/toshiba/satellite_u940/Kconfig b/src/mainboard/toshiba/satellite_u940/Kconfig new file mode 100644 index 0000000..9a13486 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/Kconfig @@ -0,0 +1,48 @@ +if BOARD_TOSHIBA_SATELLITE_U940 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default toshiba/satellite_u940 + +config MAINBOARD_PART_NUMBER + string + default "SATELLITE U940" + +config MAINBOARD_VENDOR + string + default "TOSHIBA" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/toshiba/satellite_u940/Kconfig.name b/src/mainboard/toshiba/satellite_u940/Kconfig.name new file mode 100644 index 0000000..d347bc8 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_TOSHIBA_SATELLITE_U940 + bool "SATELLITE U940" diff --git a/src/mainboard/toshiba/satellite_u940/Makefile.inc b/src/mainboard/toshiba/satellite_u940/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/toshiba/satellite_u940/acpi/ec.asl b/src/mainboard/toshiba/satellite_u940/acpi/ec.asl new file mode 100644 index 0000000..8da2182 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi/ec.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/toshiba/satellite_u940/acpi/platform.asl b/src/mainboard/toshiba/satellite_u940/acpi/platform.asl new file mode 100644 index 0000000..c34ed7d --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi/platform.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/toshiba/satellite_u940/acpi/superio.asl b/src/mainboard/toshiba/satellite_u940/acpi/superio.asl new file mode 100644 index 0000000..4ede634 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi/superio.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/toshiba/satellite_u940/acpi_tables.c b/src/mainboard/toshiba/satellite_u940/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/toshiba/satellite_u940/board_info.txt b/src/mainboard/toshiba/satellite_u940/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/toshiba/satellite_u940/devicetree.cb b/src/mainboard/toshiba/satellite_u940/devicetree.cb new file mode 100644 index 0000000..d1b5780 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x0004fd61" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1179 0xfb30 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1179 0xfb30 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1179 0xfb30 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1179 0xfb30 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1179 0xfb30 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x1179 0xfb30 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1179 0xfb30 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1179 0xfb30 + end + device pci 1f.2 on # SATA Controller 1 Unsupported PCI device 8086:282a + subsystemid 0x1179 0xfb30 + end + device pci 1f.3 on # SMBus + subsystemid 0x1179 0xfb30 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1179 0xfb10 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1179 0xfb10 + end + end +end diff --git a/src/mainboard/toshiba/satellite_u940/dsdt.asl b/src/mainboard/toshiba/satellite_u940/dsdt.asl new file mode 100644 index 0000000..cdaf16d --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/toshiba/satellite_u940/gma-mainboard.ads b/src/mainboard/toshiba/satellite_u940/gma-mainboard.ads new file mode 100644 index 0000000..ce27742 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/toshiba/satellite_u940/gpio.c b/src/mainboard/toshiba/satellite_u940/gpio.c new file mode 100644 index 0000000..44c67ed --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/gpio.c @@ -0,0 +1,238 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio4 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/toshiba/satellite_u940/hda_verb.c b/src/mainboard/toshiba/satellite_u940/hda_verb.c new file mode 100644 index 0000000..d1a1cec --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x1179fb14, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x1179fb14), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60940), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x0421101f), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x04a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005822d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x1179fb30, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x1179fb30), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/toshiba/satellite_u940/mainboard.c b/src/mainboard/toshiba/satellite_u940/mainboard.c new file mode 100644 index 0000000..b15efaf --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/mainboard.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x1b, 0x00, 0x00, 0x00, 0x10, 0x19, 0x00, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x04, 0x0a, 0x14, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x84, 0x81, 0x00, 0x00, 0x61, 0x64, + 0x00, 0x00, 0x08, 0x64, 0x19, 0x00, 0x98, + /* b0 */ 0x00, 0x00, 0x00, 0x3a, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x1f, 0x00, 0x0b, 0x00, 0x00, + /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/toshiba/satellite_u940/romstage.c b/src/mainboard/toshiba/satellite_u940/romstage.c new file mode 100644 index 0000000..b90e7bd --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004fd61); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaa45ddeed07c2757876e88e8c3d2f4e50d29d8e Gerrit-Change-Number: 34171 Gerrit-PatchSet: 1 Gerrit-Owner: franlego98 franlego98 <new.francisco.1998(a)tuta.io> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: AGESA: Fix SMM support in ASEG
by Kyösti Mälkki (Code Review) 09 Jul '19

09 Jul '19

Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Mike Banon, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/21624 to look at the new patch set (#5). Change subject: AGESA: Fix SMM support in ASEG ...................................................................... AGESA: Fix SMM support in ASEG Delay SMI enablement until SMM is configured and do it at end of SMM init sequence. Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/agesa/family16kb/Makefile.inc M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/smm/smm_init.c A src/include/cpu/amd/amdfam16.h M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/lenovo/g505s/mainboard.c M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc 10 files changed, 68 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/21624/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/hatch/variants/helios: Update GPIO table for proto stage
by Ken Lu (Code Review) 09 Jul '19

09 Jul '19

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33826 ) Change subject: mb/google/hatch/variants/helios: Update GPIO table for proto stage ...................................................................... Patch Set 6: (1 comment) > Patch Set 3: > > (4 comments) Line 101: Shouldn't this be done as part of ACPI to ensure timing requirements are met? This pin is reserved for Touchscreen I2C SDA on/off control. It will not join power on/off sequence by current design . We can set it to low for saving power . https://review.coreboot.org/c/coreboot/+/33826/3/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/gpio.c: https://review.coreboot.org/c/coreboot/+/33826/3/src/mainboard/google/hatch… PS3, Line 101: 1 > Shouldn't this be done as part of ACPI to ensure timing requirements are met? This pin is reserved for Touchscreen I2C SDA on/off control. It will not join power on/off sequence by current design . We can set it to low for saving power . -- To view, visit https://review.coreboot.org/c/coreboot/+/33826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I257a90a97e11651cdf5f85ca743e530ef5e61e56 Gerrit-Change-Number: 33826 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Jul 2019 11:10:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: drivers/intel: Move FSP stage_cache implementation into common block
by Subrata Banik (Code Review) 09 Jul '19

09 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34005 Change subject: drivers/intel: Move FSP stage_cache implementation into common block ...................................................................... drivers/intel: Move FSP stage_cache implementation into common block Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp1_1/Makefile.inc D src/drivers/intel/fsp1_1/stage_cache.c M src/drivers/intel/fsp2_0/Makefile.inc D src/drivers/intel/fsp2_0/stage_cache.c M src/soc/intel/common/block/smm/smm.c 5 files changed, 11 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34005/1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 10877b9..1372e98 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -29,7 +29,6 @@ romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c @@ -37,13 +36,11 @@ ramstage-y += fsp_util.c ramstage-y += hob.c ramstage-y += ramstage.c -ramstage-y += stage_cache.c ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c postcar-y += exit_car.S diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c deleted file mode 100644 index 2d594e6..0000000 --- a/src/drivers/intel/fsp1_1/stage_cache.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <fsp/memmap.h> -#include <stage_cache.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 9df28c0..b0a1f2b 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -23,7 +23,6 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c -romstage-$(CONFIG_EXTERNAL_STAGE_CACHE) += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += debug.c @@ -34,12 +33,10 @@ ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c ramstage-y += silicon_init.c -ramstage-$(CONFIG_EXTERNAL_STAGE_CACHE) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c -postcar-$(CONFIG_EXTERNAL_STAGE_CACHE) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c deleted file mode 100644 index a9ec154..0000000 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <fsp/memmap.h> -#include <stage_cache.h> -#include <program_loading.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { - printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; - *size = 0; - } -} diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 75b933e..38bd447 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -18,10 +18,21 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <fsp/memmap.h> #include <intelblocks/pmclib.h> #include <intelblocks/smm.h> #include <intelblocks/systemagent.h> #include <soc/pm.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} void smm_southbridge_clear_state(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/34005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Gerrit-Change-Number: 34005 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
by Subrata Banik (Code Review) 09 Jul '19

09 Jul '19

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34085 ) Change subject: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h ...................................................................... soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/include/soc/ramstage.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/icelake/sd.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/icelake/smmrelocate.c 15 files changed, 15 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Aamir Bohra: Looks good to me, approved Lean Sheng Tan: Looks good to me, but someone else must approve diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 3a46c93..ae7b344 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -27,12 +27,11 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/soc_chip.h> #include <string.h> #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> -#include "chip.h" - /* * List of supported C-states in this processor. */ diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index eff1c7a..ceef266 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -26,8 +26,7 @@ #include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> - -#include "chip.h" +#include <soc/soc_chip.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 527b989..67d41d7 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -31,8 +31,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smm.h> - -#include "chip.h" +#include <soc/soc_chip.h> static void soc_fsp_load(void) { diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 8ab909d..a4b6d80 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -29,8 +29,7 @@ #include <soc/irq.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> - -#include "chip.h" +#include <soc/soc_chip.h> /* * As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index b838c19..e035c95 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -30,11 +30,10 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/smbus.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h> #include <stdlib.h> -#include "chip.h" - #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ac7edd2..8b65a89 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -23,6 +22,7 @@ #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <soc/soc_chip.h> #include <string.h> #include <intelblocks/mp_init.h> #include <fsp/ppi/mp_service_ppi.h> diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h index d78380a..606e2ff 100644 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ b/src/soc/intel/icelake/include/soc/ramstage.h @@ -19,8 +19,7 @@ #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> - -#include "../../chip.h" +#include <soc/soc_chip.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 49af604..67f71da 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -23,11 +23,10 @@ #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> #include <soc/smm.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h> #include <stdlib.h> -#include "chip.h" - void smm_region(void **start, size_t *size) { *start = (void *)sa_get_tseg_base(); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 053d7e8..d98c83e 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -23,8 +23,7 @@ #include <intelblocks/rtc.h> #include <soc/pci_devs.h> #include <soc/pm.h> - -#include "chip.h" +#include <soc/soc_chip.h> /* * Set which power state system will be after reapplying diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 0edec4b..45f2a70 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -37,10 +37,9 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> +#include <soc/soc_chip.h> #include <security/vboot/vbnv.h> -#include "chip.h" - /* * SMI */ diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index fa6f939..420c427 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -14,12 +14,12 @@ */ #include <assert.h> -#include <chip.h> #include <console/console.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config) diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 514e5e8..65e65cc 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -27,11 +27,10 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <soc/soc_chip.h> #include <string.h> #include <timestamp.h> -#include "../chip.h" - #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c index 19c3bca..4d84bb4 100644 --- a/src/soc/intel/icelake/sd.c +++ b/src/soc/intel/icelake/sd.c @@ -14,7 +14,7 @@ */ #include <intelblocks/sd.h> -#include "chip.h" +#include <soc/soc_chip.h> int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev) { diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index a7ea094..3d41ee0 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -23,8 +23,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> - -#include "chip.h" +#include <soc/soc_chip.h> #define CSME0_FBE 0xf #define CSME0_BAR 0x0 diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 05871e4..4e2d684 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -31,8 +31,8 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/smm.h> +#include <soc/soc_chip.h> #include <soc/systemagent.h> -#include "chip.h" /* This gets filled in and used during relocation. */ static struct smm_relocation_params smm_reloc_params; -- To view, visit https://review.coreboot.org/c/coreboot/+/34085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Gerrit-Change-Number: 34085 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel: Remove HAVE_SMI_HANDLER conditional
by Kyösti Mälkki (Code Review) 09 Jul '19

09 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34155 ) Change subject: cpu/intel: Remove HAVE_SMI_HANDLER conditional ...................................................................... cpu/intel: Remove HAVE_SMI_HANDLER conditional Fix builds with HAVE_SMI_HANDLER=n. These functions are referenced across files as initialisers in const structs. While they won't get called, they are required for the linking to complete. Change-Id: I80f7ec2c5ecfe1f4bd19ee2a6dc474750d9d95ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/smm/gen1/Makefile.inc M src/soc/intel/fsp_broadwell_de/Makefile.inc 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/34155/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index a472da2..e48eef7 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -8,7 +8,7 @@ ramstage-y += acpi.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +ramstage-y += smmrelocate.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/cpu/intel/smm/gen1/Makefile.inc b/src/cpu/intel/smm/gen1/Makefile.inc index 0936710..61e9299 100644 --- a/src/cpu/intel/smm/gen1/Makefile.inc +++ b/src/cpu/intel/smm/gen1/Makefile.inc @@ -1 +1 @@ -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +ramstage-y += smmrelocate.c diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index c73c12a..1aba88b 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -28,7 +28,7 @@ ramstage-y += smi.c ramstage-y += gpio.c ramstage-y += iou_complto.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +ramstage-y += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c ramstage-y += vtd.c smm-y += pmutil.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80f7ec2c5ecfe1f4bd19ee2a6dc474750d9d95ab Gerrit-Change-Number: 34155 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019