coreboot-gerrit July 2019

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Change in coreboot[master]: soc/intel: Remove invalid smm_relocate stubs
by Kyösti Mälkki (Code Review) 10 Jul '19

10 Jul '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34150 ) Change subject: soc/intel: Remove invalid smm_relocate stubs ...................................................................... soc/intel: Remove invalid smm_relocate stubs Remove the per-platform empty stubs, builds would just fail as there is no equivalent conditional for the smmrelocate.c file. Change-Id: Ie11f307b7bc5415bfdba6a2c66aed01b70d9f0e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34150 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/soc/intel/cannonlake/include/soc/smm.h M src/soc/intel/icelake/include/soc/smm.h M src/soc/intel/skylake/include/soc/smm.h 3 files changed, 0 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h index e38c338..e1c819b 100644 --- a/src/soc/intel/cannonlake/include/soc/smm.h +++ b/src/soc/intel/cannonlake/include/soc/smm.h @@ -50,7 +50,6 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, @@ -58,14 +57,4 @@ void smm_initialize(void); void smm_relocate(void); -#else /* CONFIG_HAVE_SMI_HANDLER */ -static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) {} -static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) {} -static inline void smm_initialize(void) {} - -static inline void smm_relocate(void) {} -#endif /* CONFIG_HAVE_SMI_HANDLER */ - #endif diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h index f556b11..3c66f57 100644 --- a/src/soc/intel/icelake/include/soc/smm.h +++ b/src/soc/intel/icelake/include/soc/smm.h @@ -49,7 +49,6 @@ /* Mainboard handler for eSPI SMIs */ void mainboard_smi_espi_handler(void); -#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, @@ -57,14 +56,4 @@ void smm_initialize(void); void smm_relocate(void); -#else /* CONFIG_HAVE_SMI_HANDLER */ -static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) {} -static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) {} -static inline void smm_initialize(void) {} - -static inline void smm_relocate(void) {} -#endif /* CONFIG_HAVE_SMI_HANDLER */ - #endif diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 72992d2..7114a80 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -48,21 +48,11 @@ int smm_save_state_in_msrs; }; -#if CONFIG(HAVE_SMI_HANDLER) void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase); void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size); void smm_initialize(void); void smm_relocate(void); -#else /* CONFIG_HAVE_SMI_HANDLER */ -static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase) {} -static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, - size_t *smm_save_state_size) {} -static inline void smm_initialize(void) {} - -static inline void smm_relocate(void) {} -#endif /* CONFIG_HAVE_SMI_HANDLER */ #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie11f307b7bc5415bfdba6a2c66aed01b70d9f0e0 Gerrit-Change-Number: 34150 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/amd: Remove empty smm_lock()
by Kyösti Mälkki (Code Review) 10 Jul '19

10 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34148 ) Change subject: cpu/amd: Remove empty smm_lock() ...................................................................... cpu/amd: Remove empty smm_lock() Change-Id: I599d1d7e28f3a6439b04ef9bd38f671e1a876e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/smm/smm_init.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34148/1 diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 3efb964..60e506c 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -70,11 +70,6 @@ /* CPU MSR are set in CPU init */ } -void smm_lock(void) -{ - /* We lock SMM in CPU init */ -} - void smm_init_completion(void) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/34148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I599d1d7e28f3a6439b04ef9bd38f671e1a876e92 Gerrit-Change-Number: 34148 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/common: set disable for Level/Edge Config ...
by Maxim Polyakov (Code Review) 10 Jul '19

10 Jul '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34144 ) Change subject: src/soc/intel/common: set disable for Level/Edge Config ... ...................................................................... src/soc/intel/common: set disable for Level/Edge Config ... ... in PAD_CFG_NF_* and PAD_CFG_*_GPO macro from gpio_defs.h Change-Id: Ideadc9cb39ae34079d160c1dd7a86f2851c5f76e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/34144/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index e1ddd4b..769016b 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -177,8 +177,8 @@ /* Native function configuration */ #define PAD_CFG_NF(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S @@ -191,31 +191,33 @@ /* Native function configuration for standby state */ #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) /* Native function configuration for standby state, also configuring iostandby as masked */ #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(IGNORE)) + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(IGNORE)) /* Native function configuration for standby state, also configuring iosstate and iosterm */ #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | \ + PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | \ + PAD_CFG0_RX_DISABLE | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideadc9cb39ae34079d160c1dd7a86f2851c5f76e Gerrit-Change-Number: 34144 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Drop some HAVE_SMI_HANDLER guards
by Arthur Heymans (Code Review) 10 Jul '19

10 Jul '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34172 ) Change subject: soc/intel: Drop some HAVE_SMI_HANDLER guards ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I694cccf6779551445b83659838749dff02aedece Gerrit-Change-Number: 34172 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Jul 2019 09:08:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/oprom: Replace CONFIG() preprocessor statements
by Kyösti Mälkki (Code Review) 10 Jul '19

10 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34082 ) Change subject: device/oprom: Replace CONFIG() preprocessor statements ...................................................................... device/oprom: Replace CONFIG() preprocessor statements Change-Id: I7737b5f2a5c2598af68f2bca769232413f343a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/oprom/yabel/device.h M src/device/oprom/yabel/interrupt.c M src/device/oprom/yabel/io.c 3 files changed, 164 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34082/1 diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 8e8450a..4f28a59 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -85,7 +85,9 @@ u8 devfn; #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) struct device* dev; + u64 puid; /* unused */ #else + void *dev; u64 puid; phandle_t phandle; ihandle_t ihandle; diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index ea2a803..2bc238e 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -343,7 +343,8 @@ { // function number in AX u8 bus, devfn, offs; - struct device* dev; + struct device *dev = NULL; + switch (M.x86.R_AX) { case 0xb101: // Installation check @@ -361,30 +362,28 @@ // DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); - /* FixME: support SI != 0 */ -#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); - if (dev != 0) { - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Find Device --> 0x%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX); - M.x86.R_BH = dev->bus->secondary; - M.x86.R_BL = dev->path.pci.devfn; - M.x86.R_AH = 0x00; // return code: success - CLEAR_FLAG(F_CF); -#else + /* FixME: support SI != 0 */ + // only allow the device to find itself... if ((M.x86.R_CX == bios_device.pci_device_id) && (M.x86.R_DX == bios_device.pci_vendor_id) // device index must be 0 && (M.x86.R_SI == 0)) { - CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x00; // return code: success + dev = bios_device.dev; M.x86.R_BH = bios_device.bus; M.x86.R_BL = bios_device.devfn; -#endif - } else { + } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { + dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); + if (dev != NULL) { + M.x86.R_BH = dev->bus->secondary; + M.x86.R_BL = dev->path.pci.devfn; + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Find Device --> 0x%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX); + } + } + if (dev == NULL) { DEBUG_PRINTF_INTR ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00)\n", __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, @@ -393,7 +392,10 @@ SET_FLAG(F_CF); M.x86.R_AH = 0x86; // return code: device not found + return; } + CLEAR_FLAG(F_CF); + M.x86.R_AH = 0x00; // return code: success break; case 0xb108: //read configuration byte case 0xb109: //read configuration word @@ -403,18 +405,16 @@ offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); -#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); - if (dev == 0) { - // fail accesses to non-existent devices... -#else - dev = bios_device.dev; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... -#endif + } + + if (dev == NULL) { printf ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", __func__, bus, bios_device.bus, devfn, @@ -423,57 +423,54 @@ M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); return; - } else { - switch (M.x86.R_AX) { - case 0xb108: - M.x86.R_CL = -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_read_config8(dev, offs); -#else - (u8) rtas_pci_config_read(bios_device. - puid, 1, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CL); - break; - case 0xb109: - M.x86.R_CX = -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_read_config16(dev, offs); -#else - (u16) rtas_pci_config_read(bios_device. - puid, 2, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CX); - break; - case 0xb10a: - M.x86.R_ECX = -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_read_config32(dev, offs); -#else - (u32) rtas_pci_config_read(bios_device. - puid, 4, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_ECX); - break; - } - CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x0; // return code: success } + + switch (M.x86.R_AX) { + case 0xb108: + M.x86.R_CL = +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_read_config8(dev, offs); +#else + (u8) rtas_pci_config_read(bios_device.puid, 1, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CL); + break; + case 0xb109: + M.x86.R_CX = +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_read_config16(dev, offs); +#else + (u16) rtas_pci_config_read(bios_device.puid, 2, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CX); + break; + case 0xb10a: + M.x86.R_ECX = +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_read_config32(dev, offs); +#else + (u32) rtas_pci_config_read(bios_device.puid, 4, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_ECX); + break; + } + CLEAR_FLAG(F_CF); + M.x86.R_AH = 0x0; // return code: success break; case 0xb10b: //write configuration byte case 0xb10c: //write configuration word @@ -481,9 +478,12 @@ bus = M.x86.R_BH; devfn = M.x86.R_BL; offs = M.x86.R_DI; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } + + if (dev == NULL) { printf ("%s(): Config read access invalid! bus: %x (%x), devfn: %x (%x), offs: %x\n", __func__, bus, bios_device.bus, devfn, @@ -492,48 +492,48 @@ M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); return; - } else { - switch (M.x86.R_AX) { - case 0xb10b: -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_write_config8(bios_device.dev, offs, M.x86.R_CL); -#else - rtas_pci_config_write(bios_device.puid, 1, bus, - devfn, offs, M.x86.R_CL); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CL); - break; - case 0xb10c: -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_write_config16(bios_device.dev, offs, M.x86.R_CX); -#else - rtas_pci_config_write(bios_device.puid, 2, bus, - devfn, offs, M.x86.R_CX); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CX); - break; - case 0xb10d: -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); -#else - rtas_pci_config_write(bios_device.puid, 4, bus, - devfn, offs, M.x86.R_ECX); -#endif - DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_ECX); - break; - } - CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x0; // return code: success } + + switch (M.x86.R_AX) { + case 0xb10b: +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_write_config8(dev, offs, M.x86.R_CL); +#else + rtas_pci_config_write(bios_device.puid, 1, bus, + devfn, offs, M.x86.R_CL); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CL); + break; + case 0xb10c: +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_write_config16(dev, offs, M.x86.R_CX); +#else + rtas_pci_config_write(bios_device.puid, 2, bus, + devfn, offs, M.x86.R_CX); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CX); + break; + case 0xb10d: +#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + pci_write_config32(dev, offs, M.x86.R_ECX); +#else + rtas_pci_config_write(bios_device.puid, 4, bus, + devfn, offs, M.x86.R_ECX); +#endif + DEBUG_PRINTF_INTR + ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_ECX); + break; + } + CLEAR_FLAG(F_CF); + M.x86.R_AH = 0x0; // return code: success break; default: printf("%s(): unknown function (%x) for int1a handler.\n", diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 69cbe19..96c9224 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -431,18 +431,16 @@ offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, bus, devfn, offs); -#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", - __func__, dev_path(dev)); - if (dev == 0) { - // fail accesses to non-existent devices... -#else - dev = bios_device.dev; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... -#endif + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } else if (CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)) { + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", + __func__, dev_path(dev)); + } + + if (dev == NULL) { printf ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", __func__, bus, bios_device.bus, devfn, @@ -450,8 +448,9 @@ SET_FLAG(F_CF); HALT_SYS(); return 0; - } else { -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + } + + if (CONFIG(PCI_OPTION_ROM_RUN_YABEL)) { switch (size) { case 1: rval = pci_read_config8(dev, offs); @@ -463,23 +462,23 @@ rval = pci_read_config32(dev, offs); break; } -#else - rval = - (u32) rtas_pci_config_read(bios_device. - puid, size, + } else { + rval =(u32) rtas_pci_config_read(bios_device.puid, size, bus, devfn, offs); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", - __func__, addr, offs, size, rval); } + + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", + __func__, addr, offs, size, rval); + return rval; } void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) { + struct device *dev = NULL; u32 port_cf8_val = 0; u8 bus, devfn, offs; @@ -498,37 +497,41 @@ devfn = (port_cf8_val & 0x0000FF00) >> 8; offs = (port_cf8_val & 0x000000FF); offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... + + if ((bus == bios_device.bus) && (devfn == bios_device.devfn)) { + dev = bios_device.dev; + } else { printf ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", bus, devfn >> 3, devfn & 7, offs); -#if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) + + if (CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG)) + return; + // fail accesses to any device but ours... HALT_SYS(); -#endif - } else { -#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) + } + + if (CONFIG(PCI_OPTION_ROM_RUN_YABEL)) { switch (size) { case 1: - pci_write_config8(bios_device.dev, offs, val); + pci_write_config8(dev, offs, val); break; case 2: - pci_write_config16(bios_device.dev, offs, val); + pci_write_config16(dev, offs, val); break; case 4: - pci_write_config32(bios_device.dev, offs, val); + pci_write_config32(dev, offs, val); break; } -#else + } else { rtas_pci_config_write(bios_device.puid, size, bus, devfn, offs, val); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", - __func__, addr, offs, size, val); } + + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", + __func__, addr, offs, size, val); } u8 -- To view, visit https://review.coreboot.org/c/coreboot/+/34082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7737b5f2a5c2598af68f2bca769232413f343a39 Gerrit-Change-Number: 34082 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: device/oprom: Reduce indentation
by Kyösti Mälkki (Code Review) 10 Jul '19

10 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34081 ) Change subject: device/oprom: Reduce indentation ...................................................................... device/oprom: Reduce indentation Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/oprom/yabel/io.c 1 file changed, 101 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/34081/1 diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 7117a6e..69cbe19 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -410,66 +410,69 @@ u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size) { + u32 port_cf8_val = 0; u32 rval = 0xFFFFFFFF; - struct device * dev; - if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { - // PCI Configuration Mechanism 1 step 1 - // write to 0xCF8, sets bus, device, function and Config Space offset - // later read from 0xCFC-0xCFF returns the value... - u8 bus, devfn, offs; - u32 port_cf8_val = my_inl(0xCF8); - if ((port_cf8_val & 0x80000000) != 0) { - //highest bit enables config space mapping - bus = (port_cf8_val & 0x00FF0000) >> 16; - devfn = (port_cf8_val & 0x0000FF00) >> 8; - offs = (port_cf8_val & 0x000000FF); - offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly - DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", - __func__, bus, devfn, offs); + struct device *dev = NULL; + u8 bus, devfn, offs; + + // PCI Configuration Mechanism 1 step 1 + // write to 0xCF8, sets bus, device, function and Config Space offset + // later read from 0xCFC-0xCFF returns the value... + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) + port_cf8_val = my_inl(0xCF8); + + if ((port_cf8_val & 0x80000000) == 0) + return rval; + + //highest bit enables config space mapping + bus = (port_cf8_val & 0x00FF0000) >> 16; + devfn = (port_cf8_val & 0x0000FF00) >> 8; + offs = (port_cf8_val & 0x000000FF); + offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly + DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", + __func__, bus, devfn, offs); #if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) - dev = dev_find_slot(bus, devfn); - DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", - __func__, dev_path(dev)); - if (dev == 0) { - // fail accesses to non-existent devices... + dev = dev_find_slot(bus, devfn); + DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", + __func__, dev_path(dev)); + if (dev == 0) { + // fail accesses to non-existent devices... #else - dev = bios_device.dev; - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... + dev = bios_device.dev; + if ((bus != bios_device.bus) + || (devfn != bios_device.devfn)) { + // fail accesses to any device but ours... #endif - printf - ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", - __func__, bus, bios_device.bus, devfn, - bios_device.devfn, offs); - SET_FLAG(F_CF); - HALT_SYS(); - return 0; - } else { + printf + ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", + __func__, bus, bios_device.bus, devfn, + bios_device.devfn, offs); + SET_FLAG(F_CF); + HALT_SYS(); + return 0; + } else { #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - switch (size) { - case 1: - rval = pci_read_config8(dev, offs); - break; - case 2: - rval = pci_read_config16(dev, offs); - break; - case 4: - rval = pci_read_config32(dev, offs); - break; - } -#else - rval = - (u32) rtas_pci_config_read(bios_device. - puid, size, - bus, devfn, - offs); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", - __func__, addr, offs, size, rval); - } + switch (size) { + case 1: + rval = pci_read_config8(dev, offs); + break; + case 2: + rval = pci_read_config16(dev, offs); + break; + case 4: + rval = pci_read_config32(dev, offs); + break; } +#else + rval = + (u32) rtas_pci_config_read(bios_device. + puid, size, + bus, devfn, + offs); +#endif + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", + __func__, addr, offs, size, rval); } return rval; } @@ -477,50 +480,54 @@ void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) { - if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { - // PCI Configuration Mechanism 1 step 1 - // write to 0xCF8, sets bus, device, function and Config Space offset - // later write to 0xCFC-0xCFF sets the value... - u8 bus, devfn, offs; - u32 port_cf8_val = my_inl(0xCF8); - if ((port_cf8_val & 0x80000000) != 0) { - //highest bit enables config space mapping - bus = (port_cf8_val & 0x00FF0000) >> 16; - devfn = (port_cf8_val & 0x0000FF00) >> 8; - offs = (port_cf8_val & 0x000000FF); - offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly - if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { - // fail accesses to any device but ours... - printf - ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", - bus, devfn >> 3, devfn & 7, offs); + u32 port_cf8_val = 0; + u8 bus, devfn, offs; + + // PCI Configuration Mechanism 1 step 1 + // write to 0xCF8, sets bus, device, function and Config Space offset + // later write to 0xCFC-0xCFF sets the value... + + if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) + port_cf8_val = my_inl(0xCF8); + + if ((port_cf8_val & 0x80000000) == 0) + return; + + //highest bit enables config space mapping + bus = (port_cf8_val & 0x00FF0000) >> 16; + devfn = (port_cf8_val & 0x0000FF00) >> 8; + offs = (port_cf8_val & 0x000000FF); + offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly + if ((bus != bios_device.bus) + || (devfn != bios_device.devfn)) { + // fail accesses to any device but ours... + printf + ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", + bus, devfn >> 3, devfn & 7, offs); #if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) - HALT_SYS(); + HALT_SYS(); #endif - } else { + } else { #if CONFIG(PCI_OPTION_ROM_RUN_YABEL) - switch (size) { - case 1: - pci_write_config8(bios_device.dev, offs, val); - break; - case 2: - pci_write_config16(bios_device.dev, offs, val); - break; - case 4: - pci_write_config32(bios_device.dev, offs, val); - break; - } -#else - rtas_pci_config_write(bios_device.puid, - size, bus, devfn, offs, - val); -#endif - DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", - __func__, addr, offs, size, val); - } + switch (size) { + case 1: + pci_write_config8(bios_device.dev, offs, val); + break; + case 2: + pci_write_config16(bios_device.dev, offs, val); + break; + case 4: + pci_write_config32(bios_device.dev, offs, val); + break; } +#else + rtas_pci_config_write(bios_device.puid, + size, bus, devfn, offs, + val); +#endif + DEBUG_PRINTF_IO + ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", + __func__, addr, offs, size, val); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/34081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c Gerrit-Change-Number: 34081 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Furquan Shaikh (Code Review) 10 Jul '19

10 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jul 2019 07:08:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 10 Jul '19

10 Jul '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 9: > Patch Set 8: > > (1 comment) ok,it's done -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jul 2019 06:27:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Frank Chu (Code Review) 10 Jul '19

10 Jul '19

Hello Paul Fagerburg, Philip Chen, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33954 to look at the new patch set (#9). Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... mb/google/hatch/variants: Fix nonworking touch pad Correct ELAN Touch pad IRQ GPIO to GPP_A21 BUG=b:135507215 BRANCH=none TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/33954/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/variants: Fix nonworking touch pad
by Furquan Shaikh (Code Review) 10 Jul '19

10 Jul '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33954 ) Change subject: mb/google/hatch/variants: Fix nonworking touch pad ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/33954/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33954/8//COMMIT_MSG@9 PS8, Line 9: Modify GPP_A21 to interrupt and disable all GPIO PM config. This is not accurate anymore. Can you please update this? -- To view, visit https://review.coreboot.org/c/coreboot/+/33954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Gerrit-Change-Number: 33954 Gerrit-PatchSet: 8 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Jul 2019 06:10:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2019