coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

1 participants
1542 discussions

Change in ...coreboot[master]: qclib: Add qclib support
by Julius Werner (Code Review) 07 Mar '19

07 Mar '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 14: Code-Review-1 The QcLib stuff needs to be deduplicated with SDM845, please do not submit this as is. This is a very outdated version of the QcLib interface, we have made a lot of progress on CB:25208 since with full support for the interface table that's supposed to be used there. -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 14 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Mar 2019 21:23:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Mistral: QCS405: Added RPM support
by Julius Werner (Code Review) 07 Mar '19

07 Mar '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29970 ) Change subject: Mistral: QCS405: Added RPM support ...................................................................... Patch Set 14: Code-Review-1 (2 comments) https://review.coreboot.org/#/c/29970/14/src/soc/qualcomm/qcs405/Makefile.i… File src/soc/qualcomm/qcs405/Makefile.inc: https://review.coreboot.org/#/c/29970/14/src/soc/qualcomm/qcs405/Makefile.i… PS14, Line 61: ifneq (,$(findstring $(RPM_FILE),$(rpm_file))) This is a hack, I don't not think we should submit any code like this. These blobs should be submitted to the 3rdparty/blobs repository, and once they're there you don't need this code that checks for existence and builds a non-working image without them only to trick Jenkins. There are still many license issues to be solved for these projects, and they'll not just go away if we submit code that looks like it builds but doesn't actually work without them. I think you should keep these patches floating until they're actually resolved. If you want to speed this up, you can ask Mike Stefanick to start responding to my mails again (I haven't heard anything from Qualcomm for a month about this and that's not helpful if we want to make progress). https://review.coreboot.org/#/c/29970/14/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/memlayout.ld: https://review.coreboot.org/#/c/29970/14/src/soc/qualcomm/qcs405/include/so… PS14, Line 34: REGION(rpm, 0x00200000, 0xA4000, 0x0) nit: Do you really need two regions here? They're both covering the same space. If you just want one region, get rid of the RPMSRAM_START/_END. Those are only needed if you want to nest multiple subregions into an SRAM region. -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 14 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 06 Mar 2019 21:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/skylake: Add H110 PCH series
by Maxim Polyakov (Code Review) 07 Mar '19

07 Mar '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31602 Change subject: soc/intel/skylake: Add H110 PCH series ...................................................................... soc/intel/skylake: Add H110 PCH series This patch adds support H110 chipset (Sunrise Point) for Skylake and Kabylake processor families. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/31602/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ba740fc..b2e7b62 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2690,6 +2690,7 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e +#define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 #define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d #define PCI_DEVICE_ID_INTEL_SPT_H_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_SPT_H_QM175 0xa153 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index ad004ef..f78d194 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -126,6 +126,7 @@ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, + PCI_DEVICE_ID_INTEL_SPT_H_H110, PCI_DEVICE_ID_INTEL_SPT_H_QM170, PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index ae74489..0da1dbc 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -70,6 +70,7 @@ { PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" }, { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" }, + { PCI_DEVICE_ID_INTEL_SPT_H_H110, "Skylake PCH-H H110" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d Gerrit-Change-Number: 31602 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: soc/intel/skylake: Add a new desktop i5 CPU
by Maxim Polyakov (Code Review) 07 Mar '19

07 Mar '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31601 Change subject: soc/intel/skylake: Add a new desktop i5 CPU ...................................................................... soc/intel/skylake: Add a new desktop i5 CPU This patch adds support HB: Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host Bridge/DRAM Registers - 191F IGD: HD Graphics 530 Skylake GT2 - Intel integrated graphics processor https://en.wikichip.org/wiki/intel/hd_graphics/530 This is required to run the Coreboot on the Intel Core i5-6600 (Skylake) decktop processor. It has been tested on ASRock H110M-DVS motherboard. Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 4 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31601/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 81654bc..ba740fc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2956,6 +2956,7 @@ /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 +#define PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1 0x1912 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM 0x191E #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM 0x1916 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM 0x191B @@ -3029,6 +3030,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 +#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index da2b25f..124d367 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -128,6 +128,7 @@ PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2, PCI_DEVICE_ID_INTEL_AML_GT2_ULX, PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, + PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1, PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 69c1232..0d21250 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -310,6 +310,7 @@ PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, + PCI_DEVICE_ID_INTEL_SKL_ID_DT, PCI_DEVICE_ID_INTEL_KBL_ID_U, PCI_DEVICE_ID_INTEL_KBL_ID_Y, PCI_DEVICE_ID_INTEL_KBL_ID_H, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index c245523..ae74489 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -52,6 +52,7 @@ { PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_DT, "Skylake-DT" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" }, @@ -95,6 +96,7 @@ const char *name; } igd_table[] = { { PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM, "Skylake ULT GT1"}, + { PCI_DEVICE_ID_INTEL_SKL_GT2_DT2P1, "Skylake DT GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM, "Skylake ULX GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM, "Skylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, "Skylake HALO GT2" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/31601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d Gerrit-Change-Number: 31601 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: soc/intel/braswell/include/soc/spi.h: Add OPTYPE values
by Frans Hendriks (Code Review) 07 Mar '19

07 Mar '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31712 Change subject: soc/intel/braswell/include/soc/spi.h: Add OPTYPE values ...................................................................... soc/intel/braswell/include/soc/spi.h: Add OPTYPE values Add SPI_OPTYPE_XXX values for the SPI controller. BUG=N/A TEST=flashrom on Facebook FBG-1701 Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/spi.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31712/1 diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 49f3fcc..2d27545 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,10 @@ # define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 +# define SPI_OPTYPE_RD_NOADDR 0x00 /* Read, no address */ +# define SPI_OPTYPE_WR_NOADDR 0x01 /* Write, no address */ +# define SPI_OPTYPE_RD_ADDR 0x02 /* Read, address required */ +# define SPI_OPTYPE_WR_ADDR 0x03 /* Write, address required */ #define OPMENU0 0x98 #define OPMENU1 0x9c #define LVSCC 0xc4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a Gerrit-Change-Number: 31712 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: MAINTAINERS: Update Braswell SoC maintainers
by Michał Żygowski (Code Review) 07 Mar '19

07 Mar '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31673 Change subject: MAINTAINERS: Update Braswell SoC maintainers ...................................................................... MAINTAINERS: Update Braswell SoC maintainers Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id815db60e3718bf141abcc7923ea073bbab4a516 --- M MAINTAINERS 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31673/1 diff --git a/MAINTAINERS b/MAINTAINERS index fbaad69..103c325 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -307,7 +307,10 @@ INTEL BRASWELL SOC M: Hannah Williams <hannah.williams(a)intel.com> -S: Supported +M: Piotr Król <piotr.krol(a)3mdeb.com> +M: Michał Żygowski <michal.zygowski(a)3mdeb.com> +M: Frans Hendriks <fhendriks(a)eltan.com> +S: Maintained F: /src/soc/intel/braswell F: /src/vendorcode/intel/fsp/fsp1_1/braswell -- To view, visit https://review.coreboot.org/c/coreboot/+/31673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id815db60e3718bf141abcc7923ea073bbab4a516 Gerrit-Change-Number: 31673 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

10 17

Change in ...coreboot[master]: soc/intel/braswell/include/soc/pci_devs.h: Add PUINIT_DEV
by Frans Hendriks (Code Review) 07 Mar '19

07 Mar '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31711 Change subject: soc/intel/braswell/include/soc/pci_devs.h: Add PUINIT_DEV ...................................................................... soc/intel/braswell/include/soc/pci_devs.h: Add PUINIT_DEV Intel Braswell P-UNIT is missing in pci_devs.h Add PUNIT device, function and device ID BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I80c87c8964b3ba830571e0c03c424b67729a0c1a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/pci_devs.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31711/1 diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index c26eefb..8b06aff 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +30,11 @@ #define GFX_FUNC 0 # define GFX_DEVID 0x22b1 +/* P-Unit DPTF */ +#define PUNIT_DEV 0xB +#define PUNIT_FUNC 0 +#define PUNIT_DEVID 0x22DC + /* MMC Port */ #define MMC_DEV 0x10 #define MMC_FUNC 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/31711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c87c8964b3ba830571e0c03c424b67729a0c1a Gerrit-Change-Number: 31711 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src: Drop unused include <arch/acpi.h>
by HAOUAS Elyes (Code Review) 07 Mar '19

07 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31715 Change subject: src: Drop unused include <arch/acpi.h> ...................................................................... src: Drop unused include <arch/acpi.h> Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/romstage.c M src/cpu/x86/mtrr/mtrr.c M src/mainboard/amd/bettong/mainboard.c M src/mainboard/amd/db-ft3b-lc/mainboard.c M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/intel/kblrvp/smihandler.c 25 files changed, 3 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31715/1 diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index d364513..5455b0c 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <arch/acpi.h> static void model_15_init(struct device *dev) { diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 818cfa4..d156525 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <arch/acpi.h> #include <amdlib.h> #include <PspBaseLib.h> diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 9be6e2a..7ae89b4 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -25,7 +25,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <arch/acpi.h> static void model_16_init(struct device *dev) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index e2dd0fa..d5028c2 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -24,7 +24,6 @@ #include <halt.h> #include <lib.h> #include <timestamp.h> -#include <arch/acpi.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbmem.h> diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 249d631..b45d17f 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -33,7 +33,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <memrange.h> #include <cpu/amd/mtrr.h> #include <assert.h> diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index 16fc47e..80b888e 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> -#include <arch/acpi.h> #include <agesawrapper.h> #include <southbridge/amd/common/amd_pci_util.h> diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c index d5ae995..6ea80ed 100644 --- a/src/mainboard/amd/db-ft3b-lc/mainboard.c +++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 86dfed4..b3f2285 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> -#include <arch/acpi.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/amd_pci_util.h> #include <soc/southbridge.h> diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 08d21c8..3d33850 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <northbridge/amd/pi/00630F01/pci_devs.h> diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 45841f9..00ac1a4 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index ed22ed1..54ced88 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/acpi.h> #include <arch/io.h> #include <device/pci_ops.h> #include <commonlib/loglevel.h> diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 83fc9a0..c100a61 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> -#include <arch/acpi.h> #include <arch/io.h> #include <device/pci_ops.h> #include <commonlib/loglevel.h> diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 028af4c..4546190 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> +#include <arch/acpi.h> #include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 5c4dbe8..cf0d33b 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> +#include <arch/acpi.h> #include <arch/io.h> #include <device/pci_ops.h> #include <arch/cpu.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 6493809..35882b2 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <console/console.h> diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 45841f9..00ac1a4 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 813b1d6..3b84905 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index dcfd27f..ec73399 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -20,7 +20,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 4f445ab..b3ee2a8 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> #include <console/console.h> diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 00f5f5d..9424855 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -22,7 +22,6 @@ #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/acpi.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index e3deddd..7c906ce 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -24,7 +24,6 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/romstage.h> -#include <soc/acpi.h> #include <soc/baytrail.h> #include <drivers/intel/fsp1_0/fsp_util.h> diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index e73da8d..946a453 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -22,7 +22,6 @@ #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/acpi.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 233800a..1a46f8b 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <arch/acpi.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 4074a30..d5ba961 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <superio/smsc/sio1007/chip.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index a12a460..bb09d78 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <elog.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/31715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a Gerrit-Change-Number: 31715 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mb/google/poppy/variants/nami: Use Pantheon VBT
by John Su (Code Review) 07 Mar '19

07 Mar '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31747 Change subject: mb/google/poppy/variants/nami: Use Pantheon VBT ...................................................................... mb/google/poppy/variants/nami: Use Pantheon VBT Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31747/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 8592cae..e279693 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -195,6 +195,8 @@ case SKU_0_PANTHEON: case SKU_1_PANTHEON: case SKU_2_PANTHEON: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: return "vbt-pantheon.bin"; case SKU_0_VAYNE: case SKU_1_VAYNE: -- To view, visit https://review.coreboot.org/c/coreboot/+/31747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Gerrit-Change-Number: 31747 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: arch/x86: Prepare GDT for x86_64
by Patrick Georgi (Code Review) 07 Mar '19

07 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31769 ) Change subject: arch/x86: Prepare GDT for x86_64 ...................................................................... arch/x86: Prepare GDT for x86_64 Make GDT a separate table and don't reuse GDT descriptor as unused first field of GDT. Required for separate x86_64 GDT descriptor, pointing to the same GDT. Tested on qemu. Change-Id: I513329b67d49ade1055bc07cf7b93ff2e0131e0b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31769 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/gdt_init.S 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Kyösti Mälkki: Looks good to me, but someone else must approve diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index 6aa2a79..f66cd43 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -21,11 +21,15 @@ .previous .align 4 .globl gdtptr -gdt: gdtptr: .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ - .word 0 + + .align 4 +gdt: + /* selgdt 0, unused */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x00, 0x00, 0x00 /* selgdt 0x08, flat code segment */ .word 0xffff, 0x0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/31769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I513329b67d49ade1055bc07cf7b93ff2e0131e0b Gerrit-Change-Number: 31769 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2019