Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384
Change subject: README: Spell Web site with one space
......................................................................
README: Spell Web site with one space
Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M payloads/libpayload/README
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1
diff --git a/payloads/libpayload/README b/payloads/libpayload/README
index fdf9b18..7348934 100644
--- a/payloads/libpayload/README
+++ b/payloads/libpayload/README
@@ -49,10 +49,10 @@
Please see the sample/ directory for details.
-Website and Mailing List
+Web site and Mailing List
------------------------
-The main website is https://www.coreboot.org/Libpayload.
+The main web site is https://www.coreboot.org/Libpayload.
For additional information, patches, and discussions, please join the
coreboot mailing list at https://www.coreboot.org/Mailinglist, where most
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Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6
Gerrit-Change-Number: 31384
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821
Change subject: util/chromeos: Add unzip as a dependency
......................................................................
util/chromeos: Add unzip as a dependency
unzip might not be installed by default, so it is added as a
dependency in crosfirmware script.
Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc
Signed-off-by: Mete Balci <metebalci(a)gmail.com>
---
M util/chromeos/crosfirmware.sh
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1
diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh
index 9d2ca84..0564106 100755
--- a/util/chromeos/crosfirmware.sh
+++ b/util/chromeos/crosfirmware.sh
@@ -37,6 +37,7 @@
exit_if_uninstalled "debugfs" "e2fsprogs"
exit_if_uninstalled "parted" "parted"
exit_if_uninstalled "curl" "curl"
+ exit_if_uninstalled "unzip" "unzip"
}
get_inventory()
--
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Gerrit-Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc
Gerrit-Change-Number: 31821
Gerrit-PatchSet: 1
Gerrit-Owner: Mete Balci <metebalci(a)gmail.com>
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Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806
Change subject: x86/acpi_s3: Remove trailing dots from debug message
......................................................................
x86/acpi_s3: Remove trailing dots from debug message
The dot is not needed, as it is no sentence and followed by a line
break.
Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/arch/x86/acpi_s3.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index ad9fe00..07c0332 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -34,10 +34,10 @@
{
if (acpi_slp_type < 0) {
if (romstage_handoff_is_resume()) {
- printk(BIOS_DEBUG, "S3 Resume.\n");
+ printk(BIOS_DEBUG, "S3 Resume\n");
acpi_slp_type = ACPI_S3;
} else {
- printk(BIOS_DEBUG, "Normal boot.\n");
+ printk(BIOS_DEBUG, "Normal boot\n");
acpi_slp_type = ACPI_S0;
}
}
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Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470
Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
......................................................................
mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01
(Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3).
This is true for most of the Thinkpads, however on the X1 Carbon Gen1
(and possibly others), the battery hotkey is not present and the lock
one is instead on Fn-F3.
Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so
that the lock hotkey is on F3 and the battery one is on F2 (even if it's
not marked so).
Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola(a)corna.info>
---
M src/ec/lenovo/h8/acpi/ec.asl
M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 327a2cf..6ffba5e 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -197,12 +197,20 @@
Method (_Q11, 0, NotSerialized)
{
+#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3)
+ ^HKEY.RHK (0x03)
+#else
^HKEY.RHK (0x02)
+#endif
}
Method (_Q12, 0, NotSerialized)
{
+#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3)
+ ^HKEY.RHK (0x02)
+#else
^HKEY.RHK (0x03)
+#endif
}
Method (_Q64, 0, NotSerialized)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
index 8c9bd5a..2696607 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
+++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
@@ -20,6 +20,7 @@
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
+#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1
#include <arch/acpi.h>
DefinitionBlock(
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Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
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Gerrit-Owner: Nicola Corna <nicola(a)corna.info>
Gerrit-MessageType: newchange
Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31450
to review the following change.
Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
......................................................................
lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S
which is currently not used by any of coreboot-supported boards. Also
enable the discrete graphics PCI bus leading to HD 8570M (1002,6663)
or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround
for PCI resource allocation problems to AMD AGESA vendorcode.
Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu>
Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88
---
M src/device/Kconfig
M src/mainboard/lenovo/g505s/devicetree.cb
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
3 files changed, 17 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 33c1e5b3..5d2087e 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -247,8 +247,15 @@
Enable this option for a good compromise between security and speed.
config MULTIPLE_VGA_ADAPTERS
+ prompt "Multiple VGA Adapters"
bool
+ depends on BOARD_LENOVO_G505S
default n
+ help
+ Some motherboards may have more than one VGA adapter - for example,
+ there are versions of Lenovo G505S that have a discrete VGA adapter
+ in addition to its' integrated VGA adapter which is a part of APU.
+ Enable this option to try to initialize this discrete VGA adapter.
menu "Display"
depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
index 99f42d6..1f33c27 100644
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -27,7 +27,7 @@
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 off end
+ device pci 2.0 on end # Discrete Graphics PCI bus 0x666X
device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
index c566061..ee6d2c2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -437,8 +437,15 @@
RefPtr = MemPtr->ParameterListPtr;
// Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
+ if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) &&
+ (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) {
+ // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems
+ RefPtr->BottomIo = 0xD0;
+ }
+ else {
+ // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+ RefPtr->BottomIo = 0xE0;
+ }
RefPtr->UmaMode = UserOptions.CfgUmaMode;
RefPtr->UmaSize = UserOptions.CfgUmaSize;
RefPtr->MemHoleRemapping = TRUE;
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