coreboot-gerrit December 2019

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Change in coreboot[master]: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK
by Mike Banon (Code Review) 26 Dec '19

26 Dec '19

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37829 ) Change subject: asus/am1i-a: Switch away from ROMCC_BOOTBLOCK ...................................................................... asus/am1i-a: Switch away from ROMCC_BOOTBLOCK Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c', following the example of change CB:37719 (fc749b2). TEST=Boots into Artix Linux 2019 without a problem. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb --- M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/Kconfig.name M src/mainboard/asus/am1i-a/Makefile.inc R src/mainboard/asus/am1i-a/bootblock.c 4 files changed, 13 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37829/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 8ccb174..947c2c5 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -1,12 +1,8 @@ -config BOARD_ASUS_AM1I_A - def_bool n - if BOARD_ASUS_AM1I_A config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name index 57c6227..55b4a3c 100644 --- a/src/mainboard/asus/am1i-a/Kconfig.name +++ b/src/mainboard/asus/am1i-a/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_ASUS_AM1I_A -# bool"AM1I-A" +config BOARD_ASUS_AM1I_A + bool"AM1I-A" diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/asus/am1i-a/Makefile.inc +++ b/src/mainboard/asus/am1i-a/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/bootblock.c similarity index 83% rename from src/mainboard/asus/am1i-a/romstage.c rename to src/mainboard/asus/am1i-a/bootblock.c index de85325..07e3945 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -1,10 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov <getinaks(a)gmail.com> - * Copyright (C) 2018 Gergely Kiss <mail.gery(a)gmail.com> - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,12 +11,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> #include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/agesa/hudson/hudson.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8623e/it8623e.h> @@ -118,33 +111,22 @@ ite_reg_write(dev, 0xfb, 0x00); } -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - int i; - u32 val; - u8 byte; - pci_devfn_t dev; - u32 *addr32; + volatile u32 i, val, *addr32; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + pm_write8(0xd2, 0x0); /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xEA, 0xcd6); - outb(0x1, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); + pm_write8(0xea, 0x1); /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + pm_write8(0x24, 0x1); /* Configure ClkDrvStr1 settings */ addr32 = (u32 *)0xfed80e24; @@ -154,15 +136,11 @@ addr32 = (u32 *)0xfed80e40; *addr32 = 0x000c4050; - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f & 4e, 4f */ - pci_write_config8(dev, 0x48, byte); - + /* Configure SIO as made under vendor BIOS */ ite_gpio_conf(GPIO_DEV); ite_evc_conf(ENVC_DEV); + /* Enable serial output on it8623e */ ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV); -- To view, visit https://review.coreboot.org/c/coreboot/+/37829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb Gerrit-Change-Number: 37829 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: src/*.asl: Add FIXME comment
by HAOUAS Elyes (Code Review) 26 Dec '19

26 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37815 ) Change subject: src/*.asl: Add FIXME comment ...................................................................... src/*.asl: Add FIXME comment A device object must contain either a _HID object or an _ADR object, but should not contain both. Change-Id: I12acd54679c2c712d5f2a9dce5fb28f4c966eb2b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/aopen/dxplplusu/acpi/p64h2.asl M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/mainboard/intel/strago/acpi/mainboard.asl M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl 12 files changed, 134 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37815/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl index e3f2e5f..2629c3a 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -18,6 +18,11 @@ /* I/O APIC id 0x3 */ Device(PBIO) { + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ + Name (_HID, "ACPI000A") Name (_ADR, 0x001c0000) } @@ -59,6 +64,10 @@ /* I/O APIC id 0x4 */ Device(PAIO) { + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "ACPI000A") Name (_ADR, 0x001e0000) } diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 01942dc..b690d5d 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -18,6 +18,10 @@ /* Grunt specific I2S machine driver */ Device (I2S) { + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_ADR, 1) Name (_HID, "AMD7219") Name (_CID, "AMD7219") diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index 1d5437b..0318d73 100644 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -114,6 +114,11 @@ /* Realtek Audio Codec */ Device (RTEK) /* Audio Codec driver I2C */ { + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_ADR, 0) Name (_HID, AUDIO_CODEC_HID) Name (_CID, AUDIO_CODEC_CID) diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 06199a1..17c569a 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -16,6 +16,12 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 9a1fa9e..bbd8609 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -16,6 +16,11 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index f74b31a..9ad0c90 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -16,6 +16,11 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index c2b3aac..ab3f16c 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -16,6 +16,11 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985..fb0e6d1 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -16,6 +16,11 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index f74b31a..9ad0c90 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -16,6 +16,11 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index fe78534..f8d08a6 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -17,6 +17,11 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) + +/* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 1b44e95..b3dc3e0 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -157,6 +157,11 @@ Device (SDMA) { // Serial IO DMA Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -194,6 +199,11 @@ Device (I2C0) { // Serial IO I2C0 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { @@ -265,6 +275,11 @@ Device (I2C1) { // Serial IO I2C1 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { @@ -336,6 +351,11 @@ Device (SPI0) { // Serial IO SPI0 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { @@ -392,6 +412,11 @@ Device (SPI1) { // Serial IO SPI1 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { @@ -460,6 +485,11 @@ Device (UAR0) { // Serial IO UART0 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { @@ -528,6 +558,11 @@ Device (UAR1) { // Serial IO UART1 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { @@ -584,6 +619,11 @@ Device (SDIO) { // Serial IO SDIO Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Method (_HID) { If (\ISWP ()) { diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91..f81ec0b 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -123,6 +123,11 @@ Device (SDMA) { // Serial IO DMA Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INTL9C60") Name (_UID, 1) Name (_ADR, 0x00150000) @@ -160,6 +165,11 @@ Device (I2C0) { // Serial IO I2C0 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) @@ -242,6 +252,11 @@ Device (I2C1) { // Serial IO I2C1 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) @@ -324,6 +339,11 @@ Device (SPI0) { // Serial IO SPI0 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) @@ -362,6 +382,11 @@ Device (SPI1) { // Serial IO SPI1 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) @@ -413,6 +438,11 @@ Device (UAR0) { // Serial IO UART0 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) @@ -464,6 +494,11 @@ Device (UAR1) { // Serial IO UART1 Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) @@ -502,6 +537,11 @@ Device (SDIO) { // Serial IO SDIO Controller + + /* + * FIXME: Per ACPI spec, device object must contain either an + * _HID object or an _ADR object, but should not contain both. + */ Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/37815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12acd54679c2c712d5f2a9dce5fb28f4c966eb2b Gerrit-Change-Number: 37815 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [Please Fix] Drop boards with broken acpi code
by HAOUAS Elyes (Code Review) 26 Dec '19

26 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37826 ) Change subject: [Please Fix] Drop boards with broken acpi code ...................................................................... [Please Fix] Drop boards with broken acpi code Change-Id: I1696945622ec0fe955084f89d9dc37bd6f8815f0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/aopen/Kconfig D src/mainboard/aopen/Kconfig.name D src/mainboard/aopen/dxplplusu/Kconfig D src/mainboard/aopen/dxplplusu/Kconfig.name D src/mainboard/aopen/dxplplusu/Makefile.inc D src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl D src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl D src/mainboard/aopen/dxplplusu/acpi/i82801db.asl D src/mainboard/aopen/dxplplusu/acpi/p64h2.asl D src/mainboard/aopen/dxplplusu/acpi/power.asl D src/mainboard/aopen/dxplplusu/acpi/scsi.asl D src/mainboard/aopen/dxplplusu/acpi/superio.asl D src/mainboard/aopen/dxplplusu/acpi_tables.c D src/mainboard/aopen/dxplplusu/board_info.txt D src/mainboard/aopen/dxplplusu/bootblock.c D src/mainboard/aopen/dxplplusu/devicetree.cb D src/mainboard/aopen/dxplplusu/dsdt.asl D src/mainboard/aopen/dxplplusu/fadt.c D src/mainboard/aopen/dxplplusu/romstage.c D src/mainboard/asrock/e350m1/BiosCallOuts.c D src/mainboard/asrock/e350m1/Kconfig D src/mainboard/asrock/e350m1/Kconfig.name D src/mainboard/asrock/e350m1/Makefile.inc D src/mainboard/asrock/e350m1/OemCustomize.c D src/mainboard/asrock/e350m1/OptionsIds.h D src/mainboard/asrock/e350m1/acpi/gpe.asl D src/mainboard/asrock/e350m1/acpi/mainboard.asl D src/mainboard/asrock/e350m1/acpi/routing.asl D src/mainboard/asrock/e350m1/acpi/sata.asl D src/mainboard/asrock/e350m1/acpi/sleep.asl D src/mainboard/asrock/e350m1/acpi/superio.asl D src/mainboard/asrock/e350m1/acpi/usb_oc.asl D src/mainboard/asrock/e350m1/acpi_tables.c D src/mainboard/asrock/e350m1/board_info.txt D src/mainboard/asrock/e350m1/bootblock.c D src/mainboard/asrock/e350m1/buildOpts.c D src/mainboard/asrock/e350m1/cmos.layout D src/mainboard/asrock/e350m1/devicetree.cb D src/mainboard/asrock/e350m1/dsdt.asl D src/mainboard/asrock/e350m1/irq_tables.c D src/mainboard/asrock/e350m1/mainboard.c D src/mainboard/asrock/e350m1/mptable.c D src/mainboard/asrock/e350m1/platform_cfg.h D src/mainboard/asrock/imb-a180/BiosCallOuts.c D src/mainboard/asrock/imb-a180/Kconfig D src/mainboard/asrock/imb-a180/Kconfig.name D src/mainboard/asrock/imb-a180/Makefile.inc D src/mainboard/asrock/imb-a180/OemCustomize.c D src/mainboard/asrock/imb-a180/OptionsIds.h D src/mainboard/asrock/imb-a180/acpi/gpe.asl D src/mainboard/asrock/imb-a180/acpi/ide.asl D src/mainboard/asrock/imb-a180/acpi/mainboard.asl D src/mainboard/asrock/imb-a180/acpi/routing.asl D src/mainboard/asrock/imb-a180/acpi/sata.asl D src/mainboard/asrock/imb-a180/acpi/si.asl D src/mainboard/asrock/imb-a180/acpi/sleep.asl D src/mainboard/asrock/imb-a180/acpi/superio.asl D src/mainboard/asrock/imb-a180/acpi/thermal.asl D src/mainboard/asrock/imb-a180/acpi/usb_oc.asl D src/mainboard/asrock/imb-a180/acpi_tables.c D src/mainboard/asrock/imb-a180/board_info.txt D src/mainboard/asrock/imb-a180/bootblock.c D src/mainboard/asrock/imb-a180/buildOpts.c D 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D src/mainboard/asus/f2a85-m/board_info.txt D src/mainboard/asus/f2a85-m/bootblock.c D src/mainboard/asus/f2a85-m/buildOpts.c D src/mainboard/asus/f2a85-m/cmos.layout D src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb D src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb D src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb D src/mainboard/asus/f2a85-m/dsdt.asl D src/mainboard/asus/f2a85-m/irq_tables.c D src/mainboard/asus/f2a85-m/mainboard.c D src/mainboard/asus/f2a85-m/mptable.c D src/mainboard/asus/f2a85-m/romstage.c D src/mainboard/biostar/Kconfig D src/mainboard/biostar/Kconfig.name D src/mainboard/biostar/am1ml/BiosCallOuts.c D src/mainboard/biostar/am1ml/Kconfig D src/mainboard/biostar/am1ml/Kconfig.name D src/mainboard/biostar/am1ml/Makefile.inc D src/mainboard/biostar/am1ml/OemCustomize.c D src/mainboard/biostar/am1ml/OptionsIds.h D src/mainboard/biostar/am1ml/acpi/flag0.asl D src/mainboard/biostar/am1ml/acpi/gpe.asl D src/mainboard/biostar/am1ml/acpi/ide.asl D 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src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd D src/mainboard/google/kahlee/variants/baseboard/gpio.c D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/gpe.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/sleep.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h D src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h D src/mainboard/google/kahlee/variants/baseboard/mainboard.c D src/mainboard/google/kahlee/variants/baseboard/memory.c D src/mainboard/google/kahlee/variants/baseboard/romstage.c D src/mainboard/google/kahlee/variants/baseboard/spd/Makefile.inc D src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c D src/mainboard/google/kahlee/variants/careena/Makefile.inc D src/mainboard/google/kahlee/variants/careena/devicetree.cb D src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl D src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl D src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl D src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl D src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl D src/mainboard/google/kahlee/variants/careena/include/variant/ec.h D src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h D src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h D src/mainboard/google/kahlee/variants/careena/spd/Makefile.inc D src/mainboard/google/kahlee/variants/grunt/Makefile.inc D src/mainboard/google/kahlee/variants/grunt/devicetree.cb D src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/gpe.asl D src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl D src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/routing.asl D src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/sleep.asl D src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/thermal.asl D src/mainboard/google/kahlee/variants/grunt/include/variant/ec.h D src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h D src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h D src/mainboard/google/kahlee/variants/liara/Makefile.inc D src/mainboard/google/kahlee/variants/liara/devicetree.cb D src/mainboard/google/kahlee/variants/liara/include/variant/acpi/gpe.asl D src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl D 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src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h D src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h D src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h D src/mainboard/google/kahlee/variants/treeya/spd/Makefile.inc D src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c D src/mainboard/hp/pavilion_m6_1035dx/Kconfig D src/mainboard/hp/pavilion_m6_1035dx/Kconfig.name D src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc D src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c D src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h D src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/sata.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/si.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/superio.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/thermal.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi/usb_oc.asl D src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c D src/mainboard/hp/pavilion_m6_1035dx/board_info.txt D src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c D src/mainboard/hp/pavilion_m6_1035dx/cmos.default D src/mainboard/hp/pavilion_m6_1035dx/cmos.layout D src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb D src/mainboard/hp/pavilion_m6_1035dx/dsdt.asl D src/mainboard/hp/pavilion_m6_1035dx/ec.c D src/mainboard/hp/pavilion_m6_1035dx/ec.h D src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c D src/mainboard/hp/pavilion_m6_1035dx/mainboard.c D src/mainboard/hp/pavilion_m6_1035dx/mainboard.h D src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c D src/mainboard/hp/pavilion_m6_1035dx/mptable.c D src/mainboard/intel/strago/Kconfig D src/mainboard/intel/strago/Kconfig.name D src/mainboard/intel/strago/Makefile.inc D src/mainboard/intel/strago/acpi/dptf.asl D src/mainboard/intel/strago/acpi/ec.asl D src/mainboard/intel/strago/acpi/mainboard.asl D src/mainboard/intel/strago/acpi/superio.asl D src/mainboard/intel/strago/acpi_tables.c D src/mainboard/intel/strago/board_info.txt D src/mainboard/intel/strago/chromeos.c D src/mainboard/intel/strago/chromeos.fmd D src/mainboard/intel/strago/cmos.layout D src/mainboard/intel/strago/com_init.c D src/mainboard/intel/strago/devicetree.cb D src/mainboard/intel/strago/dsdt.asl D src/mainboard/intel/strago/ec.c D src/mainboard/intel/strago/ec.h D src/mainboard/intel/strago/fadt.c D src/mainboard/intel/strago/gpio.c D src/mainboard/intel/strago/irqroute.c D src/mainboard/intel/strago/irqroute.h D src/mainboard/intel/strago/mainboard.c D src/mainboard/intel/strago/onboard.h D src/mainboard/intel/strago/ramstage.c D src/mainboard/intel/strago/romstage.c D src/mainboard/intel/strago/smihandler.c D src/mainboard/intel/strago/w25q64.c D src/mainboard/lenovo/g505s/BiosCallOuts.c D src/mainboard/lenovo/g505s/Kconfig D src/mainboard/lenovo/g505s/Kconfig.name D src/mainboard/lenovo/g505s/Makefile.inc D src/mainboard/lenovo/g505s/OemCustomize.c D src/mainboard/lenovo/g505s/OptionsIds.h D src/mainboard/lenovo/g505s/acpi/ec.asl D src/mainboard/lenovo/g505s/acpi/gpe.asl D src/mainboard/lenovo/g505s/acpi/mainboard.asl D src/mainboard/lenovo/g505s/acpi/routing.asl D src/mainboard/lenovo/g505s/acpi/sata.asl D src/mainboard/lenovo/g505s/acpi/si.asl D src/mainboard/lenovo/g505s/acpi/sleep.asl D src/mainboard/lenovo/g505s/acpi/superio.asl D src/mainboard/lenovo/g505s/acpi/thermal.asl D src/mainboard/lenovo/g505s/acpi/usb_oc.asl D src/mainboard/lenovo/g505s/acpi_tables.c D src/mainboard/lenovo/g505s/board_info.txt D src/mainboard/lenovo/g505s/buildOpts.c D src/mainboard/lenovo/g505s/cmos.layout D src/mainboard/lenovo/g505s/config_seabios D src/mainboard/lenovo/g505s/devicetree.cb D src/mainboard/lenovo/g505s/dsdt.asl D src/mainboard/lenovo/g505s/ec.c D src/mainboard/lenovo/g505s/ec.h D src/mainboard/lenovo/g505s/irq_tables.c D src/mainboard/lenovo/g505s/mainboard.c D src/mainboard/lenovo/g505s/mainboard.h D src/mainboard/lenovo/g505s/mainboard_smi.c D src/mainboard/lenovo/g505s/mptable.c D src/mainboard/msi/ms7721/BiosCallOuts.c D src/mainboard/msi/ms7721/Kconfig D src/mainboard/msi/ms7721/Kconfig.name D src/mainboard/msi/ms7721/Makefile.inc D src/mainboard/msi/ms7721/OemCustomize.c D src/mainboard/msi/ms7721/OptionsIds.h D src/mainboard/msi/ms7721/acpi/cpstate.asl D src/mainboard/msi/ms7721/acpi/gpe.asl D src/mainboard/msi/ms7721/acpi/mainboard.asl D src/mainboard/msi/ms7721/acpi/routing.asl D src/mainboard/msi/ms7721/acpi/sata.asl D src/mainboard/msi/ms7721/acpi/si.asl D src/mainboard/msi/ms7721/acpi/sleep.asl D src/mainboard/msi/ms7721/acpi/superio.asl D src/mainboard/msi/ms7721/acpi/thermal.asl D src/mainboard/msi/ms7721/acpi_tables.c D src/mainboard/msi/ms7721/board_info.txt D src/mainboard/msi/ms7721/buildOpts.c D src/mainboard/msi/ms7721/cmos.layout D src/mainboard/msi/ms7721/devicetree.cb D src/mainboard/msi/ms7721/dsdt.asl D src/mainboard/msi/ms7721/irq_tables.c D src/mainboard/msi/ms7721/mainboard.c D src/mainboard/msi/ms7721/mptable.c D src/mainboard/msi/ms7721/romstage.c D src/mainboard/pcengines/Kconfig D src/mainboard/pcengines/Kconfig.name D src/mainboard/pcengines/apu1/BiosCallOuts.c D src/mainboard/pcengines/apu1/Kconfig D src/mainboard/pcengines/apu1/Kconfig.name D src/mainboard/pcengines/apu1/Makefile.inc D src/mainboard/pcengines/apu1/OemCustomize.c D src/mainboard/pcengines/apu1/OptionsIds.h D src/mainboard/pcengines/apu1/acpi/buttons.asl D src/mainboard/pcengines/apu1/acpi/gpe.asl D src/mainboard/pcengines/apu1/acpi/gpio.asl D src/mainboard/pcengines/apu1/acpi/leds.asl D src/mainboard/pcengines/apu1/acpi/mainboard.asl D src/mainboard/pcengines/apu1/acpi/routing.asl D src/mainboard/pcengines/apu1/acpi/sata.asl D src/mainboard/pcengines/apu1/acpi/sleep.asl D src/mainboard/pcengines/apu1/acpi/superio.asl D src/mainboard/pcengines/apu1/acpi/usb_oc.asl D src/mainboard/pcengines/apu1/acpi_tables.c D src/mainboard/pcengines/apu1/board_info.txt D src/mainboard/pcengines/apu1/bootblock.c D src/mainboard/pcengines/apu1/buildOpts.c D src/mainboard/pcengines/apu1/cmos.default D src/mainboard/pcengines/apu1/cmos.layout D src/mainboard/pcengines/apu1/devicetree.cb D src/mainboard/pcengines/apu1/dsdt.asl D src/mainboard/pcengines/apu1/gpio_ftns.c D src/mainboard/pcengines/apu1/gpio_ftns.h D src/mainboard/pcengines/apu1/irq_tables.c D src/mainboard/pcengines/apu1/mainboard.c D src/mainboard/pcengines/apu1/mptable.c D src/mainboard/pcengines/apu1/platform_cfg.h D src/mainboard/pcengines/apu1/romstage.c D src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex D src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex D src/mainboard/pcengines/apu2/BiosCallOuts.c D src/mainboard/pcengines/apu2/Kconfig D src/mainboard/pcengines/apu2/Kconfig.name D src/mainboard/pcengines/apu2/Makefile.inc D src/mainboard/pcengines/apu2/OemCustomize.c D src/mainboard/pcengines/apu2/acpi/gpe.asl D src/mainboard/pcengines/apu2/acpi/mainboard.asl D src/mainboard/pcengines/apu2/acpi/routing.asl D src/mainboard/pcengines/apu2/acpi/si.asl D src/mainboard/pcengines/apu2/acpi/sleep.asl D src/mainboard/pcengines/apu2/acpi/usb_oc.asl D src/mainboard/pcengines/apu2/acpi_tables.c D src/mainboard/pcengines/apu2/board_info.txt D src/mainboard/pcengines/apu2/bootblock.c D src/mainboard/pcengines/apu2/cmos.layout D src/mainboard/pcengines/apu2/dsdt.asl D src/mainboard/pcengines/apu2/gpio_ftns.c D src/mainboard/pcengines/apu2/gpio_ftns.h D src/mainboard/pcengines/apu2/irq_tables.c D src/mainboard/pcengines/apu2/mainboard.c D src/mainboard/pcengines/apu2/mptable.c D src/mainboard/pcengines/apu2/romstage.c D src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex D src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex D src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb D src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/northbridge/amd/agesa/family14/acpi/northbridge.asl M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00660F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/intel/broadwell/acpi/serialio.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl M util/crossgcc/buildgcc D util/crossgcc/patches/acpica-unix2-20190703_iasl.patch D util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20191213.tar.gz.cksum 448 files changed, 6 insertions(+), 36,897 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37826/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1696945622ec0fe955084f89d9dc37bd6f8815f0 Gerrit-Change-Number: 37826 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 17

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Furquan Shaikh (Code Review) 26 Dec '19

26 Dec '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 12: (7 comments) https://review.coreboot.org/c/coreboot/+/37427/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37427/12//COMMIT_MSG@13 PS12, Line 13: > Yes. But there is a problem.With that kernel the it only list the first 67 pins(group 0). […] I don't understand what you mean by "list the first 67 pins". Have you seen the comment about assigning numbers to GPD pins? Did you try the suggestion there? https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 169: GPP_B_DW0_1 > This is for progarmming the MISCCFG register for each community. […] In that case why is GPP_B named as GPP_B_DW0_1 and GPP_B_DW2? https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 26: * DW0,1 and DW2. Based on this the devicetree should assign them. : * Example of devicetree: : * register "gpe0_dw0" = "GPP_C_DW0_1" # GPP_C : * register "gpe0_dw1" = "GPP_D_DW0_1" # GPP_D : * register "gpe0_dw2" = "GPP_E_DW2" # GPP_E > OK. I will try to implement this in soc specific driver. I don't want to change the common code. I would recommend thinking if this can be solved in a generic way across Intel platforms. Reason is because we tend to copy-paste mainboard code from older to newer boards and in general gpe0_dw0, gpe0_dw1 and gpe0_dw2 naming remains consistent. It would be good if we can establish what those really mean i.e. GPE0_DWx configuration in PMC, GPIO communities or a separate coreboot-specific naming. For TGL and effectively for JSL, you would be going with the third option i.e. coreboot specific naming. --> GPP_A ... GPP_* : Coreboot-specific numbering scheme --> Common code when configuring GPIO_CFG : Queries for gpe0_dwx which SoC can adjust based on the DWx where the mapping is being done. This is basically "coreboot-specific numbering" to "PMC identifiable numbering". --> Common/SoC code when configuring GPIO community DWx: Queries for gpe0_dwx which SoC can adjust based on DWx where the mapping is being done. This is basically "coreboot-specific numbering" to "GPIO community identifiable numbering". In the future, if the numbering for each community for each DWx is different, that can be handled here too. Depending upon SoC implementation, all, few or none of the mappings above can be identity mapping. But, the common code would remain the same. BTW, before jumping into this implementation, have you verified with the EDS author that the GPE0_DWx numbering for the PMC in GPIO_CFG register is actually different for different DWx and not a typo in the document? Also, have you verified by doing various configurations in mainboard whether the GPE_STS registers in PMC get updated as per your expectation for DW0, DW1 and DW2? https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 225: GPP_VGPIO0 > Kernel is using native functions as the name here. […] Yeah, that might make it easier to follow what the GPIOs are. Or maybe add a comment here indicating what the vGPIO is? https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 374: #define GPP_MLK 277 > I got this from the excel sheet shared by the hardware team. […] If this is something that is present in hardware, I would recommend working with the kernel team to see if this was intentionally dropped there or just a miss. Ideally it would be better to update the kernel driver to handle it. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 401: 5 > Yes. Because of the missing community i kept the total number as 5. But, then your assignment for the properties of the communities are all messed up? BTW, why is GPIOCOM3 missing? https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 118: #define PMC_GPP_B 0x0 : #define PMC_GPP_T 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPD 0x4 : #define PMC_GPP_S 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_U 0x8 : #define PMC_GPP_F 0xA : #define PMC_GPP_C 0xB : #define PMC_GPP_E 0xC > My understanding was this is used for programming MISCCFG. […] These are configured in GPIO_CFG register in PMC: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/common/blo… -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 26 Dec 2019 01:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Remove default devicetree values
by Patrick Rudolph (Code Review) 25 Dec '19

25 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37467 ) Change subject: mb/supermicro/x11-lga1151-series: Remove default devicetree values ...................................................................... mb/supermicro/x11-lga1151-series: Remove default devicetree values The same default values are used if the values are not present in devicetree. Change-Id: Ic910cdc8077e1b3e98eadc77a2d1fa0f9cb38e5b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 1 file changed, 0 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/37467/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b58fbf1..ee7c932 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -95,63 +95,6 @@ register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - # VR Settings Configuration for 4 Domains - # ICC_MAX = 0 (Auto) - # Voltage limit 1.52V (not used on KBL-S and KBL-DT) - # Disable PS4 powerstate in S0ix, thus no package C10 support - # psi threshold is using FSP default values - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0, \ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0 ,\ - .voltage_limit = 1520 \ - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, \ - .psi4enable = 0, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0, \ - .voltage_limit = 1520 \ - }" - # No extra VR mailbox command register "SendVrMbxCmd" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/37467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic910cdc8077e1b3e98eadc77a2d1fa0f9cb38e5b Gerrit-Change-Number: 37467 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/skylake/vr_config: Use lookup table by default
by Patrick Rudolph (Code Review) 25 Dec '19

25 Dec '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37598 ) Change subject: soc/intel/skylake/vr_config: Use lookup table by default ...................................................................... soc/intel/skylake/vr_config: Use lookup table by default If the board doesn't provide VRconfig in devicetree make sure to use the lookup table for IccMax instead of defaults for some mobile SoC. Also use decimal values instead of hex. Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/37598/1 diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 54dfd31..9a4ddd8 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -31,9 +31,9 @@ .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, [VR_IA_CORE] = { @@ -43,9 +43,9 @@ .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, [VR_GT_UNSLICED] = { @@ -55,9 +55,9 @@ .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, [VR_GT_SLICED] = { @@ -67,9 +67,9 @@ .psi3threshold = VR_CFG_AMP(1), .psi3enable = 0, .psi4enable = 0, - .imon_slope = 0x0, - .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .imon_slope = 0, + .imon_offset = 0, + .icc_max = 0, .voltage_limit = 1520, }, }; @@ -334,6 +334,7 @@ vr_params->Psi4Enable[domain] = cfg->psi4enable; vr_params->ImonSlope[domain] = cfg->imon_slope; vr_params->ImonOffset[domain] = cfg->imon_offset; + /* If board provided non-zero value, use it. */ if (cfg->icc_max) vr_params->IccMax[domain] = cfg->icc_max; -- To view, visit https://review.coreboot.org/c/coreboot/+/37598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445 Gerrit-Change-Number: 37598 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/tigerlake: Update GPIO config
by Shaunak Saha (Code Review) 25 Dec '19

25 Dec '19

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 ) Change subject: soc/intel/tigerlake: Update GPIO config ...................................................................... Patch Set 12: (28 comments) https://review.coreboot.org/c/coreboot/+/37427/12//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37427/12//COMMIT_MSG@10 PS12, Line 10: GPIO's > GPIOs Ack https://review.coreboot.org/c/coreboot/+/37427/12//COMMIT_MSG@13 PS12, Line 13: > I am looking at this as reference: https://github. […] Yes. But there is a problem.With that kernel the it only list the first 67 pins(group 0). But as far as the group ordering is concerned this should be fine. https://review.coreboot.org/c/coreboot/+/37427/12//COMMIT_MSG@14 PS12, Line 14: none > b:144680462 Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/a… File src/soc/intel/tigerlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/a… PS12, Line 78: LAnd (LGreaterEqual (Arg0, GPP_B0), LLessEqual (Arg0, ESPI_CLK_LOOPBK)) > It would be better to stick to ASL2.0 syntax as it was before. […] Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/a… PS12, Line 101: * > space before * Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/a… PS12, Line 101: 05 > "5" to keep the naming consistent. Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/a… PS12, Line 140: And (GPIOTXSTATE_MASK, VAL0, Local0) > Can you please use ASL2. […] Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/a… PS12, Line 159: > extra blank lines Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… File src/soc/intel/tigerlake/gpio.c: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 20: * Chapter number: 27 > Was the chapter number dropped intentionally? It was a mistake.Will add. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 87: [COMM_0] > Why were these dropped? Because of this, now you would be setting the properties of community 4 to [ […] Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 94: gpi_int_sts_reg_0 = GPI_INT_STS_0, : .gpi_int_en_reg_0 = GPI_INT_EN_0, > Why were these fields dropped? Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 44: INTEL_GPP_BASE > Why do we need INTEL_GPP_BASE for TGL? I think it should be perfectly fine to use INTEL_GPP instead […] Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 45: INTEL_GPP(GPP_B0, GSPI0_CLK_LOOPBK, GSPI1_CLK_LOOPBK) > Can't these be clubbed with the above entry? […] Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 51: INTEL_GPP_BASE > Same question about using INTEL_GPP instead of INTEL_GPP_BASE for all entries here. Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 93: S,D,H,U,VGPIO > nit: space after comma Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/g… PS12, Line 169: GPP_B_DW0_1 > Why are all the entries here mapping to DW0_1 only? What happens if a mapping for DW2 is required? This is for progarmming the MISCCFG register for each community. As per EDS the mapping in MISCCFG is same as the Dw0,Dw1 in GPIO_CFG. So i kept it like this here. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 268: #define GPI_INT_STS_0 0x100 : #define GPI_INT_EN_0 0x110 > Why were these dropped? Will check. I just rebased on top of patchset 11. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 130: Group D > This is not GPP Group D. Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 255: iIRQ > extra i Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 26: * DW0,1 and DW2. Based on this the devicetree should assign them. : * Example of devicetree: : * register "gpe0_dw0" = "GPP_C_DW0_1" # GPP_C : * register "gpe0_dw1" = "GPP_D_DW0_1" # GPP_D : * register "gpe0_dw2" = "GPP_E_DW2" # GPP_E > Do we really need to do that? Is it possible for us to have a mapping scheme such that the devicetre […] OK. I will try to implement this in soc specific driver. I don't want to change the common code. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 89: GSPI0_CLK_LOOPBK > So, there is no GPP# for this pad? e.g. […] Will rename this to B24. The name B24 is not there but its ok to name for simplicity. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 135: ESPI_CLK_LOOPBK > No GPP#? Will rename this to A24. The name B24 is not there but its ok to name for simplicity. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 225: GPP_VGPIO0 > Can we use the same names as used by the kernel driver? Kernel is using native functions as the name here. You are suggesting to use those names here? https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 256: #define GPD0 171 > This community is not exposed or used by the kernel driver. […] Checking the kernel and acpi code how they are handled previously. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 369: TSSTB > TRSTB? Ack https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 374: #define GPP_MLK 277 > I don't see this in the kernel driver. I got this from the excel sheet shared by the hardware team. Will remove this if kernel does not have this pin. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 401: 5 > How is this 5? There is GPIOCOM0 - GPIOCOM5 which is a total of 6? Is this because GPIOCOM3 is missi […] Yes. Because of the missing community i kept the total number as 5. https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… File src/soc/intel/tigerlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/37427/12/src/soc/intel/tigerlake/i… PS12, Line 118: #define PMC_GPP_B 0x0 : #define PMC_GPP_T 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_R 0x3 : #define PMC_GPD 0x4 : #define PMC_GPP_S 0x5 : #define PMC_GPP_H 0x6 : #define PMC_GPP_D 0x7 : #define PMC_GPP_U 0x8 : #define PMC_GPP_F 0xA : #define PMC_GPP_C 0xB : #define PMC_GPP_E 0xC > As per EDS version 1, this is not correct. I see PMC GPP values being different based on DWx. My understanding was this is used for programming MISCCFG. In EDS MISCCFG values are not changing form one DW to another.Can you please confirm. -- To view, visit https://review.coreboot.org/c/coreboot/+/37427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa Gerrit-Change-Number: 37427 Gerrit-PatchSet: 12 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Venkata Krishna Nimmagadda Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Dec 2019 08:01:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/puff: Add GPIO configuration
by Edward O'Callaghan (Code Review) 25 Dec '19

25 Dec '19

Hello Kangheui Won, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37925 to review the following change. Change subject: mainboard/google/puff: Add GPIO configuration ...................................................................... mainboard/google/puff: Add GPIO configuration BUG=b:144809606,142094759 BRANCH=none TEST=none Change-Id: Iae20d2262c910044dde84f10d795f4aee3318532 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Signed-off-by: Kangheui Won <khwon(a)chromium.org> Co-Author: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/hatch/variants/puff/gpio.c 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/37925/1 diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/hatch/variants/puff/gpio.c index 046733e..6ff700d 100644 --- a/src/mainboard/google/hatch/variants/puff/gpio.c +++ b/src/mainboard/google/hatch/variants/puff/gpio.c @@ -17,6 +17,78 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> +static const struct pad_config gpio_table[] = { + /* A16 : SD_OC_ODL */ + PAD_CFG_GPI(GPP_A16, NONE, DEEP), + /* A18 : LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A23 : M2_WLAN_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B5 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* C0 : SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1 : SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C6: M2_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), + /* C7 : LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), + /* C10 : PCH_PCON_RST_ODL */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : PCH_PCON_PDB_ODL */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), + + /* E2 : EN_PP_MST_OD */ + PAD_CFG_GPO(GPP_E2, 1, DEEP), + /* E9 : USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* F11 : EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* GPP_F23 : A4WP_PRESENT */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H4: PCH_I2C_PCON_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5: PCH_I2C_PCON_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H22 : PWM_PP3300_BIOZZER */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* B14 : GPP_B14_STRAP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae20d2262c910044dde84f10d795f4aee3318532 Gerrit-Change-Number: 37925 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux comments
by Edward O'Callaghan (Code Review) 25 Dec '19

25 Dec '19

Hello Edward O'Callaghan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37592 to review the following change. Change subject: mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux comments ...................................................................... mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux comments Follow MEM_STRAP_* comment style to be consistent with other boards. BUG=b:144809606 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37592/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 4ebd258..b59d741 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -55,13 +55,13 @@ PAD_NC(GPP_E23, NONE), /* F1 : GPP_F1 ==> NC */ PAD_NC(GPP_F1, NONE), - /* F11 : PCH_MEM_STRAP2 */ + /* F11 : PCH_MEM_STRAP_2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), - /* F20 : PCH_MEM_STRAP0 */ + /* F20 : PCH_MEM_STRAP_0 */ PAD_CFG_GPI(GPP_F20, NONE, PLTRST), - /* F21 : PCH_MEM_STRAP1 */ + /* F21 : PCH_MEM_STRAP_1 */ PAD_CFG_GPI(GPP_F21, NONE, PLTRST), - /* F22 : PCH_MEM_STRAP3 */ + /* F22 : PCH_MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* G0 : GPP_G0 ==> NC */ PAD_NC(GPP_G0, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/37592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3 Gerrit-Change-Number: 37592 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard
by Edward O'Callaghan (Code Review) 25 Dec '19

25 Dec '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37922 ) Change subject: mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard ...................................................................... mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/dratini/gpio.c M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/kindred/gpio.c M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/mushu/gpio.c M src/mainboard/google/hatch/variants/stryke/gpio.c 8 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37922/1 diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 1000a08..ff4f358 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -134,6 +134,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H6 : NC */ PAD_NC(GPP_H6, NONE), /* H7 : NC */ diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 2c3bf8d..dcd987f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -334,8 +334,8 @@ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), - /* H3 : SPKR_PA_EN */ - PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), /* H4 : PCH_I2C_PEN_SDA */ PAD_NC(GPP_H4, NONE), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index aa32e6e..3a2ceaf 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -59,6 +59,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 03ea2e2..1e945cc 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -55,6 +55,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 7b62027..fdad243 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -61,6 +61,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : EMMC_RESET# ==> NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -116,6 +118,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ @@ -165,6 +169,8 @@ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* F22 : EMMC_RESET# ==> EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 50d0cb3..5f9ca2d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -77,6 +77,8 @@ PAD_NC(GPP_G5, NONE), /* G6 : GPP_G6 ==> NC */ PAD_NC(GPP_G6, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H4 : PCH_I2C_PEN_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : PCH_I2C_PEN_SCL */ diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 05278fb..ce589e5 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -35,6 +35,8 @@ PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; /* C15 : WWAN_DPR_SAR_ODL */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), const struct pad_config *override_gpio_table(size_t *num) { diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c index c548544..f3f40a7 100644 --- a/src/mainboard/google/hatch/variants/stryke/gpio.c +++ b/src/mainboard/google/hatch/variants/stryke/gpio.c @@ -49,6 +49,8 @@ PAD_NC(GPP_F21, NONE), /* F22 : NC */ PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Gerrit-Change-Number: 37922 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019