coreboot-gerrit December 2019

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Change in coreboot[master]: Doc/index.md: Fix a typo
by Angel Pons (Code Review) 26 Dec '19

26 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37934 ) Change subject: Doc/index.md: Fix a typo ...................................................................... Doc/index.md: Fix a typo Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/index.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37934/1 diff --git a/Documentation/index.md b/Documentation/index.md index bfc9cea..b636b61 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -175,7 +175,7 @@ * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) * [Display panel](gfx/display-panel.md) * [CPU Architecture](arch/index.md) -* [Platform independend drivers](drivers/index.md) +* [Platform independent drivers](drivers/index.md) * [Northbridge](northbridge/index.md) * [System on Chip](soc/index.md) * [Mainboard](mainboard/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/37934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612 Gerrit-Change-Number: 37934 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/generic/cbfs-serial: Add driver to read serial from CBFS
by Matt DeVillier (Code Review) 26 Dec '19

26 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37917 ) Change subject: drivers/generic/cbfs-serial: Add driver to read serial from CBFS ...................................................................... drivers/generic/cbfs-serial: Add driver to read serial from CBFS Add a new driver to support reading a board serial number from a test file in CBFS and injecting into the SMBIOS tables. Allow driver to be selected at the .config level and not require inclusion at the board level. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af --- A src/drivers/generic/cbfs-serial/Kconfig A src/drivers/generic/cbfs-serial/Makefile.inc A src/drivers/generic/cbfs-serial/cbfs-serial.c 3 files changed, 57 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37917/1 diff --git a/src/drivers/generic/cbfs-serial/Kconfig b/src/drivers/generic/cbfs-serial/Kconfig new file mode 100644 index 0000000..209c242 --- /dev/null +++ b/src/drivers/generic/cbfs-serial/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_GENERIC_CBFS_SERIAL + bool "Serial number in CBFS" + default n + help + Enable this option to read the board serial number from a + text file located in CBFS. diff --git a/src/drivers/generic/cbfs-serial/Makefile.inc b/src/drivers/generic/cbfs-serial/Makefile.inc new file mode 100644 index 0000000..163d439 --- /dev/null +++ b/src/drivers/generic/cbfs-serial/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_CBFS_SERIAL) += cbfs-serial.c diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c new file mode 100644 index 0000000..ee3e366 --- /dev/null +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <device/device.h> +#include <smbios.h> +#include <string.h> + + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af Gerrit-Change-Number: 37917 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/x86|cpu/intel: Hardcode FIT and ID
by Marshall Dawson (Code Review) 26 Dec '19

26 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37877 ) Change subject: src/x86|cpu/intel: Hardcode FIT and ID ...................................................................... src/x86|cpu/intel: Hardcode FIT and ID Revert two of the changes made in "arch|cpu/x86: Add Kconfig option for x86 reset vector" I6a814f7179ee4251aeeccb2555221616e944e03d The Intel FIT pointer and the ID section should be offsets from the top of flash, and aren't inherently tied to the reset vector or to bootblock. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf --- M src/arch/x86/id.ld M src/cpu/intel/fit/fit.ld 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37877/1 diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index 3d9ef37..2a50f9c 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -12,7 +12,7 @@ */ SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 0x10; + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; .id (.): { KEEP(*(.id)) } diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld index 2e65186..6e30ea1 100644 --- a/src/cpu/intel/fit/fit.ld +++ b/src/cpu/intel/fit/fit.ld @@ -12,7 +12,7 @@ */ SECTIONS { - . = CONFIG_X86_RESET_VECTOR - 0x30; /* 0xffffffc0 */ + . = 0xffffffc0; .fit_pointer (.): { KEEP(*(.fit_pointer)) } -- To view, visit https://review.coreboot.org/c/coreboot/+/37877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf Gerrit-Change-Number: 37877 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Configure APOB NV only with ACPI resume
by Marshall Dawson (Code Review) 26 Dec '19

26 Dec '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37722 ) Change subject: soc/amd/picasso: Configure APOB NV only with ACPI resume ...................................................................... soc/amd/picasso: Configure APOB NV only with ACPI resume The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37722/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e192818..c168ebb 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -325,21 +325,15 @@ config PSP_APOB_NV_ADDRESS hex "Base address of APOB NV" - default 0xffa68000 help Location in flash where the PSP can find the S3 restore information. Place this on a boundary that the flash device can erase. - TODO: The above default value is arbitrary, but eventually coreboot's - MRC cache base address should be used. config PSP_APOB_NV_SIZE hex "Size of APOB NV to be reserved" - default 0x10000 help Size of the S3 restore information. Make this a multiple of the size the flash device can erase. - TODO: The above default value is arbitrary, but eventually coreboot's - MRC cache size should be used. config USE_PSPSCUREOS bool "Include PSP SecureOS blobs in PSP build" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 76a4d70..0577934 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -208,8 +208,10 @@ PSP_BIOSBIN_SIZE=$(CONFIG_RAM_RESET_VECTOR_STAGE_SIZE) # type = 0x63 +ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) +endif # type2 = 0x64, 0x65 PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/37722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Gerrit-Change-Number: 37722 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/akemi: Set touchpad hold time to 400ns
by Peichao Li (Code Review) 26 Dec '19

26 Dec '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37322 ) Change subject: mb/google/hatch/akemi: Set touchpad hold time to 400ns ...................................................................... mb/google/hatch/akemi: Set touchpad hold time to 400ns According to SI team request, need to tune I2C bus 0 data hold time more than 300ns BUG=None TEST=build firmware and measure I2C bus 0 data hold time Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9 --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/37322/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index da669e4..937810b 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -57,6 +57,7 @@ .speed = I2C_SPEED_FAST, .rise_time_ns = 50, .fall_time_ns = 15, + .data_hold_time_ns = 400, }, .i2c[1] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/37322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9 Gerrit-Change-Number: 37322 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/releases/checklist.md: Correct format inconsistencies
by Angel Pons (Code Review) 26 Dec '19

26 Dec '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37709 ) Change subject: Doc/releases/checklist.md: Correct format inconsistencies ...................................................................... Doc/releases/checklist.md: Correct format inconsistencies Use periods on every element of a list, and make `IRC` uppercase. Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/releases/checklist.md 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/37709/1 diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index ff93141..4e85609 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -49,31 +49,31 @@ ## Checklist ### ~2 weeks prior to release - [ ] Announce upcoming release to mailing list, ask people to test and - to update release notes + to update release notes. ### ~1 week prior to release - [ ] Send reminder email to mailing list, ask for people to test, - and to update the release notes -- [ ] Update the topic in the irc channel with the date of the upcoming - release + and to update the release notes. +- [ ] Update the topic in the IRC channel with the date of the upcoming + release. - [ ] Finalize release notes (as much as possible), without specifying - release commit ids + release commit ids. ### Day of release - [ ] Select a commit ID to base the release upon, announce to IRC, ask for testing. -- [ ] Test the commit selected for release -- [ ] Update release notes with actual commit id, push to repo -- [ ] Run release script -- [ ] Test the release from the actual release tarballs -- [ ] Push signed Tag to repo -- [ ] Announce that the release tag is done on IRC +- [ ] Test the commit selected for release. +- [ ] Update release notes with actual commit id, push to repo. +- [ ] Run release script. +- [ ] Test the release from the actual release tarballs. +- [ ] Push signed Tag to repo. +- [ ] Announce that the release tag is done on IRC. - [ ] Upload release files to web server -- [ ] Upload crossgcc sources to web server -- [ ] Update download page to point to files, push to repo +- [ ] Upload crossgcc sources to web server. +- [ ] Update download page to point to files, push to repo. - [ ] Write and publish blog post with release notes. -- [ ] Update the topic in the irc channel that the release is done. -- [ ] Announce the release to the mailing list +- [ ] Update the topic in the IRC channel that the release is done. +- [ ] Announce the release to the mailing list. ## Pre-Release tasks Announce the upcoming release to the mailing list release 2 weeks ahead @@ -99,7 +99,7 @@ patches to be pulled in. When a release candidate has been selected, announce the commit ID to -the #coreboot irc channel, and request that it get some testing, just +the #coreboot IRC channel, and request that it get some testing, just to make sure that everything is sane. ## Generate the release -- To view, visit https://review.coreboot.org/c/coreboot/+/37709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c Gerrit-Change-Number: 37709 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/eve: select SYSTEM_TYPE_CONVERTIBLE
by Matt DeVillier (Code Review) 26 Dec '19

26 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37903 ) Change subject: mb/google/eve: select SYSTEM_TYPE_CONVERTIBLE ...................................................................... mb/google/eve: select SYSTEM_TYPE_CONVERTIBLE select SYSTEM_TYPE_CONVERTIBLE, which properly sets the SMBIOS chassis type, and allows the OS driver to recognize tablet mode capability Change-Id: Ic61659e9fa6f7428afd1f018fb8cb25fe49e8747 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/eve/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37903/1 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 31ff6e9..dcc5b38 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -21,6 +21,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 select SOC_INTEL_KABYLAKE + select SYSTEM_TYPE_CONVERTIBLE config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES -- To view, visit https://review.coreboot.org/c/coreboot/+/37903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic61659e9fa6f7428afd1f018fb8cb25fe49e8747 Gerrit-Change-Number: 37903 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/eve: Update and fix VBT
by Matt DeVillier (Code Review) 26 Dec '19

26 Dec '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37880 ) Change subject: mb/google/eve: Update and fix VBT ...................................................................... mb/google/eve: Update and fix VBT Update Eve's VBT from v211 to v221, and change the backlight control type from PWM to VESA eDP/AUX. This allows the OS to select the proper backlight control type for the panel. Test: Eve backlight control now functional under Windows 10 (Linux requires some pending patches to fix) Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/eve/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37880/1 diff --git a/src/mainboard/google/eve/data.vbt b/src/mainboard/google/eve/data.vbt index 2f950c8..0f17726 100644 --- a/src/mainboard/google/eve/data.vbt +++ b/src/mainboard/google/eve/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/37880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05 Gerrit-Change-Number: 37880 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused include <string.h>
by HAOUAS Elyes (Code Review) 26 Dec '19

26 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37888 ) Change subject: src: Remove unused include <string.h> ...................................................................... src: Remove unused include <string.h> Change-Id: Ic6b66dd8fa387e67bb0ce609fb7e2553eeb66b3c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/ebda.c M src/drivers/generic/gfx/gfx.c M src/lib/hexdump.c M src/lib/hexstrtobin.c M src/security/vboot/common.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/qualcomm/sc7180/aop_load_reset.c 8 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/37888/1 diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index f2727bb..f92f305 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -13,7 +13,6 @@ */ #include <stdint.h> -#include <string.h> #include <arch/acpi.h> #include <arch/ebda.h> #include <commonlib/endian.h> diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c index 76d311c..b2bda4a 100644 --- a/src/drivers/generic/gfx/gfx.c +++ b/src/drivers/generic/gfx/gfx.c @@ -19,7 +19,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <stdint.h> -#include <string.h> #include "chip.h" diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index 2c9e483..8ecba6d 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <ctype.h> #include <lib.h> -#include <string.h> void hexdump(const void *memory, size_t length) { diff --git a/src/lib/hexstrtobin.c b/src/lib/hexstrtobin.c index 61290b8..f0d3e9d 100644 --- a/src/lib/hexstrtobin.c +++ b/src/lib/hexstrtobin.c @@ -13,7 +13,6 @@ #include <ctype.h> #include <lib.h> -#include <string.h> size_t hexstrtobin(const char *str, uint8_t *buf, size_t len) { diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 214f6fa..aeb4498 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <fmap.h> #include <stdint.h> -#include <string.h> #include <symbols.h> #include <vb2_api.h> #include <security/vboot/misc.h> diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index db6b271..77cc21b 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> -#include <string.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <cpu/intel/turbo.h> diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index b0b416e..4a519cf 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -27,7 +27,6 @@ #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <string.h> static struct { u32 cpuid; diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 8d22d62..5cf2311 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <arch/cache.h> #include <cbfs.h> #include <halt.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b66dd8fa387e67bb0ce609fb7e2553eeb66b3c Gerrit-Change-Number: 37888 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon
by Chen Wisley (Code Review) 26 Dec '19

26 Dec '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37833 ) Change subject: hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon ...................................................................... hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon In https://review.coreboot.org/c/coreboot/+/37459, which move power/reset pin control of FPMCU to var/board/ramstage, but lose to implement in dratini/jinlon. So, add it in dratini/jinlon. BUG=b:146366921 TEST=emerge-hatch coreboot Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/Makefile.inc M src/mainboard/google/hatch/variants/dratini/gpio.c A src/mainboard/google/hatch/variants/dratini/ramstage.c M src/mainboard/google/hatch/variants/jinlon/Makefile.inc M src/mainboard/google/hatch/variants/jinlon/gpio.c A src/mainboard/google/hatch/variants/jinlon/ramstage.c 6 files changed, 125 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/37833/1 diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc index 4ed09c9..0d577cd 100644 --- a/src/mainboard/google/hatch/variants/dratini/Makefile.inc +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -26,3 +26,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 30d56d7..e6d39fb 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -138,3 +138,32 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dratini/ramstage.c b/src/mainboard/google/hatch/variants/dratini/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc index 6e5d883..c57d090 100644 --- a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc +++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc @@ -25,3 +25,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 7e475fa..c1b6885 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -108,3 +108,33 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} + diff --git a/src/mainboard/google/hatch/variants/jinlon/ramstage.c b/src/mainboard/google/hatch/variants/jinlon/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/jinlon/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f Gerrit-Change-Number: 37833 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2019