coreboot-gerrit November 2019

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Change in ...coreboot[master]: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by h...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33871 Change subject: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this motherboard. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33871/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbe..6d88992 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -54,4 +54,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 Gerrit-Change-Number: 33871 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mb/*/*{i440BX}: Enable console in bootblock
by Arthur Heymans (Code Review) 27 Mar '20

27 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36775 ) Change subject: mb/*/*{i440BX}: Enable console in bootblock ...................................................................... mb/*/*{i440BX}: Enable console in bootblock This renames and links romstage.c into both the bootblock and the romstage. The definition of spd_read_byte needs to be guarded in bootblock as the declaration is only done in bootblock. Change-Id: I87e5eb93c15a72f790739eff8395e7eecbf1eb04 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asus/p2b-d/Makefile.inc R src/mainboard/asus/p2b-d/early_init.c A src/mainboard/asus/p2b-ds/Makefile.inc R src/mainboard/asus/p2b-ds/early_init.c A src/mainboard/asus/p2b-f/Makefile.inc R src/mainboard/asus/p2b-f/early_init.c A src/mainboard/asus/p2b-ls/Makefile.inc R src/mainboard/asus/p2b-ls/early_init.c A src/mainboard/asus/p2b/Makefile.inc R src/mainboard/asus/p2b/early_init.c A src/mainboard/asus/p3b-f/Makefile.inc R src/mainboard/asus/p3b-f/early_init.c M src/northbridge/intel/i440bx/Kconfig M src/southbridge/intel/i82371eb/i82371eb.h 14 files changed, 46 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36775/1 diff --git a/src/mainboard/asus/p2b-d/Makefile.inc b/src/mainboard/asus/p2b-d/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-d/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/early_init.c similarity index 94% rename from src/mainboard/asus/p2b-d/romstage.c rename to src/mainboard/asus/p2b-d/early_init.c index 7fad06b..172ee95 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/early_init.c @@ -15,4 +15,4 @@ */ /* Shares romstage with P2B-DS */ -#include "../p2b-ds/romstage.c" +#include "../p2b-ds/early_init.c" diff --git a/src/mainboard/asus/p2b-ds/Makefile.inc b/src/mainboard/asus/p2b-ds/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-ds/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/early_init.c similarity index 91% rename from src/mainboard/asus/p2b-ds/romstage.c rename to src/mainboard/asus/p2b-ds/early_init.c index 5b3a30b..248cb21 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/early_init.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <device/pci_def.h> +#include <bootblock_common.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> @@ -25,16 +25,20 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } +#endif void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); diff --git a/src/mainboard/asus/p2b-f/Makefile.inc b/src/mainboard/asus/p2b-f/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-f/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/early_init.c similarity index 94% rename from src/mainboard/asus/p2b-f/romstage.c rename to src/mainboard/asus/p2b-f/early_init.c index 31a100c..b61a318 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/early_init.c @@ -15,4 +15,4 @@ */ /* Shares romstage with the better supported P2B-LS sibling. */ -#include "../p2b-ls/romstage.c" +#include "../p2b-ls/early_init.c" diff --git a/src/mainboard/asus/p2b-ls/Makefile.inc b/src/mainboard/asus/p2b-ls/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-ls/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/early_init.c similarity index 92% rename from src/mainboard/asus/p2b-ls/romstage.c rename to src/mainboard/asus/p2b-ls/early_init.c index f933c77..ef7d3d8 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/early_init.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <device/pci_def.h> +#include <bootblock_common.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> @@ -26,6 +26,12 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); @@ -33,10 +39,8 @@ void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); } +#endif diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/early_init.c similarity index 91% rename from src/mainboard/asus/p2b/romstage.c rename to src/mainboard/asus/p2b/early_init.c index 1d7c928..69450de 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/early_init.c @@ -14,8 +14,7 @@ * GNU General Public License for more details. */ -#include <device/pci_def.h> -#include <console/console.h> +#include <bootblock_common.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> @@ -25,16 +24,20 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } +#endif void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); diff --git a/src/mainboard/asus/p3b-f/Makefile.inc b/src/mainboard/asus/p3b-f/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p3b-f/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/early_init.c similarity index 95% rename from src/mainboard/asus/p3b-f/romstage.c rename to src/mainboard/asus/p3b-f/early_init.c index 8fc135d..8524098 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/early_init.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <arch/io.h> -#include <device/pci_def.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> @@ -28,10 +28,17 @@ /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } +#endif /* * ASUS P3B-F specific SPD enable magic. @@ -66,9 +73,6 @@ void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); enable_pm(); diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 01154da..45cdd9c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -18,7 +18,6 @@ select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select UDELAY_IO - select NO_BOOTBLOCK_CONSOLE config SDRAMPWR_4DIMM bool diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87e5eb93c15a72f790739eff8395e7eecbf1eb04 Gerrit-Change-Number: 36775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mb/*/*/gpio: Remove null-initialized members
by Peter Lemenkov (Code Review) 27 Mar '20

27 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35900 ) Change subject: mb/*/*/gpio: Remove null-initialized members ...................................................................... mb/*/*/gpio: Remove null-initialized members Made with this oneliner: $ find src/mainboard/ -type f -name gpio.c -print -exec sed -i -e '/^\s*.gpio[0-9]\+\s*=\s*$GPIO_MODE_NATIVE\|GPIO_DIR_OUTPUT\|GPIO_NO_INVERT\|GPIO_LEVEL_LOW\|GPIO_NO_BLINK\|GPIO_RESET_PWROK$\s*$/d' {} \; It didn't touch lines with comments. Change-Id: I2799293585bcfcf41c93a9dbe358cd806f9374f5 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/apple/macbook21/gpio.c M src/mainboard/apple/macbookair4_2/gpio.c M src/mainboard/asrock/b75pro3-m/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c M src/mainboard/asrock/h81m-hds/gpio.c M src/mainboard/asus/h61m-cs/gpio.c M src/mainboard/asus/maximus_iv_gene-z/gpio.c M src/mainboard/asus/p5gc-mx/gpio.c M src/mainboard/asus/p5qc/gpio.c M src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c M src/mainboard/asus/p8h61-m_lx/gpio.c M src/mainboard/asus/p8h61-m_pro/gpio.c M src/mainboard/asus/p8z77-m_pro/gpio.c M src/mainboard/compulab/intense_pc/gpio.c M src/mainboard/foxconn/d41s/gpio.c M src/mainboard/foxconn/g41s-k/gpio.c M src/mainboard/getac/p470/gpio.c M src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c M src/mainboard/gigabyte/ga-g41m-es2l/gpio.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c M src/mainboard/google/link/gpio.c M src/mainboard/google/parrot/gpio.c M src/mainboard/google/stout/gpio.c M src/mainboard/hp/2570p/gpio.c M src/mainboard/hp/2760p/gpio.c M src/mainboard/hp/8460p/gpio.c M src/mainboard/hp/8470p/gpio.c M src/mainboard/hp/8770w/gpio.c M src/mainboard/hp/compaq_8200_elite_sff/gpio.c M src/mainboard/hp/folio_9470m/gpio.c M src/mainboard/hp/revolve_810_g1/gpio.c M src/mainboard/hp/z220_sff_workstation/gpio.c M src/mainboard/ibase/mb899/gpio.c M src/mainboard/intel/d510mo/gpio.c M src/mainboard/intel/d945gclf/gpio.c M src/mainboard/intel/dcp847ske/gpio.c M src/mainboard/intel/dg41wv/gpio.c M src/mainboard/intel/dg43gt/gpio.c M src/mainboard/kontron/986lcd-m/gpio.c M src/mainboard/lenovo/l520/gpio.c M src/mainboard/lenovo/s230u/gpio.c M src/mainboard/lenovo/t400/variants/r500/gpio.c M src/mainboard/lenovo/t400/variants/t400/gpio.c M src/mainboard/lenovo/t420/gpio.c M src/mainboard/lenovo/t420s/gpio.c M src/mainboard/lenovo/t430s/variants/t430s/gpio.c M src/mainboard/lenovo/t430s/variants/t431s/gpio.c M src/mainboard/lenovo/t520/variants/t520/gpio.c M src/mainboard/lenovo/t520/variants/w520/gpio.c M src/mainboard/lenovo/t530/variants/t530/gpio.c M src/mainboard/lenovo/t530/variants/w530/gpio.c M src/mainboard/lenovo/t60/gpio.c M src/mainboard/lenovo/thinkcentre_a58/gpio.c M src/mainboard/lenovo/x131e/gpio.c M src/mainboard/lenovo/x1_carbon_gen1/gpio.c M src/mainboard/lenovo/x200/gpio.c M src/mainboard/lenovo/x201/gpio.c M src/mainboard/lenovo/x220/variants/x1/gpio.c M src/mainboard/lenovo/x220/variants/x220/gpio.c M src/mainboard/lenovo/x230/gpio.c M src/mainboard/lenovo/x60/gpio.c M src/mainboard/msi/ms7707/gpio.c M src/mainboard/packardbell/ms2290/gpio.c M src/mainboard/roda/rk886ex/gpio.c M src/mainboard/roda/rk9/gpio.c M src/mainboard/roda/rv11/gpio.c M src/mainboard/samsung/lumpy/gpio.c M src/mainboard/samsung/stumpy/gpio.c M src/mainboard/sapphire/pureplatinumh61/gpio.c M src/mainboard/supermicro/x10slm-f/gpio.c 79 files changed, 0 insertions(+), 4,228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35900/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2799293585bcfcf41c93a9dbe358cd806f9374f5 Gerrit-Change-Number: 35900 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by Mike Banon (Code Review) 27 Mar '20

27 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33874 Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply two changes CB:31448 and CB:31450 to add the discrete GPU support for AMD Lenovo G505S. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2452a75d425f8f647e81314111c462d1195d595d --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33874/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..aca4adb --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < "./b7d4266.diff" +### diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..6137cc4 --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_dgpu_my.txt" +sha256sum "./8e35cfe.diff" > "./sha256sums_dgpu_my.txt" +sha256sum "./b7d4266.diff" >> "./sha256sums_dgpu_my.txt" +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" + exit 1 +fi +# diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..e0d4a2a --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +rm -f "./8e35cfe.diff" +wget "https://review.coreboot.org/changes/31448/revisions/17/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +rm -f "./b7d4266.diff" +wget "https://review.coreboot.org/changes/31450/revisions/12/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b7d4266.diff" +### diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b607b61 --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,2 @@ +284cb0908c498c730dd8ed994c65ffd186d1dd34b4bc3432c9e7ccf7f40313e2 ./8e35cfe.diff +0edfa4f1bb2310220f0d6be2228f0be15d2ab0256e63fa1ed6fecc1650e1f938 ./b7d4266.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2452a75d425f8f647e81314111c462d1195d595d Gerrit-Change-Number: 33874 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: mb/google/sarien: Modify Melfas touchscreen reset delay
by Ivy Jian (Code Review) 27 Mar '20

27 Mar '20

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34162 ) Change subject: mb/google/sarien: Modify Melfas touchscreen reset delay ...................................................................... mb/google/sarien: Modify Melfas touchscreen reset delay Modify reset_delay_ms as 115ms to waiting for Melfas device I2C interface ready after touch fw AU and rebind driver. BUG=b:136560969 BRANCH=sarien TEST=Touchscreen works fine after touch FW auto updated. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34162/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849..53189ce 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -343,7 +343,7 @@ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "reset_delay_ms" = "115" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/34162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Gerrit-Change-Number: 34162 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 3

Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503 Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ...................................................................... drivers/intel/gma: Add `new-pch.asl` for Skylake+ This should work as `pch.asl` equivalent for Skylake and later platforms. Untested. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1 diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Gerrit-Change-Number: 31503 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: vendorcode/secunet: Add driver to read DMI info from I2C EEPROM
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36298 ) Change subject: vendorcode/secunet: Add driver to read DMI info from I2C EEPROM ...................................................................... vendorcode/secunet: Add driver to read DMI info from I2C EEPROM Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/vendorcode/Makefile.inc A src/vendorcode/secunet/Kconfig A src/vendorcode/secunet/Makefile.inc A src/vendorcode/secunet/dmi/Makefile.inc A src/vendorcode/secunet/dmi/eeprom.h A src/vendorcode/secunet/dmi/smbios.c 6 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36298/1 diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 8ccb0d0..55c2bb1 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan +subdirs-y += secunet diff --git a/src/vendorcode/secunet/Kconfig b/src/vendorcode/secunet/Kconfig new file mode 100644 index 0000000..7e83f90 --- /dev/null +++ b/src/vendorcode/secunet/Kconfig @@ -0,0 +1,3 @@ +config SECUNET_DMI + bool + select SMBIOS_PROVIDED_BY_MOBO diff --git a/src/vendorcode/secunet/Makefile.inc b/src/vendorcode/secunet/Makefile.inc new file mode 100644 index 0000000..15d7360 --- /dev/null +++ b/src/vendorcode/secunet/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SECUNET_DMI) += dmi diff --git a/src/vendorcode/secunet/dmi/Makefile.inc b/src/vendorcode/secunet/dmi/Makefile.inc new file mode 100644 index 0000000..90da971 --- /dev/null +++ b/src/vendorcode/secunet/dmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += smbios.c diff --git a/src/vendorcode/secunet/dmi/eeprom.h b/src/vendorcode/secunet/dmi/eeprom.h new file mode 100644 index 0000000..c4cdd41 --- /dev/null +++ b/src/vendorcode/secunet/dmi/eeprom.h @@ -0,0 +1,62 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SECUNET_DMI_EEPROM_H +#define _SECUNET_DMI_EEPROM_H + +#include <stdint.h> + +enum bx26_strings { + BOARD_MATNR, + BOARD_SERIAL_NUMBER, + BOARD_VERSION, + BOARD_MCTRL_FW_VERSION, + BOARD_CCR_FW_VERSION, + BOARD_NIC_FW_VERSION, + BOARD_LP_VERSION, + BOARD_VERSION_ID, + + SYSTEM_PRODUCT_NAME, + SYSTEM_VERSION, + SYSTEM_SERIAL_NUMBER, + SYSTEM_UUID, + SYSTEM_MANUFACTURER, + SYSTEM_PRODUCTION_DATE, + SYSTEM_MLFB, + SYSTEM_MATNR, +}; + +struct bx26_location { + uint16_t offset; + uint16_t length; +}; + +static const struct bx26_location bx26_locations[] = { + [BOARD_MATNR] = { 0x0000, 0x20 }, + [BOARD_SERIAL_NUMBER] = { 0x0020, 0x20 }, + [BOARD_VERSION] = { 0x0040, 0x20 }, + [BOARD_MCTRL_FW_VERSION] = { 0x0060, 0x20 }, + [BOARD_CCR_FW_VERSION] = { 0x0080, 0x20 }, + [BOARD_NIC_FW_VERSION] = { 0x00a0, 0x20 }, + [BOARD_LP_VERSION] = { 0x00c0, 0x20 }, + [BOARD_VERSION_ID] = { 0x0100, 0x20 }, + + [SYSTEM_PRODUCT_NAME] = { 0x4000, 0x20 }, + [SYSTEM_VERSION] = { 0x4040, 0x10 }, + [SYSTEM_SERIAL_NUMBER] = { 0x4060, 0x10 }, + [SYSTEM_UUID] = { 0x4080, 0x24 }, + [SYSTEM_MANUFACTURER] = { 0x40c0, 0x20 }, + [SYSTEM_PRODUCTION_DATE] = { 0x4100, 0x20 }, + [SYSTEM_MLFB] = { 0x4140, 0x20 }, + [SYSTEM_MATNR] = { 0x4180, 0x20 }, +}; + +#endif diff --git a/src/vendorcode/secunet/dmi/smbios.c b/src/vendorcode/secunet/dmi/smbios.c new file mode 100644 index 0000000..c299516d --- /dev/null +++ b/src/vendorcode/secunet/dmi/smbios.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <ctype.h> +#include <commonlib/helpers.h> +#include <uuid.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> +#include <smbios.h> + +#include "eeprom.h" + +#define MAX_STRING_LENGTH 256 + +static struct device *eeprom; + +static const char *eeprom_read_string(const enum bx26_strings idx) +{ + static char str[MAX_STRING_LENGTH + 1]; + + if (!eeprom) { + printk(BIOS_WARNING, "DMI: Serial EEPROM not found\n"); + str[0] = '\0'; + return str; + } + + const size_t offset = bx26_locations[idx].offset; + const size_t length = MIN(bx26_locations[idx].length, MAX_STRING_LENGTH); + + if (i2c_dev_read_at16(eeprom, (u8 *)str, length, offset) != length) { + printk(BIOS_WARNING, "DMI: Failed to read serial EEPROM\n"); + str[0] = '\0'; + } else { + unsigned int i; + /* Terminate at first non-printable character. */ + for (i = 0; i < length; ++i) { + if (!isprint(str[i])) + break; + } + str[i] = '\0'; + } + + return str; +} + +const char *smbios_system_manufacturer(void) +{ + return eeprom_read_string(SYSTEM_MANUFACTURER); +} + +const char *smbios_system_product_name(void) +{ + return eeprom_read_string(SYSTEM_PRODUCT_NAME); +} + +const char *smbios_system_serial_number(void) +{ + return eeprom_read_string(SYSTEM_SERIAL_NUMBER); +} + +const char *smbios_system_version(void) +{ + return eeprom_read_string(SYSTEM_VERSION); +} + +void smbios_system_set_uuid(u8 *const uuid) +{ + if (parse_uuid(uuid, eeprom_read_string(SYSTEM_UUID))) { + printk(BIOS_WARNING, "DMI: Cannot parse UUID\n"); + memset(uuid, 0x00, UUID_LEN); + } +} + +const char *smbios_mainboard_serial_number(void) +{ + return eeprom_read_string(BOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + return eeprom_read_string(BOARD_VERSION); +} + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_I2C || (dev->path.i2c.device & 0xf0) != 0x50) + return; + eeprom = dev; +} + +struct chip_operations vendorcode_secunet_dmi_ops = { + CHIP_NAME("secunet DMI") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Gerrit-Change-Number: 36298 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/skylake: Add Lewisburg PCH GPIOs support
by Maxim Polyakov (Code Review) 23 Mar '20

23 Mar '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35031 ) Change subject: soc/intel/skylake: Add Lewisburg PCH GPIOs support ...................................................................... soc/intel/skylake: Add Lewisburg PCH GPIOs support The pin layout in this patch corresponds to the driver in the linux kernel for Lewisburg PCH GPIO hardware [1] [1] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h A src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h M src/soc/intel/skylake/include/soc/pcr_ids.h 5 files changed, 440 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35031/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 13c1517..34fd97c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -175,6 +175,12 @@ help Choose this option if you have a PCH-H chipset. +config WELISBURG_SOC_PCH_H + bool + default n + help + Choose this option if you have the Lewisburg C62x PCH chipset. + config NHLT_DMIC_2CH bool default n diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..0130936 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -36,6 +36,9 @@ static const struct pad_group skl_community_com0_groups[] = { INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ +#if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */ +#endif }; static const struct pad_group skl_community_com1_groups[] = { @@ -48,19 +51,38 @@ INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */ #else INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ +# if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ +# else INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */ +# endif #endif }; static const struct pad_group skl_community_com3_groups[] = { #if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +#elif CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_I0, GPP_I0, RCOMP_3P3), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */ #endif }; +#if CONFIG(WELISBURG_SOC_PCH_H) +static const struct pad_group skl_community_com4_groups[] = { + INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */ + INTEL_GPP(GPP_J0, GPP_K0, RCOMP_1P8_3P3), /* GPP G */ +}; + +static const struct pad_group skl_community_com5_groups[] = { + INTEL_GPP(GPP_J0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_J0, GPP_H0, GPP_H23), /* GPP H */ + INTEL_GPP(GPP_J0, GPP_L2, GPP_L19), /* GPP L */ +}; +#endif + static const struct pad_group skl_community_com2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ }; @@ -69,7 +91,11 @@ { .port = PID_GPIOCOM0, .first_pad = GPP_A0, +#if CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_F23, +#else .last_pad = GPP_B23, +#endif .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -89,6 +115,8 @@ .first_pad = GPP_C0, #if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, +#elif CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_E12, #else .last_pad = GPP_E23, #endif @@ -108,7 +136,7 @@ .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if CONFIG(SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -130,6 +158,44 @@ .groups = skl_community_com3_groups, .num_groups = ARRAY_SIZE(skl_community_com3_groups), }, { +#if CONFIG(WELISBURG_SOC_PCH_H) + .port = PID_GPIOCOM4, + .first_pad = GPP_J0, + .last_pad = GPP_K10, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com4_groups, + .num_groups = ARRAY_SIZE(skl_community_com4_groups), + }, { + .port = PID_GPIOCOM4, + .first_pad = GPP_G0, + .last_pad = GPP_L19, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com5_groups, + .num_groups = ARRAY_SIZE(skl_community_com5_groups), + }, { +#endif .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -161,17 +227,27 @@ static const struct pmc_to_gpio_route routes[] = { { GPP_A, GPP_A}, { GPP_B, GPP_B}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_F, GPP_F}, +#endif { GPP_C, GPP_C}, { GPP_D, GPP_D}, { GPP_E, GPP_E}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_I, GPP_I}, + { GPP_J, GPP_J}, + { GPP_K, GPP_K}, +#else { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if CONFIG(SKYLAKE_SOC_PCH_H) +# if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, +# endif #endif { GPD, GPD}, }; + *num = ARRAY_SIZE(routes); return routes; } @@ -179,7 +255,7 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (CONFIG(SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..0285989 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -20,6 +20,8 @@ #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> +#elif CONFIG(WELISBURG_SOC_PCH_H) +# include <soc/gpio_wlb_pch_defs.h> #else # include <soc/gpio_soc_defs.h> #endif @@ -33,6 +35,22 @@ #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#if CONFIG(WELISBURG_SOC_PCH_H) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) +#endif + +#if CONFIG(WELISBURG_SOC_PCH_H) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + +#else #define NUM_GPI_STATUS_REGS \ ((NUM_GPIO_COM0_GPI_REGS) +\ @@ -218,6 +236,8 @@ #define GPD10_IRQ 0x5a #define GPD11_IRQ 0x5b +#endif + /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 diff --git a/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h new file mode 100644 index 0000000..636837c --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_WLB_PCH_DEFS_H_ +#define _SOC_GPIO_WLB_PCH_DEFS_H_ + +/* GPIO Community 0 */ +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_F 0x2 +/* GPIO Community 1 */ +#define GPP_C 0x3 +#define GPP_D 0x4 +#define GPP_E 0x5 +/* GPIO Community 3 */ +#define GPP_I 0x6 +/* GPIO Community 4 */ +#define GPP_J 0x7 +#define GPP_K 0x8 +/* GPIO Community 5 */ +#define GPP_G 0x9 +#define GPP_H 0xA +#define GPP_L 0xB +/* GPIO Community 2 */ +#define GPD 0xC + +#define GPIO_NUM_GROUPS 13 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group F */ +#define GPP_F0 48 +#define GPP_F1 49 +#define GPP_F2 50 +#define GPP_F3 51 +#define GPP_F4 52 +#define GPP_F5 53 +#define GPP_F6 54 +#define GPP_F7 55 +#define GPP_F8 56 +#define GPP_F9 57 +#define GPP_F10 58 +#define GPP_F11 59 +#define GPP_F12 60 +#define GPP_F13 61 +#define GPP_F14 62 +#define GPP_F15 63 +#define GPP_F16 64 +#define GPP_F17 65 +#define GPP_F18 66 +#define GPP_F19 67 +#define GPP_F20 68 +#define GPP_F21 69 +#define GPP_F22 70 +#define GPP_F23 71 + +#define NUM_GPIO_COM0_PADS (GPP_F23 - GPP_A0 + 1) + +/* Group C */ +#define GPP_C0 72 +#define GPP_C1 73 +#define GPP_C2 74 +#define GPP_C3 75 +#define GPP_C4 76 +#define GPP_C5 77 +#define GPP_C6 78 +#define GPP_C7 79 +#define GPP_C8 80 +#define GPP_C9 81 +#define GPP_C10 82 +#define GPP_C11 83 +#define GPP_C12 84 +#define GPP_C13 85 +#define GPP_C14 86 +#define GPP_C15 87 +#define GPP_C16 88 +#define GPP_C17 89 +#define GPP_C18 90 +#define GPP_C19 91 +#define GPP_C20 92 +#define GPP_C21 93 +#define GPP_C22 94 +#define GPP_C23 95 +/* Group D */ +#define GPP_D0 96 +#define GPP_D1 97 +#define GPP_D2 98 +#define GPP_D3 99 +#define GPP_D4 100 +#define GPP_D5 101 +#define GPP_D6 102 +#define GPP_D7 103 +#define GPP_D8 104 +#define GPP_D9 105 +#define GPP_D10 106 +#define GPP_D11 107 +#define GPP_D12 108 +#define GPP_D13 109 +#define GPP_D14 110 +#define GPP_D15 111 +#define GPP_D16 112 +#define GPP_D17 113 +#define GPP_D18 114 +#define GPP_D19 115 +#define GPP_D20 116 +#define GPP_D21 117 +#define GPP_D22 118 +#define GPP_D23 119 +/* Group E */ +#define GPP_E0 120 +#define GPP_E1 121 +#define GPP_E2 122 +#define GPP_E3 123 +#define GPP_E4 124 +#define GPP_E5 125 +#define GPP_E6 126 +#define GPP_E7 127 +#define GPP_E8 128 +#define GPP_E9 129 +#define GPP_E10 130 +#define GPP_E11 131 +#define GPP_E12 132 + +#define NUM_GPIO_COM1_PADS (GPP_E12 - GPP_C0 + 1) + +/* Group I */ +#define GPP_I0 133 +#define GPP_I1 134 +#define GPP_I2 135 +#define GPP_I3 136 +#define GPP_I4 137 +#define GPP_I5 138 +#define GPP_I6 139 +#define GPP_I7 140 +#define GPP_I8 141 +#define GPP_I9 142 +#define GPP_I10 143 +#define RCOMP_3P3 144 + +#define NUM_GPIO_COM3_PADS (RCOMP_3P3 - GPP_I0 + 1) + +/* Group J */ +#define GPP_J0 145 +#define GPP_J1 146 +#define GPP_J2 147 +#define GPP_J3 148 +#define GPP_J4 149 +#define GPP_J5 150 +#define GPP_J6 151 +#define GPP_J7 152 +#define GPP_J8 153 +#define GPP_J9 154 +#define GPP_J10 155 +#define GPP_J11 156 +#define GPP_J12 157 +#define GPP_J13 158 +#define GPP_J14 159 +#define GPP_J15 160 +#define GPP_J16 161 +#define GPP_J17 162 +#define GPP_J18 163 +#define GPP_J19 164 +#define GPP_J20 165 +#define GPP_J21 166 +#define GPP_J22 167 +#define GPP_J23 168 +/* Group K */ +#define GPP_K0 169 +#define GPP_K1 170 +#define GPP_K2 171 +#define GPP_K3 172 +#define GPP_K4 173 +#define GPP_K5 174 +#define GPP_K6 175 +#define GPP_K7 176 +#define GPP_K8 177 +#define GPP_K9 178 +#define GPP_K10 179 + +#define RCOMP_1P8_3P3 180 + +#define NUM_GPIO_COM4_PADS (RCOMP_1P8_3P3 - GPP_J0 + 1) + +/* Group G */ +#define GPP_G0 181 +#define GPP_G1 182 +#define GPP_G2 183 +#define GPP_G3 184 +#define GPP_G4 185 +#define GPP_G5 186 +#define GPP_G6 187 +#define GPP_G7 188 +#define GPP_G8 189 +#define GPP_G9 190 +#define GPP_G10 191 +#define GPP_G11 192 +#define GPP_G12 193 +#define GPP_G13 194 +#define GPP_G14 195 +#define GPP_G15 196 +#define GPP_G16 197 +#define GPP_G17 198 +#define GPP_G18 199 +#define GPP_G19 200 +#define GPP_G20 201 +#define GPP_G21 202 +#define GPP_G22 203 +#define GPP_G23 204 +/* Group H */ +#define GPP_H0 205 +#define GPP_H1 206 +#define GPP_H2 207 +#define GPP_H3 208 +#define GPP_H4 209 +#define GPP_H5 210 +#define GPP_H6 211 +#define GPP_H7 212 +#define GPP_H8 213 +#define GPP_H9 214 +#define GPP_H10 215 +#define GPP_H11 216 +#define GPP_H12 217 +#define GPP_H13 218 +#define GPP_H14 219 +#define GPP_H15 220 +#define GPP_H16 221 +#define GPP_H17 222 +#define GPP_H18 223 +#define GPP_H19 224 +#define GPP_H20 225 +#define GPP_H21 226 +#define GPP_H22 227 +#define GPP_H23 228 +/* Group L */ +#define GPP_L2 229 +#define GPP_L3 230 +#define GPP_L4 231 +#define GPP_L5 232 +#define GPP_L6 233 +#define GPP_L7 234 +#define GPP_L8 235 +#define GPP_L9 236 +#define GPP_L10 237 +#define GPP_L11 238 +#define GPP_L12 239 +#define GPP_L13 240 +#define GPP_L14 241 +#define GPP_L15 242 +#define GPP_L16 243 +#define GPP_L17 244 +#define GPP_L18 245 +#define GPP_L19 246 + +#define NUM_GPIO_COM5_PADS (GPP_L23 - GPP_G0 + 1) + +/* Group GPD */ +#define GPD0 247 +#define GPD1 248 +#define GPD2 249 +#define GPD3 250 +#define GPD4 251 +#define GPD5 252 +#define GPD6 253 +#define GPD7 254 +#define GPD8 255 +#define GPD9 256 +#define GPD10 257 +#define GPD11 258 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#endif diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index 71affd8..1185e17 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -20,6 +20,8 @@ * Port ids */ #define PID_PSTH 0x89 +#define PID_GPIOCOM5 0x11 +#define PID_GPIOCOM4 0xAB #define PID_GPIOCOM3 0xAC #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE -- To view, visit https://review.coreboot.org/c/coreboot/+/35031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Gerrit-Change-Number: 35031 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 24

Change in coreboot[master]: sb/ibexpeak: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 20 Mar '20

20 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37116 ) Change subject: sb/ibexpeak: Use macros instead of hard-coded IDs ...................................................................... sb/ibexpeak: Use macros instead of hard-coded IDs This patch replaces hard-coded PCI IDs with macros from pci_ids.h and adds the related IDs to it. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 322170 Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/include/device/pci_ids.h M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c 8 files changed, 50 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37116/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f60..d1d26fe 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2675,6 +2675,19 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */ +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_QM57 0x3b07 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_HM55 0x3b09 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1 0x3b28 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI 0x3b29 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2 0x3b2e +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_1 0x3b34 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_2 0x3b3c +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_AUDIO 0x3b56 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_HECI1 0x3b64 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_THERMAL 0x3b32 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5b38ea7..c36ef5e 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -326,7 +326,12 @@ .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c20, + 0x1e20, + PCI_DEVICE_ID_INTEL_IBEXPEAK_AUDIO, + 0 +}; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..c6a73b2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -779,7 +779,11 @@ }; -static const unsigned short pci_device_ids[] = { 0x3b07, 0x3b09, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_QM57, + PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_HM55, + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..e9dc908 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -615,8 +615,11 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c3a, + PCI_DEVICE_ID_INTEL_IBEXPEAK_HECI1, + 0 +}; static const struct pci_driver intel_me __pci_driver = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..4c00e8e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -247,7 +247,12 @@ .ops_pci = &sata_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b28, 0x3b29, 0x3b2e, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1, + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI, + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2, + 0 +}; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index dd3abfe..589b349 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -98,7 +98,12 @@ .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c22, + 0x1e22, + PCI_DEVICE_ID_INTEL_IBEXPEAK_SMBUS, + 0 +}; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 597d388..540eb6f 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -57,7 +57,10 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b32, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_THERMAL, + 0 +}; static const struct pci_driver pch_thermal __pci_driver = { .ops = &thermal_ops, diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index d31fd70..9e8d19c 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -98,7 +98,11 @@ .ops_pci = &lops_pci, }; -static const unsigned short pci_device_ids[] = { 0x3b34, 0x3b3c, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_1, + PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_2, + 0 +}; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/37116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Gerrit-Change-Number: 37116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: ec/lenovo/h8: Add a config to indicate whether dock init is needed
by Bill XIE (Code Review) 20 Mar '20

20 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36385 ) Change subject: ec/lenovo/h8: Add a config to indicate whether dock init is needed ...................................................................... ec/lenovo/h8: Add a config to indicate whether dock init is needed Discussed in CB:36093, in the past many lenovo boards need to declare empty h8_mainboard_init_dock() to satisfy h8.c. Since H8_DOCK_EARLY_INIT has a different meaning, it had better add another config to indicate whether dock init is needed, thus eliminating the necessity to declare empty h8_mainboard_init_dock() in the future. Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/h8.c M src/mainboard/lenovo/l520/mainboard.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430/mainboard.c M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc D src/mainboard/lenovo/x200/variants/x301/dock.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/mainboard.c M src/mainboard/lenovo/x60/Kconfig 21 files changed, 16 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36385/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f3df56a..5cc26d6 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,7 +44,14 @@ bool default n -endif +config H8_NEED_DOCK_INIT + bool "Dock init during boot is necessary" + +if H8_NEED_DOCK_INIT config H8_DOCK_EARLY_INIT bool + +endif # H8_NEED_DOCK_INIT + +endif # EC_LENOVO_H8 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3a99b52..679b96c 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -354,7 +354,7 @@ h8_set_audio_mute(0); -#if !CONFIG(H8_DOCK_EARLY_INIT) +#if CONFIG(H8_NEED_DOCK_INIT) && !CONFIG(H8_DOCK_EARLY_INIT) h8_mainboard_init_dock(); #endif } diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index db695b1..88c7884 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2caf1d3..171cb29 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -10,6 +10,7 @@ select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..600b8a6 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -21,6 +21,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select MAINBOARD_HAS_LIBGFXINIT config VBOOT diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index 99a5bd8..a86a90e 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -17,10 +17,6 @@ #include <drivers/intel/gma/int15.h> #include <ec/lenovo/h8/h8.h> -void h8_mainboard_init_dock (void) -{ -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index bd4292a..6825b6b 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -28,10 +28,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index bc8fa29..86351c8 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -19,6 +19,7 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT select I945_LVDS diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca..50b4de1 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -24,10 +24,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index 64cc15b..bc6dcb1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -29,8 +29,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - -/* TODO: this device doesnt have a dock */ -void h8_mainboard_init_dock (void) -{ -} diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index fab8a88..8cab040 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -23,6 +23,7 @@ select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select H8_NEED_DOCK_INIT if BOARD_LENOVO_X200 config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index f6c2c0c..7e38a78 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -ramstage-y += variants/$(VARIANT_DIR)/dock.c +ramstage-$(CONFIG_BOARD_LENOVO_X200) += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c deleted file mode 100644 index f8a2dc4..0000000 --- a/src/mainboard/lenovo/x200/variants/x301/dock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/h8.h> - -void h8_mainboard_init_dock(void) -{ -} diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index e40c0d3..21edec79 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index e3aabf3..27c953b 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select I945_LVDS -- To view, visit https://review.coreboot.org/c/coreboot/+/36385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Gerrit-Change-Number: 36385 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2019