coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: soc/intel/common/ebda: Drop code
by Michael Niewöhner (Code Review) 04 Nov '19

04 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36362 ) Change subject: soc/intel/common/ebda: Drop code ...................................................................... Patch Set 21: > Patch Set 21: > > hmmm, common/systemagent/memmap.c still calls this? the skl,cnl,icl patches got dropped, but they are needed -- To view, visit https://review.coreboot.org/c/coreboot/+/36362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Gerrit-Change-Number: 36362 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Nov 2019 20:01:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/ebda: Drop code
by Nico Huber (Code Review) 04 Nov '19

04 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36362 ) Change subject: soc/intel/common/ebda: Drop code ...................................................................... Patch Set 21: hmmm, common/systemagent/memmap.c still calls this? -- To view, visit https://review.coreboot.org/c/coreboot/+/36362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Gerrit-Change-Number: 36362 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Nov 2019 19:53:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include: introduce update* for mmio operations
by Aaron Durbin (Code Review) 04 Nov '19

04 Nov '19

1 0

Change in coreboot[master]: include: introduce update* for mmio operations
by Nico Huber (Code Review) 04 Nov '19

04 Nov '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36596 ) Change subject: include: introduce update* for mmio operations ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36596/2/src/include/mmio.h File src/include/mmio.h: https://review.coreboot.org/c/coreboot/+/36596/2/src/include/mmio.h@13 PS2, Line 13: > > Should we allow users to expect the indirect inclusion of `arch/mmio.h`? […] Well, this is not the best example. We know that it makes no sense to implemented update*() differently. But generally, when an implementation would change, indirect includes can break. Hence, one shouldn't make assumptions about them unless there is a clear definition... like "mmio.h provides read/write*()". Also, I wrote this mostly because I know some folks try to keep includes clean. And a comment here could save us any future discussion about it :) -- To view, visit https://review.coreboot.org/c/coreboot/+/36596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f188d586c09ee9f1e17290563f68970603204fb Gerrit-Change-Number: 36596 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Nov 2019 19:50:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/ebda: Drop code
by Michael Niewöhner (Code Review) 04 Nov '19

04 Nov '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36362 ) Change subject: soc/intel/common/ebda: Drop code ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Gerrit-Change-Number: 36362 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Nov 2019 19:47:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/ebda: Drop code
by Arthur Heymans (Code Review) 04 Nov '19

04 Nov '19

Hello Patrick Rudolph, Michael Niewöhner, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36362 to look at the new patch set (#21). Change subject: soc/intel/common/ebda: Drop code ...................................................................... soc/intel/common/ebda: Drop code There is no need to use EBDA to pass cbmem_top from romstage to later stages. Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/soc/intel/cannonlake/include/soc/ebda.h D src/soc/intel/common/block/ebda/Kconfig D src/soc/intel/common/block/ebda/Makefile.inc D src/soc/intel/common/block/ebda/ebda.c D src/soc/intel/common/block/include/intelblocks/ebda.h M src/soc/intel/common/block/systemagent/memmap.c D src/soc/intel/icelake/include/soc/ebda.h D src/soc/intel/skylake/include/soc/ebda.h 8 files changed, 2 insertions(+), 181 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/36362/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/36362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Gerrit-Change-Number: 36362 Gerrit-PatchSet: 21 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: google/auron: hook up libgfxinit
by Matt DeVillier (Code Review) 04 Nov '19

04 Nov '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36107 ) Change subject: google/auron: hook up libgfxinit ...................................................................... google/auron: hook up libgfxinit Test: build/boot lulu variant with libgfxinit Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/Makefile.inc A src/mainboard/google/auron/gma-mainboard.ads 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/36107/1 diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 13348a3..b4ef3a8 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -9,6 +9,7 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 6b1de05..ca42470 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -35,3 +35,5 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/auron/gma-mainboard.ads b/src/mainboard/google/auron/gma-mainboard.ads new file mode 100644 index 0000000..d110261 --- /dev/null +++ b/src/mainboard/google/auron/gma-mainboard.ads @@ -0,0 +1,30 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + HDMI1, + DP1, + DP2, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/36107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20 Gerrit-Change-Number: 36107 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: include: introduce update* for mmio operations
by Aaron Durbin (Code Review) 04 Nov '19

04 Nov '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36596 ) Change subject: include: introduce update* for mmio operations ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/36596/2/src/include/mmio.h File src/include/mmio.h: https://review.coreboot.org/c/coreboot/+/36596/2/src/include/mmio.h@13 PS2, Line 13: > Should we allow users to expect the indirect inclusion of `arch/mmio.h`? > e.g. only include `mmio.h` and then use read32() and update32(). Why wouldn't we expect that? The update functions wouldn't work if this header was included bare without the accompanying #include for readX/writeX(). > > If so, please leave a comment here that `mmio.h` provides read*() and > write*() as well. https://review.coreboot.org/c/coreboot/+/36596/1/src/include/mmio.h File src/include/mmio.h: https://review.coreboot.org/c/coreboot/+/36596/1/src/include/mmio.h@19 PS1, Line 19: static __always_inline void update8(const volatile void *addr, uint8_t mask, uint8_t or) > For the record, I'm ok with the short names. It seems obvious what these […] now I hate readX/writeX being bare w/o a namespace. :) But if we want the short form I can't argue against readX/writeX not having one for mmio but of course everything else needs a prefix because of the namespace collisions. FWIW, I don't think about things an obviousness of what they do in their implementation. It's legibility at the call sites -- helps w/ reading code and reviewing patchsets, imo. -- To view, visit https://review.coreboot.org/c/coreboot/+/36596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f188d586c09ee9f1e17290563f68970603204fb Gerrit-Change-Number: 36596 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Nov 2019 19:32:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/ebda: Drop code
by Arthur Heymans (Code Review) 04 Nov '19

04 Nov '19

Hello Patrick Rudolph, Michael Niewöhner, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36362 to look at the new patch set (#20). Change subject: soc/intel/common/ebda: Drop code ...................................................................... soc/intel/common/ebda: Drop code Using ebda to pass romstage information to ramstage is unused now. Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/soc/intel/cannonlake/include/soc/ebda.h D src/soc/intel/common/block/ebda/Kconfig D src/soc/intel/common/block/ebda/Makefile.inc D src/soc/intel/common/block/ebda/ebda.c D src/soc/intel/common/block/include/intelblocks/ebda.h D src/soc/intel/icelake/include/soc/ebda.h D src/soc/intel/skylake/include/soc/ebda.h 7 files changed, 0 insertions(+), 210 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/36362/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/36362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Gerrit-Change-Number: 36362 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/sgx: make SGX a Kconfig option
by Michael Niewöhner (Code Review) 04 Nov '19

04 Nov '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35799 ) Change subject: soc/intel/sgx: make SGX a Kconfig option ...................................................................... soc/intel/sgx: make SGX a Kconfig option This removes the devicetree parameter sgx_enable and add a Kconfig option instead, as the devictree is not made for user-choosable options. Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/Kconfig M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/cpu.c 10 files changed, 19 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35799/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index d3d0b00..9277f08 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -97,8 +97,6 @@ # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" - register "sgx_enable" = "1" - # PRMRR size options # 0x02000000 - 32MiB # 0x04000000 - 64MiB diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index a5ff0c5..0c42edd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -17,8 +17,6 @@ register "Device4Enable" = "1" register "SaGv" = "SaGv_Disabled" - # Disable SGX - register "sgx_enable" = "0" # SGX is broken in coreboot register "PrmrrSize" = "128 * MiB" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 85cfff9..3fdc646 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -145,12 +145,6 @@ * 0x08000000 - 128MiB */ uint32_t PrmrrSize; - /* Enable SGX feature. - * Enabling SGX feature is 2 step process, - * (1) set sgx_enable = 1 - * (2) set PrmrrSize to supported size */ - uint8_t sgx_enable; - /* Select PNP Settings. * (0) Performance, * (1) Power diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3349627..4ec714f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -293,11 +293,3 @@ /* Do nothing because MCHECK while loading microcode and enabling * IA untrusted mode takes care of necessary locking */ } - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 77711eb..5cdd43b 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,11 +35,11 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_soc(); - /* FSP allocates 2x PRMRR Size Memory for alignment */ - if (config->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) { + config = config_of_soc(); tolum -= config->PrmrrSize * 2; + } return tolum; } diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 502483f..693dd20 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -18,10 +18,6 @@ #include <soc/nvs.h> -struct sgx_param { - uint8_t enable; -}; - /* * Lock SGX memory. * CPU specific code needs to provide the implementation. @@ -40,10 +36,6 @@ */ void sgx_configure(void *unused); -/* SOC specific API to get SGX params. - * returns 0, if able to get SGX params; otherwise returns -1 */ -int soc_fill_sgx_param(struct sgx_param *sgx_param); - /* Fill GNVS data with SGX status, EPC base and length */ void sgx_fill_gnvs(global_nvs_t *gnvs); diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 0852bfb..78284fb 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -2,6 +2,12 @@ bool default n help - Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU - instructions that can be used by applications to set aside private - regions of code and data. + Intel Processor common SGX support + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + bool + depends on SOC_INTEL_COMMON_BLOCK_SGX + default n + help + Software Guard eXtension (SGX) Feature. Intel SGX is a set of new CPU instructions + that can be used by applications to set aside private regions of code and data. diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 60714d9..4567e13 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -25,9 +25,6 @@ #include <soc/pci_devs.h> #include <string.h> -static bool sgx_param_valid; -static struct sgx_param g_sgx_param; - static inline uint64_t sgx_resource(uint32_t low, uint32_t high) { uint64_t val; @@ -36,28 +33,6 @@ return val; } -static const struct sgx_param *get_sgx_param(void) -{ - if (sgx_param_valid) - return &g_sgx_param; - - memset(&g_sgx_param, 0, sizeof(g_sgx_param)); - if (soc_fill_sgx_param(&g_sgx_param) < 0) { - printk(BIOS_ERR, "SGX : Failed to get soc sgx param\n"); - return NULL; - } - sgx_param_valid = true; - printk(BIOS_INFO, "SGX : param.enable = %d\n", g_sgx_param.enable); - - return &g_sgx_param; -} - -static int soc_sgx_enabled(void) -{ - const struct sgx_param *sgx_param = get_sgx_param(); - return sgx_param ? sgx_param->enable : 0; -} - static int is_sgx_supported(void) { struct cpuid_result cpuid_regs; @@ -79,7 +54,7 @@ } prmrr_base, prmrr_mask; msr_t msr; - if (!soc_sgx_enabled() || !is_sgx_supported()) + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || !is_sgx_supported()) return; msr = rdmsr(MSR_PRMRR_PHYS_MASK); @@ -204,7 +179,7 @@ { const void *microcode_patch = intel_mp_current_microcode(); - if (!soc_sgx_enabled() || !is_sgx_supported() || !is_prmrr_set()) { + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || !is_sgx_supported() || !is_prmrr_set()) { printk(BIOS_ERR, "SGX: pre-conditions not met\n"); return; } @@ -234,7 +209,7 @@ { struct cpuid_result cpuid_regs; - if (!soc_sgx_enabled() || !is_sgx_supported()) { + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) || !is_sgx_supported()) { printk(BIOS_DEBUG, "SGX: not enabled or not supported. skip gnvs fill\n"); return; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 944315b..626d36b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -576,9 +576,6 @@ u8 SlowSlewRateForGt; u8 SlowSlewRateForSa; - /* Enable SGX feature */ - u8 sgx_enable; - /* Enable/Disable EIST * 1b - Enabled * 0b - Disabled diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5424c91..26cc533 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -455,7 +455,8 @@ enable_turbo(); /* Configure Core PRMRR for SGX. */ - prmrr_core_configure(); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + prmrr_core_configure(); } static void per_cpu_smm_trigger(void) @@ -493,7 +494,8 @@ ret |= mp_run_on_all_cpus(vmx_configure, NULL); - ret |= mp_run_on_all_cpus(sgx_configure, NULL); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) + ret |= mp_run_on_all_cpus(sgx_configure, NULL); ret |= mp_run_on_all_cpus(fc_lock_configure, NULL); @@ -559,11 +561,3 @@ wrmsr(MSR_LT_LOCK_MEMORY, msr); } } - -int soc_fill_sgx_param(struct sgx_param *sgx_param) -{ - config_t *conf = config_of_soc(); - - sgx_param->enable = conf->sgx_enable; - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Gerrit-Change-Number: 35799 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

7 117

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019