coreboot-gerrit October 2019

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Change in coreboot[master]: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35821 ) Change subject: [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table ...................................................................... [RFC]arch/x86: Only use BOOTBLOCK_NORMAL with an CMOS option table There is no explicit dependency on an option table since the reboot counter and the normal/fallback byte is at a fixed offset. I don't feel strongly about imposing this... Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35821/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 502e774..9d26692 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -255,6 +255,7 @@ bool "Always load fallback" config BOOTBLOCK_NORMAL + depends on USE_OPTION_TABLE select CONFIGURABLE_CBFS_PREFIX bool "Switch to normal if CMOS says so" -- To view, visit https://review.coreboot.org/c/coreboot/+/35821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126e71c72951d11960f5d27d25eaa838854057d Gerrit-Change-Number: 35821 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35823 ) Change subject: [RFC]arch/x86: Only allow normal and fallback cbfs prefixes ...................................................................... [RFC]arch/x86: Only allow normal and fallback cbfs prefixes Using other cbfsprefixes is errorprone: It requires a properly formatted cbfs file to be present (an error in the cbfsfile will render the system unbootable) and to correctly enter the cbfs prefix in menuconfig. Therefore remove this functionality that merely allows to use different names. Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/bootblock_normal.c 2 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35823/1 diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..5b2a615 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -48,13 +48,10 @@ config CBFS_PREFIX_NORMAL bool "normal" -config CBFS_PREFIX_DIY - bool "Define your own cbfs prefix" - endchoice config CBFS_PREFIX - string "CBFS prefix to use" if CBFS_PREFIX_DIY + string default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK default "normal" if CBFS_PREFIX_NORMAL help diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 905ecb2..c55eda2 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -16,18 +16,9 @@ #include <pc80/mc146818rtc.h> #include <halt.h> -static const char *get_fallback(const char *stagelist) -{ - while (*stagelist) - stagelist++; - return ++stagelist; -} - static void main(unsigned long bist) { u8 boot_mode; - const char *default_filenames = - "normal/romstage\0fallback/romstage"; if (boot_cpu()) { bootblock_mainboard_init(); @@ -44,20 +35,15 @@ boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - unsigned long entry; if (boot_mode) { - entry = findstage(normal_candidate); + entry = findstage("normal/romstage"); if (entry) call(entry, bist); } - entry = findstage(get_fallback(normal_candidate)); + entry = findstage("fallback/romstage"); if (entry) call(entry, bist); -- To view, visit https://review.coreboot.org/c/coreboot/+/35823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7399b144fe122badd53d518543868c6ecb14fe21 Gerrit-Change-Number: 35823 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]Makefile.inc: Add Macro to generate cbfs int files
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33353 Change subject: [WIP]Makefile.inc: Add Macro to generate cbfs int files ...................................................................... [WIP]Makefile.inc: Add Macro to generate cbfs int files Add the makefile function 'add-cbfs-int' to generate cbfs files containing a little endian integer. Adding cbfs files containing a 64 bit is usually done with cbfstool add-int, but this requires the coreboot.rom image to be already build which clutters the Makefile. Instead add a method to cleanly generate the cbfsfile containing a 64bit little endian int which integrates better with the rest of the makefile. Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33353/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..d0f47e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -788,6 +788,20 @@ $(call cbfs-add-cmd-for-region,$(1),$(2)) endef +# add-cbfs-int (little endian) +# $(call add-cbfs-int, +# integer +# cbfs-file-name) +define add-cbfs-int + $(eval tmp_int:=$(shell mktemp -u int_file.XXXX)) + $(eval $(obj)/$(tmp_int): + echo -n -e $$$$(printf "%016x" $$$$(($(1))) \ + | sed -re "s/(..)(..)(..)(..)(..)(..)(..)(..)/\\\x\8\\\x\7\\\x\6\\\x\5\\\x\4\\\x\3\\\x\2\\\x\1/") > $$@) + cbfs-files-y += $(2) + $(2)-file := $(obj)/$(tmp_int) + $(2)-type := raw +endef + # list of files to add (using their file system names, not CBFS names), # for dependencies etc. prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) @@ -1064,18 +1078,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efa..24eeba6 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -110,6 +110,18 @@ bootorder-type := raw endif +# Add SeaBIOS PS2 timeout file +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_PS2_TIMEOUT),etc/ps2-keyboard-spinup)) +endif +endif + +# Add SeaBIOS Sercon port file +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_SERCON_PORT_ADDR),etc/sercon-port)) +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/33353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Gerrit-Change-Number: 33353 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: mediatek/me8183: Refactor dsi driver as common code
by jitao shi (Code Review) 31 Mar '22

31 Mar '22

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34562 ) Change subject: WIP: mediatek/me8183: Refactor dsi driver as common code ...................................................................... WIP: mediatek/me8183: Refactor dsi driver as common code BUG=b:80501386,b:117254947 BRANCH=none TEST=build pass Change-Id: I242d7a4f75057c0a955c9284a79c385a667ce7bd --- A src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h 7 files changed, 604 insertions(+), 1,050 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34562/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c new file mode 100644 index 0000000..cf6d228 --- /dev/null +++ b/src/soc/mediatek/common/dsi.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +void dsi_write32(void *a, uint32_t v) +{ + write32(a, v); +} + +void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a, m, v); +} + +void dsi_clrbits_le32(void *a, uint32_t m) +{ + clrbits_le32(a, m); +} + +void dsi_setbits_le32(void *a, uint32_t m) +{ + setbits_le32(a, m); +} + +void mtk_dsi_reset(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_write32(&dsi0->dsi_con_ctrl, 1); + dsi_write32(&dsi0->dsi_con_ctrl, 0); +} + +void mtk_dsi_clk_hs_mode_enable(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_setbits_le32(&dsi0->dsi_phy_lccon, 1); +} + +void mtk_dsi_set_mode(u32 dsi_id, u32 mode_flags) +{ + u32 tmp_reg1 = 0; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); +} + +void mtk_dsi_rxtx_control(u32 dsi_id, u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); +} + +void mtk_dsi_start(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_clrbits_le32(&dsi0->dsi_start, 1); + dsi_setbits_le32(&dsi0->dsi_start, 1); +} + +static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) +{ + struct stopwatch sw; + u8 *tx_buf = data; + u8 cmdq_size; + u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; + struct dsi_regs *const dsi0 = getdsi_regbase(0); + + while (read32(&dsi0->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); + mdelay(20); + } + + dsi_write32(&dsi0->dsi_intsta, 0); + + if (MTK_DSI_HOST_IS_READ(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len > 2) { + cmdq_size = 1 + (len + 3) / 4; + cmdq_off = 4; + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; + reg_val = (len << 16) | (type << 8) | config; + } else { + cmdq_size = 1; + cmdq_off = 2; + cmdq_mask = CONFIG | DATA_ID; + reg_val = (type << 8) | config; + } + + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + + ((cmdq_off + i) & (0xfffffffc)), + (0xff << (((i + cmdq_off) & 3) * 8)), + tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } + + dsi_clrsetbits_le32(&dsi0->dsi_cmdq0, cmdq_mask, reg_val); + dsi_clrsetbits_le32(&dsi0->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); + mtk_dsi_start(0); + + stopwatch_init_usecs_expire(&sw, 400); + do { + intsta_0 = read32(&dsi0->dsi_intsta); + if (intsta_0 & CMD_DONE_INT_FLAG) + break; + udelay(4); + } while (!stopwatch_expired(&sw)); + + if (!(intsta_0 & CMD_DONE_INT_FLAG)) + printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); +} + +void push_table(struct lcm_init_table *init_cmd) +{ + u32 cmd, i; + u32 type; + + for (i = 0; ; i++) { + cmd = init_cmd[i].cmd; + + switch (cmd) { + case DELAY_CMD: + mdelay(init_cmd[i].len); + break; + + case END_OF_TABLE: + return; + + case INIT_DCS_CMD: + switch (init_cmd[i].len) { + case 0: + return; + + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + + case INIT_GENENIC_CMD: + default: + switch (init_cmd[i].len) { + case 0: + type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + } + } +} + diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 0ffa196..7e43138 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -82,7 +82,7 @@ ramstage-y += ../common/usb.c usb.c ramstage-y += ddp.c -ramstage-y += dsi.c +ramstage-y += ../common/dsi.c dsi.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b2279ea..23be800 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -25,71 +25,7 @@ static bool dual_dsi_mode; -static void mipi_write32(void *a, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void mipi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void mipi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void mipi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static void dsi_write32(void *a, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, +static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid) { u32 txdiv0, txdiv1; @@ -97,6 +33,7 @@ u32 reg; u32 bit_per_pixel; int i, data_rate, mipi_tx_rate; + struct mipi_tx_regs *const mipi_tx0 = getmipitx_regbase(dsi_id); reg = read32(&mipi_tx0->dsi_bg_con); @@ -111,16 +48,16 @@ mipi_write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - mipi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + dsi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - mipi_setbits_le32(&mipi_tx0->dsi_con, + dsi_setbits_le32(&mipi_tx0->dsi_con, RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + dsi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); switch (format) { case MIPI_DSI_FMT_RGB565: @@ -171,7 +108,7 @@ return -1; } - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, + dsi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); @@ -185,29 +122,47 @@ */ pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; pcw /= 13; - mipi_write32(&mipi_tx0->dsi_pll_con2, pcw); + dsi_write32(&mipi_tx0->dsi_pll_con2, pcw); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + dsi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - mipi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + dsi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - mipi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + dsi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + dsi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - mipi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); return mipi_tx_rate; } -static void mtk_dsi_phy_timconfig(u32 data_rate) +static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid) { u32 timcon0, timcon1, timcon2, timcon3; u32 cycle_time, ui, lpx; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel / + (lanes * 1000 * 100); ui = 1000 / data_rate + 0x01; cycle_time = 8000 / data_rate + 0x01; @@ -228,67 +183,13 @@ dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); } -static void mtk_dsi_reset(void) +static void mtk_dsi_config_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, const struct edid *edid) { - dsi_setbits_le32(&dsi0->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi0->dsi_con_ctrl, 1); + mtk_dsi_phy_timconfig(dsi_id, format, lanes, edid); + mtk_dsi_config_vdo_timing(dsi_id, mode_flags, format, edid); } -static void mtk_dsi_clk_hs_mode_enable(void) -{ - dsi_setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_clk_hs_mode_disable(void) -{ - dsi_clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; - - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) +static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, const struct edid *edid) { u32 hsync_active_byte; u32 hbp_byte; @@ -298,6 +199,7 @@ u32 bpp; u32 packet_fmt; u32 hactive; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); if (format == MIPI_DSI_FMT_RGB565) bpp = 2; @@ -353,18 +255,12 @@ dsi_write32(&dsi0->dsi_psctrl, packet_fmt); } -static void mtk_dsi_start(void) -{ - dsi_write32(&dsi0->dsi_start, 0); - /* Only start master DSI */ - write32(&dsi0->dsi_start, 1); -} - static void mtk_dsi_tx_cmd_type0(u8 cmd) { struct stopwatch sw; u32 cmdq0; u32 intsta_0, intsta_1; + struct dsi_regs *const dsi0 = getdsi_regbase(0); cmdq0 = (MIPI_DSI_DCS_SHORT_WRITE << 8) | SHORT_PACKET | (cmd << 16); @@ -406,10 +302,9 @@ return -1; mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_config_timing(0, mode_flags, format, lanes, edid); + mtk_dsi_rxtx_control(0, mode_flags, lanes); + mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable(); @@ -455,3 +350,11 @@ mipi_clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } + +void *const getmipitx_regbase(u32 dsi_id){ + return dsi_id ? (void *)MIPI_TX1_BASE : (void *)MIPI_TX0_BASE; +} + +void *const getdsi_regbase(u32 dsi_id){ + return dsi_id ? (void *)DSI1_BASE : (void *)DSI0_BASE; +} \ No newline at end of file diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index ca35bd1..9b4f5db 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -17,431 +17,12 @@ #define _DSI_REG_H_ #include <edid.h> +#include <soc/dsi_common.h> #include <types.h> -enum mipi_dsi_pixel_format { - MIPI_DSI_FMT_RGB888, - MIPI_DSI_FMT_RGB666, - MIPI_DSI_FMT_RGB666_PACKED, - MIPI_DSI_FMT_RGB565 -}; - -/* video mode */ -enum { - MIPI_DSI_MODE_VIDEO = BIT(0), - /* video burst mode */ - MIPI_DSI_MODE_VIDEO_BURST = BIT(1), - /* video pulse mode */ - MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), - /* enable auto vertical count mode */ - MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), - /* enable hsync-end packets in vsync-pulse and v-porch area */ - MIPI_DSI_MODE_VIDEO_HSE = BIT(4), - /* disable hfront-porch area */ - MIPI_DSI_MODE_VIDEO_HFP = BIT(5), - /* disable hback-porch area */ - MIPI_DSI_MODE_VIDEO_HBP = BIT(6), - /* disable hsync-active area */ - MIPI_DSI_MODE_VIDEO_HSA = BIT(7), - /* flush display FIFO on vsync pulse */ - MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), - /* disable EoT packets in HS mode */ - MIPI_DSI_MODE_EOT_PACKET = BIT(9), - /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ - MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), - /* transmit data in low power */ - MIPI_DSI_MODE_LPM = BIT(11) -}; - -struct dsi_regs { - u32 dsi_start; - u8 reserved0[4]; - u32 dsi_inten; - u32 dsi_intsta; - u32 dsi_con_ctrl; - u32 dsi_mode_ctrl; - u32 dsi_txrx_ctrl; - u32 dsi_psctrl; - u32 dsi_vsa_nl; - u32 dsi_vbp_nl; - u32 dsi_vfp_nl; - u32 dsi_vact_nl; - u8 reserved1[32]; - u32 dsi_hsa_wc; - u32 dsi_hbp_wc; - u32 dsi_hfp_wc; - u32 dsi_bllp_wc; - u32 dsi_cmdq_size; - u32 dsi_hstx_cklp_wc; - u8 reserved2[156]; - u32 dsi_phy_lccon; - u32 dsi_phy_ld0con; - u8 reserved3[4]; - u32 dsi_phy_timecon0; - u32 dsi_phy_timecon1; - u32 dsi_phy_timecon2; - u32 dsi_phy_timecon3; - u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[204]; - u32 dsi_cmdq0; -}; - -check_member(dsi_regs, dsi_phy_lccon, 0x104); -check_member(dsi_regs, dsi_phy_timecon3, 0x11c); -check_member(dsi_regs, dsi_vm_cmd_con, 0x130); -check_member(dsi_regs, dsi_cmdq0, 0x200); -static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -static struct dsi_regs *const dsi1 = (void *)DSI1_BASE; - -/* DSI_INTSTA */ -enum { - LPRX_RD_RDY_INT_FLAG = BIT(0), - CMD_DONE_INT_FLAG = BIT(1), - TE_RDY_INT_FLAG = BIT(2), - VM_DONE_INT_FLAG = BIT(3), - EXT_TE_RDY_INT_FLAG = BIT(4), - DSI_BUSY = BIT(31), -}; - -/* DSI_CON_CTRL */ -enum { - DSI_RESET = BIT(0), - DSI_EN = BIT(1), - DSI_DUAL = BIT(4), -}; - -/* DSI_MODE_CTRL */ -enum { - MODE = 3, - CMD_MODE = 0, - SYNC_PULSE_MODE = 1, - SYNC_EVENT_MODE = 2, - BURST_MODE = 3, - FRM_MODE = BIT(16), - MIX_MODE = BIT(17) -}; - -/* DSI_PSCTRL */ -enum { - DSI_PS_WC = 0x3fff, - DSI_PS_SEL = (3 << 16), - PACKED_PS_16BIT_RGB565 = (0 << 16), - LOOSELY_PS_18BIT_RGB666 = (1 << 16), - PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) -}; - -/* DSI_CMDQ_SIZE */ -enum { - CMDQ_SIZE = 0x3f, -}; - -/* DSI_PHY_LCCON */ -enum { - LC_HS_TX_EN = BIT(0), - LC_ULPM_EN = BIT(1), - LC_WAKEUP_EN = BIT(2) -}; - -/*DSI_PHY_LD0CON */ -enum { - LD0_RM_TRIG_EN = BIT(0), - LD0_ULPM_EN = BIT(1), - LD0_WAKEUP_EN = BIT(2) -}; - -enum { - LPX = (0xff << 0), - HS_PRPR = (0xff << 8), - HS_ZERO = (0xff << 16), - HS_TRAIL = (0xff << 24) -}; - -enum { - TA_GO = (0xff << 0), - TA_SURE = (0xff << 8), - TA_GET = (0xff << 16), - DA_HS_EXIT = (0xff << 24) -}; - -enum { - CONT_DET = (0xff << 0), - CLK_ZERO = (0xf << 16), - CLK_TRAIL = (0xff << 24) -}; - -enum { - CLK_HS_PRPR = (0xff << 0), - CLK_HS_POST = (0xff << 8), - CLK_HS_EXIT = (0xf << 16) -}; - -/* DSI_VM_CMD_CON */ -enum { - VM_CMD_EN = BIT(0), - TS_VFP_EN = BIT(5), -}; - -/* DSI_CMDQ0 */ -enum { - CONFIG = (0xff << 0), - SHORT_PACKET = 0, - LONG_PACKET = 2, - BTA = BIT(2), - DATA_ID = (0xff << 8), - DATA_0 = (0xff << 16), - DATA_1 = (0xff << 24), -}; - -/* MIPITX_REG */ -struct mipi_tx_regs { - u32 dsi_con; - u32 dsi_clock_lane; - u32 dsi_data_lane[4]; - u8 reserved0[40]; - u32 dsi_top_con; - u32 dsi_bg_con; - u8 reserved1[8]; - u32 dsi_pll_con0; - u32 dsi_pll_con1; - u32 dsi_pll_con2; - u32 dsi_pll_con3; - u32 dsi_pll_chg; - u32 dsi_pll_top; - u32 dsi_pll_pwr; - u8 reserved2[4]; - u32 dsi_rgs; - u32 dsi_gpi_en; - u32 dsi_gpi_pull; - u32 dsi_phy_sel; - u32 dsi_sw_ctrl_en; - u32 dsi_sw_ctrl_con0; - u32 dsi_sw_ctrl_con1; - u32 dsi_sw_ctrl_con2; - u32 dsi_dbg_con; - u32 dsi_dbg_out; - u32 dsi_apb_async_sta; -}; - -check_member(mipi_tx_regs, dsi_top_con, 0x40); -check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); - -static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE; -static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE; - -/* MIPITX_DSI0_CON */ -enum { - RG_DSI0_LDOCORE_EN = BIT(0), - RG_DSI0_CKG_LDOOUT_EN = BIT(1), - RG_DSI0_BCLK_SEL = (3 << 2), - RG_DSI0_LD_IDX_SEL = (7 << 4), - RG_DSI0_PHYCLK_SEL = (2 << 8), - RG_DSI0_DSICLK_FREQ_SEL = BIT(10), - RG_DSI0_LPTX_CLMP_EN = BIT(11) -}; - -/* MIPITX_DSI0_CLOCK_LANE */ -enum { - LDOOUT_EN = BIT(0), - CKLANE_EN = BIT(1), - IPLUS1 = BIT(2), - LPTX_IPLUS2 = BIT(3), - LPTX_IMINUS = BIT(4), - LPCD_IPLUS = BIT(5), - LPCD_IMLUS = BIT(6), - RT_CODE = (0xf << 8) -}; - -/* MIPITX_DSI_TOP_CON */ -enum { - RG_DSI_LNT_INTR_EN = BIT(0), - RG_DSI_LNT_HS_BIAS_EN = BIT(1), - RG_DSI_LNT_IMP_CAL_EN = BIT(2), - RG_DSI_LNT_TESTMODE_EN = BIT(3), - RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), - RG_DSI_LNT_AIO_SEL = (7 << 8), - RG_DSI_PAD_TIE_LOW_EN = BIT(11), - RG_DSI_DEBUG_INPUT_EN = BIT(12), - RG_DSI_PRESERVE = (7 << 13) -}; - -/* MIPITX_DSI_BG_CON */ -enum { - RG_DSI_BG_CORE_EN = BIT(0), - RG_DSI_BG_CKEN = BIT(1), - RG_DSI_BG_DIV = (0x3 << 2), - RG_DSI_BG_FAST_CHARGE = BIT(4), - RG_DSI_V12_SEL = (7 << 5), - RG_DSI_V10_SEL = (7 << 8), - RG_DSI_V072_SEL = (7 << 11), - RG_DSI_V04_SEL = (7 << 14), - RG_DSI_V032_SEL = (7 << 17), - RG_DSI_V02_SEL = (7 << 20), - rsv_23 = BIT(23), - RG_DSI_BG_R1_TRIM = (0xf << 24), - RG_DSI_BG_R2_TRIM = (0xf << 28) -}; - -/* MIPITX_DSI_PLL_CON0 */ -enum { - RG_DSI0_MPPLL_PLL_EN = BIT(0), - RG_DSI0_MPPLL_PREDIV = (3 << 1), - RG_DSI0_MPPLL_TXDIV0 = (3 << 3), - RG_DSI0_MPPLL_TXDIV1 = (3 << 5), - RG_DSI0_MPPLL_POSDIV = (7 << 7), - RG_DSI0_MPPLL_MONVC_EN = BIT(10), - RG_DSI0_MPPLL_MONREF_EN = BIT(11), - RG_DSI0_MPPLL_VOD_EN = BIT(12) -}; - -/* MIPITX_DSI_PLL_CON1 */ -enum { - RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0), - RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1), - RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2), - RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16) -}; - -/* MIPITX_DSI_PLL_PWR */ -enum { - RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), - RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), - RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) -}; - -/* LVDS_TX1_REG */ -struct lvds_tx1_regs { - u32 lvdstx1_ctl1; - u32 lvdstx1_ctl2; - u32 lvdstx1_ctl3; - u32 lvdstx1_ctl4; - u32 lvdstx1_ctl5; - u32 vopll_ctl1; - u32 vopll_ctl2; - u32 vopll_ctl3; -}; - static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800); static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800); -/* LVDS_VOPLL_CTRL3 */ -enum { - RG_LVDSTX_21EDG = BIT(0), - RG_LVDSTX_21LEV = BIT(1), - RG_LVDSTX_51EDG = BIT(2), - RG_LVDSTX_51LEV = BIT(3), - RG_AD_LVDSTX_PWR_ACK = BIT(4), - RG_DA_LVDS_ISO_EN = BIT(8), - RG_DA_LVDSTX_PWR_ON = BIT(9) -}; - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -}; - int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, bool dual_dsi_mode, const struct edid *edid); void mtk_dsi_pin_drv_ctrl(void); diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 15ad154..355c889 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -43,7 +43,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ddp.c -ramstage-y += dsi.c +ramstage-y += ../common/dsi.c dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 30057c7..383f79e 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -1,481 +1,310 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <console/console.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/dsi.h> -#include <timer.h> - -static void dsi_write32(void *a, uint32_t v) -{ - write32(a, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - clrsetbits_le32(a, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - clrbits_le32(a, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - setbits_le32(a, m); -} - -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, - const struct edid *edid) -{ - unsigned int txdiv, txdiv0, txdiv1; - u64 pcw; - int data_rate; - u32 bpp; - - switch (format) { - case MIPI_DSI_FMT_RGB565: - bpp = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bpp = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bpp = 24; - break; - } - - data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; - - printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); - - if (data_rate >= 2000000000) { - txdiv = 1; - txdiv0 = 0; - txdiv1 = 0; - } else if (data_rate >= 1000000000) { - txdiv = 2; - txdiv0 = 1; - txdiv1 = 0; - } else if (data_rate >= 500000000) { - txdiv = 4; - txdiv0 = 2; - txdiv1 = 0; - } else if (data_rate > 250000000) { - txdiv = 8; - txdiv0 = 3; - txdiv1 = 0; - } else if (data_rate >= 125000000) { - txdiv = 16; - txdiv0 = 4; - txdiv1 = 0; - } else { - printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " - "pixel clock (%u), bpp (%u), number of lanes (%u)\n", - data_rate, edid->mode.pixel_clock, bpp, - lanes); - return -1; - } - - dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10)); - - dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); - udelay(30); - dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); - - pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); - pcw <<= 24; - pcw /= 26; - - dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw); - dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, - txdiv0 << 8); - udelay(30); - dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN); - - /* BG_LPF_EN / BG_CORE_EN */ - dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180); - udelay(40); - dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0); - - /* Switch OFF each Lane */ - dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); - - dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); - - return data_rate; -} - -static void mtk_dsi_phy_timconfig(u32 data_rate, - struct mtk_phy_timing *phy_timing) -{ - u32 timcon0, timcon1, timcon2, timcon3; - - timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | - phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; - timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | - phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; - timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | - phy_timing->clk_hs_trail << 24; - timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | - phy_timing->clk_hs_exit << 16; - - dsi_write32(&dsi->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi->dsi_phy_timecon3, timcon3); -} - -static void mtk_dsi_reset(void) -{ - dsi_write32(&dsi->dsi_con_ctrl, 1); - dsi_write32(&dsi->dsi_con_ctrl, 0); -} - -static void mtk_dsi_clk_hs_mode_enable(void) -{ - dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); -} - -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; - - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes, - const struct edid *edid, - struct mtk_phy_timing *phy_timing) -{ - u32 ui, cycle_time, data_rate; - u32 bit_per_pixel; - - switch (format) { - case MIPI_DSI_FMT_RGB565: - bit_per_pixel = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bit_per_pixel = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bit_per_pixel = 24; - break; - } - - data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; - - ui = 1000 / (data_rate / 1000) + 1U; - cycle_time = 8000 / (data_rate / 1000) + 1U; - - phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); - - phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; - - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; - - phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid, - struct mtk_phy_timing *phy_timing, - u32 lanes) -{ - u32 hsync_active_byte; - u32 hbp_byte; - u32 hfp_byte, tmp_hfp_byte; - u32 vbp_byte; - u32 vfp_byte; - u32 bpp; - u32 packet_fmt; - u32 hactive; - u32 data_phy_cycles; - - if (format == MIPI_DSI_FMT_RGB565) - bpp = 2; - else - bpp = 3; - - vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - - edid->mode.vborder; - vfp_byte = edid->mode.vso - edid->mode.vborder; - - dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw); - dsi_write32(&dsi->dsi_vbp_nl, vbp_byte); - dsi_write32(&dsi->dsi_vfp_nl, vfp_byte); - dsi_write32(&dsi->dsi_vact_nl, edid->mode.va); - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bpp - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; - - hsync_active_byte = edid->mode.hspw * bpp - 10; - - data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; - - tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { - if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { - hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; - } else { - printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); - hfp_byte = tmp_hfp_byte; - } - } else { - if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { - hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; - } else { - printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); - hfp_byte = tmp_hfp_byte; - } - } - - dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte); - dsi_write32(&dsi->dsi_hbp_wc, hbp_byte); - dsi_write32(&dsi->dsi_hfp_wc, hfp_byte); - - switch (format) { - case MIPI_DSI_FMT_RGB888: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - packet_fmt = LOOSELY_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - packet_fmt = PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - packet_fmt = PACKED_PS_16BIT_RGB565; - break; - default: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - } - - hactive = edid->mode.ha; - packet_fmt |= (hactive * bpp) & DSI_PS_WC; - - dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt); - dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive); -} - -static void mtk_dsi_start(void) -{ - dsi_clrbits_le32(&dsi->dsi_start, 1); - dsi_setbits_le32(&dsi->dsi_start, 1); -} - -static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) -{ - struct stopwatch sw; - u8 *tx_buf = data; - u8 cmdq_size; - u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; - - while (read32(&dsi->dsi_intsta) & (1 << 31)) { - printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); - mdelay(20); - } - - dsi_write32(&dsi->dsi_intsta, 0); - - if (MTK_DSI_HOST_IS_READ(type)) - config = BTA; - else - config = (len > 2) ? LONG_PACKET : SHORT_PACKET; - - if (len > 2) { - cmdq_size = 1 + (len + 3) / 4; - cmdq_off = 4; - cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; - reg_val = (len << 16) | (type << 8) | config; - } else { - cmdq_size = 1; - cmdq_off = 2; - cmdq_mask = CONFIG | DATA_ID; - reg_val = (type << 8) | config; - } - - for (i = 0; i < 0x20; i = i + 4) - dsi_write32((void *)DSI_BASE + 0x200 + i, 0); - - for (i = 0; i < len; i++) { - dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + - ((cmdq_off + i) & (0xfffffffc)), - (0xff << (((i + cmdq_off) & 3) * 8)), - tx_buf[i] << (((i + cmdq_off) & 3) * 8)); - } - - dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); - dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); - mtk_dsi_start(); - - stopwatch_init_usecs_expire(&sw, 400); - do { - intsta_0 = read32(&dsi->dsi_intsta); - if (intsta_0 & CMD_DONE_INT_FLAG) - break; - udelay(4); - } while (!stopwatch_expired(&sw)); - - if (!(intsta_0 & CMD_DONE_INT_FLAG)) - printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); -} - -static void push_table(struct lcm_init_table *init_cmd) -{ - u32 cmd, i; - u32 type; - - for (i = 0; ; i++) { - cmd = init_cmd[i].cmd; - - switch (cmd) { - case DELAY_CMD: - mdelay(init_cmd[i].len); - break; - - case END_OF_TABLE: - return; - - case INIT_DCS_CMD: - switch (init_cmd[i].len) { - case 0: - return; - - case 1: - type = MIPI_DSI_DCS_SHORT_WRITE; - break; - - case 2: - type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - - default: - type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); - break; - - case INIT_GENENIC_CMD: - default: - switch (init_cmd[i].len) { - case 0: - type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; - break; - case 1: - type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; - break; - case 2: - type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; - break; - default: - type = MIPI_DSI_GENERIC_LONG_WRITE; - break; - } - mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); - break; - } - } -} - -int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, - const struct edid *edid, struct lcm_init_table *init_cmd) -{ - int data_rate; - struct mtk_phy_timing phy_timing; - - mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); - - data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); - - if (data_rate < 0) - return -1; - - dsi_write32(&dsi->dsi_force_commit, 3); - mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate, &phy_timing); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes); - mtk_dsi_clk_hs_mode_enable(); - push_table(init_cmd); - mtk_dsi_set_mode(mode_flags); - mtk_dsi_start(); - - return 0; -} +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +void *getmipitx_regbase(u32 dsi_id) +{ + return dsi_id ? NULL : (void *)MIPITX_BASE; +} + +void *getdsi_regbase(u32 dsi_id) +{ + return dsi_id ? NULL : (void *)DSI_BASE; +} + +static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 timcon0, timcon1, timcon2, timcon3; + u32 ui, cycle_time, data_rate, bit_per_pixel; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; + + ui = 1000 / (data_rate / 1000) + 1U; + cycle_time = 8000 / (data_rate / 1000) + 1U; + + phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + dsi_write32(&dsi0->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi0->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi0->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); +} + +static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes, + const struct edid *edid) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + int data_rate; + u32 bpp; + void *mipi_tx0 = getmipitx_regbase(dsi_id); + + if (dsi_id > 0) { + printk(BIOS_ERR, "No support dual dsi, please check you panel config\n"); + return -1; + } + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bpp = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bpp = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bpp = 24; + break; + } + + data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; + + printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); + + if (data_rate >= 2000000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250000000) { + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else if (data_rate >= 125000000) { + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bpp, + lanes); + return -1; + } + + dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_CON4, BIT(11) | BIT(10)); + + dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); + pcw <<= 24; + pcw /= 26; + + dsi_write32(mipi_tx0 + MIPITX_PLL_CON0, pcw); + dsi_clrsetbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, + txdiv0 << 8); + udelay(30); + dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF0180); + udelay(40); + dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF00c0); + + /* Switch OFF each Lane */ + dsi_clrbits_le32(mipi_tx0 + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + dsi_setbits_le32(mipi_tx0 + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + + return data_rate; +} + +static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte, tmp_hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + u32 hactive; + u32 data_phy_cycles; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + dsi_write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); + dsi_write32(&dsi0->dsi_vbp_nl, vbp_byte); + dsi_write32(&dsi0->dsi_vfp_nl, vfp_byte); + dsi_write32(&dsi0->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } else { + if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } + + dsi_write32(&dsi0->dsi_hsa_wc, hsync_active_byte); + dsi_write32(&dsi0->dsi_hbp_wc, hbp_byte); + dsi_write32(&dsi0->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bpp) & DSI_PS_WC; + + dsi_write32(&dsi0->dsi_psctrl, 0x2c << 24 | packet_fmt); + dsi_write32(&dsi0->dsi_size_con, edid->mode.va << 16 | hactive); + dsi_write32(&dsi0->dsi_force_commit, 3); +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd) +{ + int data_rate; + struct dsi_regs *const dsi0 = getdsi_regbase(0); + struct mtk_phy_timing *phy_timing = NULL; + + data_rate = mtk_dsi_phy_clk_setting(0, format, lanes, edid); + + if (data_rate < 0) + return -1; + + if (dual) { + data_rate = mtk_dsi_phy_clk_setting(1, format, lanes, edid); + if (data_rate < 0) + return -1; + } + + mtk_dsi_reset(0); + if (dual) + mtk_dsi_reset(1); + + mtk_dsi_rxtx_control(0, mode_flags, lanes); + mtk_dsi_phy_timconfig(0, format, lanes, edid, phy_timing); + mtk_dsi_config_vdo_timing(0, mode_flags, format, lanes, edid, phy_timing); + mtk_dsi_clk_hs_mode_enable(0); + + push_table(init_cmd); + + mtk_dsi_set_mode(0, mode_flags); + if (dual) { + mtk_dsi_set_mode(1, mode_flags); + dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN | DSI_DUAL); + } + mtk_dsi_start(0); + + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 1fb3509..5f614034 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -483,4 +483,19 @@ const struct edid *edid, struct lcm_init_table *init_cmd); +void *getmipitx_regbase(u32 dsi_id); +void *getdsi_regbase(u32 dsi_id); + +void dsi_write32(void *a, uint32_t v); +void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v); +void dsi_clrbits_le32(void *a, uint32_t m); +void dsi_setbits_le32(void *a, uint32_t m); +void mtk_dsi_reset(u32 dsi_id); +void mtk_dsi_clk_hs_mode_enable(u32 dsi_id); +void mtk_dsi_set_mode(u32 dsi_id, u32 mode_flags); +void mtk_dsi_rxtx_control(u32 dsi_id, u32 mode_flags, u32 lanes); +void mtk_dsi_start(u32 dsi_id); +void push_table(struct lcm_init_table *init_cmd); + + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I242d7a4f75057c0a955c9284a79c385a667ce7bd Gerrit-Change-Number: 34562 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: WIP: mediatek/mt8183: Add SCP work support
by Erin Lo (Code Review) 31 Mar '22

31 Mar '22

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34382 ) Change subject: WIP: mediatek/mt8183: Add SCP work support ...................................................................... WIP: mediatek/mt8183: Add SCP work support Load SCP firmware to SCP's sram since buffer size is limited so load splitted binaries. After SCP works done, disable it Test=Build pass Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/scp.h A src/soc/mediatek/mt8183/scp.c 6 files changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34382/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..f8a5bab 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,18 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += scp_0.bin +scp_0.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_0.bin +scp_0.bin-type := raw +scp_0.bin-compression := none + +cbfs-files-y += scp_1.bin +scp_1.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_1.bin +scp_1.bin-type := raw +scp_1.bin-compression := none + +cbfs-files-y += scp_2.bin +scp_2.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_2.bin +scp_2.bin-type := raw +scp_2.bin-compression := none diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..cf3572d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,7 +19,7 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> - +#include <soc/scp.h> #include "early_init.h" void platform_romstage_main(void) @@ -33,6 +33,7 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); + scp_work(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d35a07e..0543552 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c +romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index e9f80d1..affc776 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,9 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SCP_SRAM_BASE = IO_PHYS + 0x00500000, + SCP_CFG_BASE = IO_PHYS + 0x005C0000, + SCP_CLK_CTRL_BASE = IO_PHYS + 0x005C4000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/scp.h b/src/soc/mediatek/mt8183/include/soc/scp.h new file mode 100644 index 0000000..a3003bd --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/scp.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SCP_H +#define SOC_MEDIATEK_MT8183_SCP_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_scp_regs { + u32 sw_rstn; + u32 reserved[19]; + u32 gpr0; +}; + +struct mt8183_scp_clk_ctrl_regs { + u32 reserved[11]; + u32 sram_pdn; +}; + +static struct mt8183_scp_regs *const mt8183_scp = (void *)SCP_CFG_BASE; +static struct mt8183_scp_clk_ctrl_regs *const mt8183_scp_clk_ctrl = (void *)SCP_CLK_CTRL_BASE; +void scp_work(void); +#endif /* SOC_MEDIATEK_MT8183_SCP_H */ diff --git a/src/soc/mediatek/mt8183/scp.c b/src/soc/mediatek/mt8183/scp.c new file mode 100644 index 0000000..150eeba --- /dev/null +++ b/src/soc/mediatek/mt8183/scp.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/mmio.h> +#include <soc/scp.h> +#include <string.h> + +#define BUF_SIZE (40 * KiB) +static uint8_t scp_bin[BUF_SIZE] __aligned(8); + +void scp_work(void) +{ + size_t fw_size; + + write32(&mt8183_scp_clk_ctrl->sram_pdn, 0x0); + mb(); + + fw_size = cbfs_boot_load_file("scp_0.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_0.bin not found."); + memcpy((void *)SCP_SRAM_BASE + 0x0, scp_bin, fw_size); + + fw_size = cbfs_boot_load_file("scp_1.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size); + if (fw_size == 0) + die("SCP file :scp_1.bin not found."); + + fw_size = cbfs_boot_load_file("scp_2.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_2.bin not found."); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size); + + + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8183_scp->sw_rstn, 0x1); + while (read32(&mt8183_scp->gpr0) != 0xaaaa){} + mb(); + write32(&mt8183_scp->sw_rstn, 0x0); + printk(BIOS_DEBUG, "scp finished \n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Gerrit-Change-Number: 34382 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: driver/thunderbolt: Driver for allocating hotplug resources
by Jeremy Soller (Code Review) 24 Mar '22

24 Mar '22

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35946 ) Change subject: driver/thunderbolt: Driver for allocating hotplug resources ...................................................................... driver/thunderbolt: Driver for allocating hotplug resources This adds a new driver which can be selected with DRIVERS_THUNDERBOLT that, by default, adds 32 PCI subordinate numbers, 256 MiB of both prefetchable and non-prefetchable memory, and 8 KiB of I/O space to matching devices. It currently supports the JHL7540 Thunderbolt 3 bridge, but other devices can be added easily. In order to support the allocation of hotplugged PCI buses, a new field was added to struct device called hotplug_buses. This is defaulted to zero, but when set, it adds the hotplug_buses value to the subordinate value of the PCI bridge. This allows devices to be plugged in and unplugged after boot. This code was tested on the System76 Darter Pro (darp6). Before this change, there are not enough resources allocated to the Thunderbolt PCI bridge to allow plugging in new devices after boot. This can be worked around in the Linux kernel by passing a boot param such as: pci=assign-buses,hpbussize=32,realloc This change makes it possible to use Thunderbolt hotplugging without kernel parameters, and attempts to match closely what our motherboard manufacturer's firmware does by default. Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc --- M src/device/pci_device.c A src/drivers/thunderbolt/Kconfig A src/drivers/thunderbolt/Makefile.inc A src/drivers/thunderbolt/thunderbolt.c M src/include/device/device.h 5 files changed, 117 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35946/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index c043dd6..1796d81 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1217,7 +1217,7 @@ if (state == PCI_ROUTE_SCAN) { link->secondary = parent->subordinate + 1; - link->subordinate = link->secondary; + link->subordinate = link->secondary + dev->hotplug_buses; } if (state == PCI_ROUTE_CLOSE) { diff --git a/src/drivers/thunderbolt/Kconfig b/src/drivers/thunderbolt/Kconfig new file mode 100644 index 0000000..f64e6cb --- /dev/null +++ b/src/drivers/thunderbolt/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_THUNDERBOLT + bool + help + Thunderbolt support diff --git a/src/drivers/thunderbolt/Makefile.inc b/src/drivers/thunderbolt/Makefile.inc new file mode 100644 index 0000000..623b897 --- /dev/null +++ b/src/drivers/thunderbolt/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_THUNDERBOLT) += thunderbolt.c diff --git a/src/drivers/thunderbolt/thunderbolt.c b/src/drivers/thunderbolt/thunderbolt.c new file mode 100644 index 0000000..db463e0e --- /dev/null +++ b/src/drivers/thunderbolt/thunderbolt.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76. + * Copyright (C) 2017-2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> + +static void slot_dev_read_resources(struct device *dev) +{ + struct resource *resource; + + // Add 256 MiB of memory space + resource = new_resource(dev, 0x10); + resource->size = 1 << 28; + resource->align = 22; + resource->gran = 22; + resource->limit = 0xffffffff; + resource->flags |= IORESOURCE_MEM; + + // Add 256 MiB of prefetchable memory space + resource = new_resource(dev, 0x14); + resource->size = 1 << 28; + resource->align = 22; + resource->gran = 22; + resource->limit = 0xffffffff; + resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; + + // Add 8 KiB of I/O space + resource = new_resource(dev, 0x18); + resource->size = 1 << 13; + resource->align = 12; + resource->gran = 12; + resource->limit = 0xffff; + resource->flags |= IORESOURCE_IO; +} + +static struct device_operations slot_dev_ops = { + .read_resources = slot_dev_read_resources, +}; + +static bool tbt_is_hotplug_bridge(struct device *dev) { + return PCI_SLOT(dev->path.pci.devfn) == 1; +} + +static void tbt_pciexp_scan_bridge(struct device *dev) { + printk(BIOS_DEBUG, "%s: %s: scan bridge\n", __func__, dev_path(dev)); + + bool is_hotplug = tbt_is_hotplug_bridge(dev); + if (is_hotplug) { + /* Add hotplug buses, must happen before bus scan */ + printk(BIOS_DEBUG, "%s: %s: add hotplug buses\n", __func__, dev_path(dev)); + dev->hotplug_buses = 32; + } + + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); + + if (is_hotplug) { + /* Add dummy slot to preserve resources, must happen after bus scan */ + printk(BIOS_DEBUG, "%s: %s: add dummy device\n", __func__, dev_path(dev)); + struct device *slot; + struct device_path slot_path = { .type = DEVICE_PATH_NONE }; + slot = alloc_dev(dev->link_list, &slot_path); + slot->ops = &slot_dev_ops; + } +} + +static struct pci_operations pcie_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0, + .scan_bus = tbt_pciexp_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &pcie_ops, +}; + +static const unsigned short pcie_device_ids[] = { + // JHL7540 Thunderbolt 3 Bridge + 0x15e7, + 0 +}; + +static const struct pci_driver tbt_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; diff --git a/src/include/device/device.h b/src/include/device/device.h index cb37c09..f22bed5 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -129,6 +129,7 @@ unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ u8 command; + uint16_t hotplug_buses; /* hotplug buses to allocate */ /* Base registers for this device. I/O, MEM and Expansion ROM */ DEVTREE_CONST struct resource *resource_list; -- To view, visit https://review.coreboot.org/c/coreboot/+/35946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc Gerrit-Change-Number: 35946 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jeremy(a)system76.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: enable lpc at bootblock
by Thomas Heijligen (Code Review) 01 Feb '22

01 Feb '22

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31371 to review the following change. Change subject: soc/intel/apl: enable lpc at bootblock ...................................................................... soc/intel/apl: enable lpc at bootblock Serial console can be attached to lpc bus. Enable it for early debug Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c 4 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31371/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..e0217ef 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -120,4 +121,6 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + + pch_enable_lpc(); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b8f9f8c..2f25a3b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,9 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Generic i/o decode ranges routed to LPC */ + uint32_t lpc_gen_dec[4]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index a20b82a..ffa4cf5 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -42,6 +42,18 @@ return apl_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const struct soc_intel_apollolake_config *const config = dev->chip_info; + + if (!config) { + memset(gen_io_dec, 0x00, sizeof(config->lpc_gen_dec)); + return; + } + + memcpy(gen_io_dec, config->lpc_gen_dec, sizeof(config->lpc_gen_dec)); +} + static const struct pad_config lpc_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if !IS_ENABLED(CONFIG_SOC_ESPI) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index fb50b74..d584d2c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -24,6 +24,9 @@ #include <lib.h> #include "lpc_def.h" #include <soc/pci_devs.h> +#include <stdint.h> + +__weak void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) {} uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Gerrit-Change-Number: 31371 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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