coreboot-gerrit June 2018

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Change in coreboot[master]: Documentation: Add Gigabyte GA-H61M-S2PV
by build bot (Jenkins) (Code Review) 08 Jun '18

08 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26964 ) Change subject: Documentation: Add Gigabyte GA-H61M-S2PV ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/28666/ : ABORTED -- To view, visit https://review.coreboot.org/26964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0064710362a1c7882d5a40b469d6aacad5c60218 Gerrit-Change-Number: 26964 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Jun 2018 15:49:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Add Gigabyte GA-H61M-S2PV
by Angel Pons (Code Review) 08 Jun '18

08 Jun '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/26964 Change subject: Documentation: Add Gigabyte GA-H61M-S2PV ...................................................................... Documentation: Add Gigabyte GA-H61M-S2PV Change-Id: I0064710362a1c7882d5a40b469d6aacad5c60218 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A Documentation/mainboard/gigabyte/ga-h61m-s2pv.md 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/26964/1 diff --git a/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md new file mode 100644 index 0000000..54c647e --- /dev/null +++ b/Documentation/mainboard/gigabyte/ga-h61m-s2pv.md @@ -0,0 +1,54 @@ +# Gigabyte GA-H61M-S2PV + +This page describes how to run coreboot on the [Gigabyte GA-H61M-S2PV] desktop +from [Gigabyte]. + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L3206E | ++---------------------+------------+ +| Size | 4 MiB | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | Yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | ITE IT8728F | ++------------------+--------------------------------------------------+ +| EC | | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[Gigabyte GA-H61M-S2PV]: https://www.gigabyte.com/us/Motherboard/GA-H61M-S2PV-rev-10 +[Gigabyte]: https://www.gigabyte.com +[flashrom]: https://flashrom.org/Flashrom -- To view, visit https://review.coreboot.org/26964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0064710362a1c7882d5a40b469d6aacad5c60218 Gerrit-Change-Number: 26964 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: mainboard/google/kahlee: Use 66MHz SPI clock for fast read
by build bot (Jenkins) (Code Review) 08 Jun '18

08 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26950 ) Change subject: mainboard/google/kahlee: Use 66MHz SPI clock for fast read ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74546/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28664/ : SUCCESS -- To view, visit https://review.coreboot.org/26950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Gerrit-Change-Number: 26950 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Jun 2018 15:09:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/kahlee: Use 66MHz SPI clock for fast read
by Martin Roth (Code Review) 08 Jun '18

08 Jun '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26950 Change subject: mainboard/google/kahlee: Use 66MHz SPI clock for fast read ...................................................................... mainboard/google/kahlee: Use 66MHz SPI clock for fast read Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/bootblock/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/26950/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 8f124b3..7e6524d 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -44,7 +44,7 @@ /* Set SPI speeds before verstage. Needed for TPM */ sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_100M, /* Fast */ + SPI_SPEED_66M, /* Fast */ SPI_SPEED_66M, /* AltIO */ SPI_SPEED_66M); /* TPM */ -- To view, visit https://review.coreboot.org/26950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Gerrit-Change-Number: 26950 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: util/lint: Update lint-stable-000-license-headers linter
by build bot (Jenkins) (Code Review) 08 Jun '18

08 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26573 ) Change subject: util/lint: Update lint-stable-000-license-headers linter ...................................................................... Patch Set 6: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74545/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/28663/ : SUCCESS -- To view, visit https://review.coreboot.org/26573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40046a2fb7359262b130f6813eda1f2c30916b46 Gerrit-Change-Number: 26573 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 07 Jun 2018 14:13:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/lint: Update lint-stable-000-license-headers linter
by build bot (Jenkins) (Code Review) 08 Jun '18

08 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26573 ) Change subject: util/lint: Update lint-stable-000-license-headers linter ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/74544/ : ABORTED -- To view, visit https://review.coreboot.org/26573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40046a2fb7359262b130f6813eda1f2c30916b46 Gerrit-Change-Number: 26573 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 07 Jun 2018 14:13:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI source
by build bot (Jenkins) (Code Review) 07 Jun '18

07 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26931 ) Change subject: mb/google/kahlee: Configure EC_PCH_WAKE_L as an SCI source ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74543/ : SUCCESS -- To view, visit https://review.coreboot.org/26931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe Gerrit-Change-Number: 26931 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Jun 2018 13:55:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOs
by build bot (Jenkins) (Code Review) 07 Jun '18

07 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26930 ) Change subject: amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOs ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74542/ : SUCCESS -- To view, visit https://review.coreboot.org/26930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a Gerrit-Change-Number: 26930 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Jun 2018 13:54:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Enable low power S0Idle capability
by Naresh Solanki (Code Review) 07 Jun '18

07 Jun '18

Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/26940 ) Change subject: soc/intel/skylake: Enable low power S0Idle capability ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/26940/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26940/2//COMMIT_MSG@11 PS2, Line 11: FSPUPD Which FSP UPD is being set? https://review.coreboot.org/#/c/26940/2/src/soc/intel/skylake/acpi.c File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/#/c/26940/2/src/soc/intel/skylake/acpi.c@238 PS2, Line 238: dev Do NULL check before de-referencing pointer: const struct soc_intel_skylake_config *config = dev ? dev->chip_info : NULL; https://review.coreboot.org/#/c/26940/2/src/soc/intel/skylake/acpi.c@287 PS2, Line 287: if (config->s0ix_enable) NULL check of pointer config before it is dereferenced. if (config && config->s0ix_enable) -- To view, visit https://review.coreboot.org/26940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210 Gerrit-Change-Number: 26940 Gerrit-PatchSet: 2 Gerrit-Owner: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Haridhar Kalvala <haridhar.kalvala(a)intel.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Comment-Date: Thu, 07 Jun 2018 12:59:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation: Add Trusted Computing documentation
by Patrick Rudolph (Code Review) 07 Jun '18

07 Jun '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/26925 ) Change subject: Documentation: Add Trusted Computing documentation ...................................................................... Patch Set 1: (12 comments) https://review.coreboot.org/#/c/26925/1/Documentation/security/security.md File Documentation/security/security.md: https://review.coreboot.org/#/c/26925/1/Documentation/security/security.md@1 PS1, Line 1: .. toctree:: rename file to index.md https://review.coreboot.org/#/c/26925/1/Documentation/security/security.md@6 PS1, Line 6: The security describes existing technologies which are shipped with coreboot. section https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… File Documentation/security/trusted-computing/index.md: https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 2: respect 80 chars line limit https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 3: coreboot offers trusted computing support for the TCG specification 1.1, 1.2 and 2.0. Bus protocols like I2C, SPI and PC80 are supported by default. For more information please consult the [TCG](https://trustedcomputinggroup.org/). bus ...based on the TCG spec... ... are supported. ... the [TCG]. [TCG]: https://trustedcomputinggroup.org/ https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 7: ![integration](code-structure.png) Interface, not integration https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 12: The TPM Interface Service is the driver layer communicating directly to the TPM through different bus implementations. Bold or italic https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 22: The TPM Software Stack is the implementation of the TPM communication protocol and commands which can be used to execute task on a TPM. Évery TPM specification has its own functionality which needs to be implemented standalone. Every https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 92: The normal boot flow without measured boot and vboot is done by a TPM ramstage driver which is executed at the start of BS_DEV_INIT. The ramstage driver is automatically selected if there is no vboot enabled but the TPM support is compiled into the coreboot image. there is no vboot enabled -> vboot isn't enabled, https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 102: coreboot does not use the official TCPA log because of limitations and specification issues. Therefore we offer two ACPI logs. The first is the standard log which is interfaced through ACPI buy bootloader and the OS. The second log is exposed via CBMEM and used by coreboot to report all measurements. To be compliant with the existing kernel TCPA ACPI log, cbmem prints the results in the same format. cbmem logs ? https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 114: First select one of the bus type driver: newline before ``` due to broken markdown parsers ! https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 127: If you added it to the config. You should already see a kconfig menu under Security -> Trusted Platform Module for selecting the TPM specification. This is useful for desktop and server boards which have a TPM header with multiple specification options. ```Security -> Trusted Platform Module``` specifications -> variations https://review.coreboot.org/#/c/26925/1/Documentation/security/trusted-comp… PS1, Line 137: Ǹow you are done! Now -- To view, visit https://review.coreboot.org/26925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d49a113c77c08c0c703791a160704ae57e3c3f7 Gerrit-Change-Number: 26925 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Jun 2018 12:50:59 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit June 2018