coreboot-gerrit June 2018

coreboot-gerrit@coreboot.org

1 participants
2751 discussions

Change in coreboot[master]: driver/spi/macronix.c: Add MX25L8005
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27040 ) Change subject: driver/spi/macronix.c: Add MX25L8005 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/74812/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/28912/ : SUCCESS -- To view, visit https://review.coreboot.org/27040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I595198d66193c63f6c80c39371fbec10065d2165 Gerrit-Change-Number: 27040 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Jun 2018 22:28:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: sb/intel/i82801{g, j}x: Automatically generate ACPI PIRQ tables
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22981 ) Change subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables ...................................................................... Patch Set 16: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/74813/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/28913/ : SUCCESS -- To view, visit https://review.coreboot.org/22981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Gerrit-Change-Number: 22981 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 12 Jun 2018 22:28:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: sb/intel/common: Make RCBA manipulation MACROs common
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/27041 ) Change subject: sb/intel/common: Make RCBA manipulation MACROs common ...................................................................... sb/intel/common: Make RCBA manipulation MACROs common No Change in BUILD_TIMELESS. Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/pch.h A src/southbridge/intel/common/rcba.h M src/southbridge/intel/ibexpeak/pch.h 3 files changed, 43 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27041/2 -- To view, visit https://review.coreboot.org/27041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d Gerrit-Change-Number: 27041 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: Revert "sb/intel/{bd82x6, ibexpeak}: Move RCBA macros to a common loca...
by build bot (Jenkins) (Code Review) 13 Jun '18

13 Jun '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27038 ) Change subject: Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" ...................................................................... Patch Set 2: (32 comments) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h File src/southbridge/intel/bd82x6x/pch.h: https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 273: #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 274: #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 275: #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 277: #define RCBA_AND_OR(bits, x, and, or) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 278: RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) code indent should use tabs where possible https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 278: RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) please, no spaces at the start of a line https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 324: #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 326: #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 413: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 413: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 413: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 413: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 413: #define DIR_ROUTE(x,a,b,c,d) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 414: RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ please, no spaces at the start of a line https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 415: ((b) << DIR_IBR) | ((a) << DIR_IAR)) code indent should use tabs where possible https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/bd82x6x/pch.h… PS2, Line 415: ((b) << DIR_IBR) | ((a) << DIR_IAR)) please, no spaces at the start of a line https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.h File src/southbridge/intel/ibexpeak/pch.h: https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 245: #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 246: #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 247: #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 249: #define RCBA_AND_OR(bits, x, and, or) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 250: RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) code indent should use tabs where possible https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 250: RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) please, no spaces at the start of a line https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 296: #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 298: #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 386: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 386: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 386: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 386: #define DIR_ROUTE(x,a,b,c,d) \ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 386: #define DIR_ROUTE(x,a,b,c,d) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 387: RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ please, no spaces at the start of a line https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 388: ((b) << DIR_IBR) | ((a) << DIR_IAR)) code indent should use tabs where possible https://review.coreboot.org/#/c/27038/2/src/southbridge/intel/ibexpeak/pch.… PS2, Line 388: ((b) << DIR_IBR) | ((a) << DIR_IAR)) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/27038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Gerrit-Change-Number: 27038 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Jun 2018 22:23:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [RFC]sb/intel/acpi_pirq_gen.c: Have the southbridge provide RCBA
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/27039 ) Change subject: [RFC]sb/intel/acpi_pirq_gen.c: Have the southbridge provide RCBA ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/27039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I5beb7ffd460f32deaa9e0f397f444baeee9c41fb Gerrit-Change-Number: 27039 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: sb/intel/i82801xx: Use common RCBA MACROs
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27043 Change subject: sb/intel/i82801xx: Use common RCBA MACROs ...................................................................... sb/intel/i82801xx: Use common RCBA MACROs Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/i82801jx.h 3 files changed, 3 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/27043/1 diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 36c79eb..d14a809 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -31,11 +31,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif +#include <southbridge/intel/common/rcba.h> #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 @@ -194,10 +190,6 @@ /* Root Complex Register Block */ #define RCBA 0xf0 -#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x)))) -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) -#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x)))) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 38dfa38..2bce3ab 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -24,12 +24,7 @@ #endif #endif -#define DEFAULT_TBAR ((u8 *)0xfed1b000) -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif +#include <southbridge/intel/common/rcba.h> #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) /* @@ -154,10 +149,6 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - #define RCBA_V0CTL 0x0014 #define RCBA_V1CAP 0x001c #define RCBA_V1CTL 0x0020 diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 88e0ad0..1e63e4f 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -24,12 +24,7 @@ #endif #endif -#define DEFAULT_TBAR ((u8 *)0xfed1b000) -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif +#include <southbridge/intel/common/rcba.h> #define DEFAULT_PMBASE 0x00000500 #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) @@ -147,10 +142,6 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - #define RCBA_V0CTL 0x0014 #define RCBA_V1CAP 0x001c #define RCBA_V1CTL 0x0020 -- To view, visit https://review.coreboot.org/27043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870 Gerrit-Change-Number: 27043 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27042 Change subject: sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs ...................................................................... sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27042/1 diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 7f97971..366fe08 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> +#include <southbridge/intel/common/rcba.h> #define MAX_SLOT 31 #define MIN_SLOT 19 diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index cf76fb3..e5ac409 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -37,8 +37,4 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define DEFAULT_RCBA 0xfed1c000 - -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) - #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */ -- To view, visit https://review.coreboot.org/27042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Gerrit-Change-Number: 27042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: sb/intel/common: Make RCBA manipulation MACROs common
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27041 Change subject: sb/intel/common: Make RCBA manipulation MACROs common ...................................................................... sb/intel/common: Make RCBA manipulation MACROs common No Change in BUILD_TIMELESS. Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/pch.h A src/southbridge/intel/common/rcba.h M src/southbridge/intel/ibexpeak/pch.h 3 files changed, 50 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27041/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3975d0c..7c7e0ed 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -45,11 +45,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif +#include <southbridge/intel/common/rcba.h> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) #define CROS_GPIO_DEVICE_NAME "CougarPoint" @@ -270,17 +266,6 @@ /* Root Complex Register Block */ #define RCBA 0xf0 -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h new file mode 100644 index 0000000..21329a3 --- /dev/null +++ b/src/southbridge/intel/common/rcba.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H +#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H + +/* + * The DnnIR registers use common RCBA offsets across these chipsets: + * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint + * + * However not all registers are in use on all of these. + */ + +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else +#define DEFAULT_RCBA 0xfed1c000 +#endif + +#ifndef __ACPI__ + +#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) +#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) +#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) + +#define RCBA_AND_OR(bits, x, and, or) \ + (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) +#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) +#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) +#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) +#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) + + +#endif /* __ACPI__ */ +#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 8012a75..55478b9 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -46,11 +46,7 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif +#include <southbridge/intel/common/rcba.h> #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 @@ -242,17 +238,6 @@ /* Root Complex Register Block */ #define RCBA 0xf0 -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ -- To view, visit https://review.coreboot.org/27041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d Gerrit-Change-Number: 27041 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: Revert "sb/intel/{bd82x6, ibexpeak}: Move RCBA macros to a common loca...
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27038 to look at the new patch set (#2). Change subject: Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" ...................................................................... Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location" In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/apple/macbookair4_2/mainboard.c M src/mainboard/compulab/intense_pc/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/roda/rv11/romstage.c M src/mainboard/roda/rv11/variants/rv11/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/sapphire/pureplatinumh61/mainboard.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_rcba.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/bd82x6x/usb_ehci.c D src/southbridge/intel/common/rcba.h M src/southbridge/intel/common/rcba_pirq.c A src/southbridge/intel/common/rcba_pirq.h M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/ibexpeak/usb_ehci.c 65 files changed, 363 insertions(+), 295 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/27038/2 -- To view, visit https://review.coreboot.org/27038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Gerrit-Change-Number: 27038 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: driver/spi/macronix.c: Add MX25L8005
by Arthur Heymans (Code Review) 13 Jun '18

13 Jun '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27040 Change subject: driver/spi/macronix.c: Add MX25L8005 ...................................................................... driver/spi/macronix.c: Add MX25L8005 Change-Id: I595198d66193c63f6c80c39371fbec10065d2165 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/spi/macronix.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27040/1 diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index b7f2c49..7ed70c0 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -56,6 +56,14 @@ static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { { + .idcode = 0x2014, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "MX25L8005", + }, + { .idcode = 0x2015, .page_size = 256, .pages_per_sector = 16, -- To view, visit https://review.coreboot.org/27040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I595198d66193c63f6c80c39371fbec10065d2165 Gerrit-Change-Number: 27040 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2018