coreboot-gerrit April 2018

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Change in coreboot[master]: mb/lenovo/x220: Allow optional use of the mrc.bin
by build bot (Jenkins) (Code Review) 22 Apr '18

22 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23489 ) Change subject: mb/lenovo/x220: Allow optional use of the mrc.bin ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70502/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24720/ : SUCCESS -- To view, visit https://review.coreboot.org/23489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602 Gerrit-Change-Number: 23489 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 22:15:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/atlas: Enable trackpad
by Furquan Shaikh (Code Review) 21 Apr '18

21 Apr '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/25759 ) Change subject: mb/google/poppy/atlas: Enable trackpad ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/25759/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/devicetree.cb: https://review.coreboot.org/#/c/25759/1/src/mainboard/google/poppy/variants… PS1, Line 256: register "wake" = "GPE0_DWx_19" not possible? Is the trackpad_int# routed to two SoC GPIOs? I don't see it in the gpio.c file. -- To view, visit https://review.coreboot.org/25759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Gerrit-Change-Number: 25759 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 12:27:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/emulation/qemu-i440fx/fw_cfg: fix checksum for ACPI tables
by Patrick Rudolph (Code Review) 21 Apr '18

21 Apr '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/25753 ) Change subject: mainboard/emulation/qemu-i440fx/fw_cfg: fix checksum for ACPI tables ...................................................................... Patch Set 1: Code-Review+2 Tested on qemu. -- To view, visit https://review.coreboot.org/25753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1fb29ef4e58982aab0c54b1f715c5658d2a663d8 Gerrit-Change-Number: 25753 Gerrit-PatchSet: 1 Gerrit-Owner: Oleksii Kurochko <oleksii.kurochko(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 12:00:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/atlas: Enable trackpad
by build bot (Jenkins) (Code Review) 21 Apr '18

21 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25759 ) Change subject: mb/google/poppy/atlas: Enable trackpad ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70478/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24696/ : SUCCESS -- To view, visit https://review.coreboot.org/25759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Gerrit-Change-Number: 25759 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 01:51:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/atlas: Enable trackpad
by Caveh Jalali (Code Review) 21 Apr '18

21 Apr '18

Hello caveh jalali, I'd like you to do a code review. Please visit https://review.coreboot.org/25759 to review the following change. Change subject: mb/google/poppy/atlas: Enable trackpad ...................................................................... mb/google/poppy/atlas: Enable trackpad This enables the i2c trackpad on atlas. BUG=b:75454415 TEST=able to move pointer using trackpad Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/25759/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 3d31c40..4444549 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -247,7 +247,17 @@ device pci 14.2 on end # Thermal Subsystem device pci 15.0 on end # I2C #0 - Touchscreen device pci 15.1 off end # I2C #1 - device pci 15.2 on end # I2C #2 - Trackpad + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A19_IRQ)" + # TODO(caveh): fix wake source + #register "wake" = "GPE0_DWx_19" not possible? + register "probed" = "1" # may not be present + device i2c 0x15 on end + end + end # I2C #2 - Trackpad device pci 15.3 on end # I2C #3 - Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 -- To view, visit https://review.coreboot.org/25759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If4a82aa605ec68fd38e52c13406eaf803f9e86cc Gerrit-Change-Number: 25759 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org>

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Change in coreboot[master]: vendorcode/intel: Update Geminilake FSP Header files
by build bot (Jenkins) (Code Review) 21 Apr '18

21 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25757 ) Change subject: vendorcode/intel: Update Geminilake FSP Header files ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70477/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24695/ : SUCCESS -- To view, visit https://review.coreboot.org/25757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Gerrit-Change-Number: 25757 Gerrit-PatchSet: 4 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 00:14:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: stoneyridge GPIO: Create and use PAD_INT for interrupt pins
by build bot (Jenkins) (Code Review) 21 Apr '18

21 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25758 ) Change subject: stoneyridge GPIO: Create and use PAD_INT for interrupt pins ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70475/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24694/ : SUCCESS -- To view, visit https://review.coreboot.org/25758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Gerrit-Change-Number: 25758 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 00:11:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/kahlee: Set SPI speed early
by Richard Spiegel (Code Review) 21 Apr '18

21 Apr '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/25756 ) Change subject: mainboard/google/kahlee: Set SPI speed early ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/25756/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25756/1//COMMIT_MSG@11 PS1, Line 11: of the TPM access for for the TPM access in? -- To view, visit https://review.coreboot.org/25756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c Gerrit-Change-Number: 25756 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Apr 2018 00:01:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: vendorcode/intel: Update Geminilake FSP Header files
by build bot (Jenkins) (Code Review) 21 Apr '18

21 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25757 ) Change subject: vendorcode/intel: Update Geminilake FSP Header files ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/70476/ : SUCCESS -- To view, visit https://review.coreboot.org/25757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Gerrit-Change-Number: 25757 Gerrit-PatchSet: 3 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 20 Apr 2018 23:57:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge GPIO: Create and use PAD_INT for interrupt pins
by Richard Spiegel (Code Review) 21 Apr '18

21 Apr '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25758 Change subject: stoneyridge GPIO: Create and use PAD_INT for interrupt pins ...................................................................... stoneyridge GPIO: Create and use PAD_INT for interrupt pins The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create a PAD_INT definition and change function sb_program_gpios() to accept the output from PAD_INT and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO programming. Remove code that reports GPIO configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 80 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25758/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 1eb18f1..9c41d95 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -36,11 +36,4 @@ { /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); - - /* Configure cr50 interrupt pin for use in polling tpm status */ - if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { - const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW | - GPIO_INT_STATUS_EN; - gpio_set_interrupt(H1_PCH_INT, flags); - } } diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 209d5ea..5a93fe3 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -30,16 +30,16 @@ PAD_GPO(GPIO_4, HIGH), /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - PAD_GPI(GPIO_6, PULL_UP), + PAD_INT(GPIO_6, EDGE_HIGH, PULL_UP), /* GPIO_9 - H1_PCH_INT_ODL, SCI */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_INT(GPIO_9, EDGE_LOW_STATUS, PULL_UP), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), /* GPIO_22 - EC_SCI_ODL, SCI */ - PAD_GPI(GPIO_22, PULL_UP), + PAD_INT(GPIO_22, EDGE_HIGH, PULL_UP), /* GPIO_26 - APU_PCIE_RST_L */ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), @@ -80,16 +80,16 @@ PAD_GPO(GPIO_4, HIGH), /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - PAD_GPI(GPIO_6, PULL_UP), + PAD_INT(GPIO_6, EDGE_HIGH, PULL_UP), /* GPIO_9 - H1_PCH_INT_ODL, SCI */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_INT(GPIO_9, EDGE_LOW_STATUS, PULL_UP), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), /* GPIO_22 - EC_SCI_ODL, SCI */ - PAD_GPI(GPIO_22, PULL_UP), + PAD_INT(GPIO_22, EDGE_HIGH, PULL_UP), /* GPIO_24 - EC_PCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), @@ -142,7 +142,7 @@ PAD_GPI(GPIO_3, PULL_UP), /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_5, PULL_UP), + PAD_INT(GPIO_5, EDGE_HIGH, PULL_UP), /* GPIO_7 - APU_PWROK_OD (currently not used) */ PAD_GPI(GPIO_7, PULL_UP), @@ -154,7 +154,7 @@ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_11, PULL_UP), + PAD_INT(GPIO_11, EDGE_HIGH, PULL_UP), /* GPIO_12 - Unused (TP126) */ PAD_GPI(GPIO_12, PULL_UP), @@ -163,7 +163,7 @@ PAD_GPI(GPIO_13, PULL_UP), /* GPIO_14 - APU_HP_INT_ODL, SCI */ - PAD_GPI(GPIO_14, PULL_UP), + PAD_INT(GPIO_14, EDGE_HIGH, PULL_UP), /* GPIO_16 - USB_C0_OC_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), @@ -181,7 +181,7 @@ PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), /* GPIO_21 - APU_PEN_INT_ODL, SCI */ - PAD_GPI(GPIO_21, PULL_UP), + PAD_INT(GPIO_21, EDGE_HIGH, PULL_UP), /* GPIO_24 - USB_A1_OC_ODL */ PAD_NF(GPIO_24, USB_OC3_L, PULL_UP), @@ -309,7 +309,7 @@ PAD_GPI(GPIO_3, PULL_UP), /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_5, PULL_UP), + PAD_INT(GPIO_5, EDGE_HIGH, PULL_UP), /* GPIO_7 - APU_PWROK_OD (currently not used) */ PAD_GPI(GPIO_7, PULL_UP), @@ -321,7 +321,7 @@ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ - PAD_GPI(GPIO_11, PULL_UP), + PAD_INT(GPIO_11, EDGE_HIGH, PULL_UP), /* GPIO_12 - EN_PP3300_TRACKPAD */ PAD_GPO(GPIO_12, HIGH), @@ -330,7 +330,7 @@ PAD_GPI(GPIO_13, PULL_UP), /* GPIO_14 - APU_HP_INT_ODL, SCI */ - PAD_GPI(GPIO_14, PULL_UP), + PAD_INT(GPIO_14, EDGE_HIGH, PULL_UP), /* GPIO_16 - USB_C0_OC_L */ PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), @@ -348,7 +348,7 @@ PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), /* GPIO_21 - APU_PEN_INT_ODL, SCI */ - PAD_GPI(GPIO_21, PULL_UP), + PAD_INT(GPIO_21, EDGE_HIGH, PULL_UP), /* GPIO_25 - SD_CD */ PAD_NF(GPIO_25, SD0_CD, PULL_UP), diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 0f7ec1b..b408ab2 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -335,6 +335,57 @@ #define GPIO_PULL_PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE #define GPIO_PULL_PULL_NONE 0 +/* + * Definitions for PAD_INT. It uses the fact that the register bit 16 + * (bit 0 of control) is the status of the pin(read-only) as a signal + * for the code to treat control differently. If bit 0 is set, control + * will be interpreted as: + * Bit 7 register bit 21 pull down + * Bit 6 register bit 20 pull up + * Bits 5-1 register bits 12-8 interrupt related bits. + */ +#define GPIO_INT_PULL_NONE 0x00 +#define GPIO_INT_PULL_UP 0x40 +#define GPIO_INT_PULL_DOWN 0x80 +#define GPIO_INT_EDGE_HIGH 0x00 +#define GPIO_INT_EDGE_LOW 0x04 +#define GPIO_INT_BOTH_EDGES 0x08 +#define GPIO_INT_LEVEL_HIGH 0x02 +#define GPIO_INT_LEVEL_LOW 0x06 +#define GPIO_INT_EDGE_HIGH 0x00 +#define GPIO_INT_EDGE_LOW 0x04 +#define GPIO_INT_BOTH_EDGES 0x08 +#define GPIO_INT_LEVEL_HIGH 0x02 +#define GPIO_INT_LEVEL_LOW 0x06 +#define GPIO_INT_EDGE_HIGH_STATUS 0x10 +#define GPIO_INT_EDGE_LOW_STATUS 0x14 +#define GPIO_INT_BOTH_EDGES_STATUS 0x18 +#define GPIO_INT_LEVEL_HIGH_STATUS 0x12 +#define GPIO_INT_LEVEL_LOW_STATUS 0x16 +#define GPIO_INT_EDGE_HIGH_DELIVER 0x20 +#define GPIO_INT_EDGE_LOW_DELIVER 0x24 +#define GPIO_INT_BOTH_EDGES_DELIVER 0x28 +#define GPIO_INT_LEVEL_HIGH_DELIVER 0x22 +#define GPIO_INT_LEVEL_LOW_DELIVER 0x26 +#define GPIO_INT_EDGE_HIGH_STATUS_DELIVER 0x30 +#define GPIO_INT_EDGE_LOW_STATUS_DELIVER 0x34 +#define GPIO_INT_BOTH_EDGES_STATUS_DELIVER 0x38 +#define GPIO_INT_LEVEL_HIGH_STATUS_DELIVER 0x32 +#define GPIO_INT_LEVEL_LOW_STATUS_DELIVER 0x36 +#define GPIO_INT_FLAG 0x01 +#define GPIO_INT_INT_MASK 0x3e +#define GPIO_INT_INT_NEG_SHIFT 1 +#define GPIO_INT_PULL_MASK 0xc0 +#define GPIO_INT_PULL_NEG_SHIFT 2 + +/* Auxiliary definition for PAD_INT */ +#define PAD_CONTROL(interrupt, pull) \ + (GPIO_INT ## _ ## interrupt | GPIO_INT ## _ ## pull) +/* General purpose interrupt pad configuration */ +#define PAD_INT(pin, interrupt, pull) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = PAD_CONTROL(interrupt, pull) | GPIO_INT_FLAG } /* Native function pad configuration */ #define PAD_NF(pin, func, pull) \ { .gpio = (pin), \ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a2a54c2..1f7ca0f 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -175,8 +175,8 @@ void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, size_t size) { - void *tmp_ptr; - uint8_t control, mux, index; + uint8_t *tmp_ptr; + uint8_t control, mux, index, interrupt, pull; for (index = 0; index < size; index++) { mux = gpio_ptr[index].function; @@ -186,11 +186,21 @@ /* * Get the address of AMD_GPIO_CONTROL (dword) relative - * to the desired pin and program bits 16-23. + * to the desired pin and point to bits 16-23. */ - tmp_ptr = (void *)(gpio_ptr[index].gpio * sizeof(uint32_t) + + tmp_ptr = (uint8_t *)(gpio_ptr[index].gpio * sizeof(uint32_t) + AMD_GPIO_CONTROL + 2); - write8(tmp_ptr, control); + if ((control & GPIO_INT_FLAG) == GPIO_INT_FLAG) { + /* here if PAD_INT generated control */ + interrupt = (control & GPIO_INT_INT_MASK) >> + GPIO_INT_INT_NEG_SHIFT; + pull = (control & GPIO_INT_PULL_MASK) >> + GPIO_INT_PULL_NEG_SHIFT; + write8(tmp_ptr, pull); /* pull goes to bits 16-23 */ + tmp_ptr--; /* Point bits 8 - 15. */ + write8(tmp_ptr, interrupt); + } else + write8(tmp_ptr, control); } } -- To view, visit https://review.coreboot.org/25758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Gerrit-Change-Number: 25758 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit April 2018